drivers/net/wireless/mediatek/mt76/mt7921/dma.c - linux - Git at Google

 // SPDX-License-Identifier: ISC
 /* Copyright (C) 2020 MediaTek Inc. */

 #include "mt7921.h"
 #include "../dma.h"
 #include "mac.h"

 int mt7921_init_tx_queues(struct mt7921_phy *phy, int idx, int n_desc)
 {
 	int i, err;

 	err = mt76_init_tx_queue(phy->mt76, 0, idx, n_desc, MT_TX_RING_BASE);
 	if (err < 0)
 		return err;

 	for (i = 0; i <= MT_TXQ_PSD; i++)
 		phy->mt76->q_tx[i] = phy->mt76->q_tx[0];

 	return 0;
 }

 static int mt7921_poll_tx(struct napi_struct *napi, int budget)
 {
 	struct mt7921_dev *dev;

 	dev = container_of(napi, struct mt7921_dev, mt76.tx_napi);

 	if (!mt76_connac_pm_ref(&dev->mphy, &dev->pm)) {
 		napi_complete(napi);
 		queue_work(dev->mt76.wq, &dev->pm.wake_work);
 		return 0;
 	}

 	mt7921_mcu_tx_cleanup(dev);
 	if (napi_complete(napi))
 		mt7921_irq_enable(dev, MT_INT_TX_DONE_ALL);
 	mt76_connac_pm_unref(&dev->mphy, &dev->pm);

 	return 0;
 }

 static int mt7921_poll_rx(struct napi_struct *napi, int budget)
 {
 	struct mt7921_dev *dev;
 	int done;

 	dev = container_of(napi->dev, struct mt7921_dev, mt76.napi_dev);

 	if (!mt76_connac_pm_ref(&dev->mphy, &dev->pm)) {
 		napi_complete(napi);
 		queue_work(dev->mt76.wq, &dev->pm.wake_work);
 		return 0;
 	}
 	done = mt76_dma_rx_poll(napi, budget);
 	mt76_connac_pm_unref(&dev->mphy, &dev->pm);

 	return done;
 }

 static void mt7921_dma_prefetch(struct mt7921_dev *dev)
 {
 #define PREFETCH(base, depth)	((base) << 16 | (depth))

 	mt76_wr(dev, MT_WFDMA0_RX_RING0_EXT_CTRL, PREFETCH(0x0, 0x4));
 	mt76_wr(dev, MT_WFDMA0_RX_RING2_EXT_CTRL, PREFETCH(0x40, 0x4));
 	mt76_wr(dev, MT_WFDMA0_RX_RING3_EXT_CTRL, PREFETCH(0x80, 0x4));
 	mt76_wr(dev, MT_WFDMA0_RX_RING4_EXT_CTRL, PREFETCH(0xc0, 0x4));
 	mt76_wr(dev, MT_WFDMA0_RX_RING5_EXT_CTRL, PREFETCH(0x100, 0x4));

 	mt76_wr(dev, MT_WFDMA0_TX_RING0_EXT_CTRL, PREFETCH(0x140, 0x4));
 	mt76_wr(dev, MT_WFDMA0_TX_RING1_EXT_CTRL, PREFETCH(0x180, 0x4));
 	mt76_wr(dev, MT_WFDMA0_TX_RING2_EXT_CTRL, PREFETCH(0x1c0, 0x4));
 	mt76_wr(dev, MT_WFDMA0_TX_RING3_EXT_CTRL, PREFETCH(0x200, 0x4));
 	mt76_wr(dev, MT_WFDMA0_TX_RING4_EXT_CTRL, PREFETCH(0x240, 0x4));
 	mt76_wr(dev, MT_WFDMA0_TX_RING5_EXT_CTRL, PREFETCH(0x280, 0x4));
 	mt76_wr(dev, MT_WFDMA0_TX_RING6_EXT_CTRL, PREFETCH(0x2c0, 0x4));
 	mt76_wr(dev, MT_WFDMA0_TX_RING16_EXT_CTRL, PREFETCH(0x340, 0x4));
 	mt76_wr(dev, MT_WFDMA0_TX_RING17_EXT_CTRL, PREFETCH(0x380, 0x4));
 }

 static u32 __mt7921_reg_addr(struct mt7921_dev *dev, u32 addr)
 {
 	static const struct {
 		u32 phys;
 		u32 mapped;
 		u32 size;
 	} fixed_map[] = {
 		{ 0x820d0000, 0x30000, 0x10000 }, /* WF_LMAC_TOP (WF_WTBLON) */
 		{ 0x820ed000, 0x24800, 0x0800 }, /* WF_LMAC_TOP BN0 (WF_MIB) */
 		{ 0x820e4000, 0x21000, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_TMAC) */
 		{ 0x820e7000, 0x21e00, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_DMA) */
 		{ 0x820eb000, 0x24200, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_LPON) */
 		{ 0x820e2000, 0x20800, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_AGG) */
 		{ 0x820e3000, 0x20c00, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_ARB) */
 		{ 0x820e5000, 0x21400, 0x0800 }, /* WF_LMAC_TOP BN0 (WF_RMAC) */
 		{ 0x00400000, 0x80000, 0x10000 }, /* WF_MCU_SYSRAM */
 		{ 0x00410000, 0x90000, 0x10000 }, /* WF_MCU_SYSRAM (configure register) */
 		{ 0x40000000, 0x70000, 0x10000 }, /* WF_UMAC_SYSRAM */
 		{ 0x54000000, 0x02000, 0x1000 }, /* WFDMA PCIE0 MCU DMA0 */
 		{ 0x55000000, 0x03000, 0x1000 }, /* WFDMA PCIE0 MCU DMA1 */
 		{ 0x58000000, 0x06000, 0x1000 }, /* WFDMA PCIE1 MCU DMA0 (MEM_DMA) */
 		{ 0x59000000, 0x07000, 0x1000 }, /* WFDMA PCIE1 MCU DMA1 */
 		{ 0x7c000000, 0xf0000, 0x10000 }, /* CONN_INFRA */
 		{ 0x7c020000, 0xd0000, 0x10000 }, /* CONN_INFRA, WFDMA */
 		{ 0x7c060000, 0xe0000, 0x10000 }, /* CONN_INFRA, conn_host_csr_top */
 		{ 0x80020000, 0xb0000, 0x10000 }, /* WF_TOP_MISC_OFF */
 		{ 0x81020000, 0xc0000, 0x10000 }, /* WF_TOP_MISC_ON */
 		{ 0x820c0000, 0x08000, 0x4000 }, /* WF_UMAC_TOP (PLE) */
 		{ 0x820c8000, 0x0c000, 0x2000 }, /* WF_UMAC_TOP (PSE) */
 		{ 0x820cc000, 0x0e000, 0x1000 }, /* WF_UMAC_TOP (PP) */
 		{ 0x820cd000, 0x0f000, 0x1000 }, /* WF_MDP_TOP */
 		{ 0x820ce000, 0x21c00, 0x0200 }, /* WF_LMAC_TOP (WF_SEC) */
 		{ 0x820cf000, 0x22000, 0x1000 }, /* WF_LMAC_TOP (WF_PF) */
 		{ 0x820e0000, 0x20000, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_CFG) */
 		{ 0x820e1000, 0x20400, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_TRB) */
 		{ 0x820e9000, 0x23400, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_WTBLOFF) */
 		{ 0x820ea000, 0x24000, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_ETBF) */
 		{ 0x820ec000, 0x24600, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_INT) */
 		{ 0x820f0000, 0xa0000, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_CFG) */
 		{ 0x820f1000, 0xa0600, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_TRB) */
 		{ 0x820f2000, 0xa0800, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_AGG) */
 		{ 0x820f3000, 0xa0c00, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_ARB) */
 		{ 0x820f4000, 0xa1000, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_TMAC) */
 		{ 0x820f5000, 0xa1400, 0x0800 }, /* WF_LMAC_TOP BN1 (WF_RMAC) */
 		{ 0x820f7000, 0xa1e00, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_DMA) */
 		{ 0x820f9000, 0xa3400, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_WTBLOFF) */
 		{ 0x820fa000, 0xa4000, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_ETBF) */
 		{ 0x820fb000, 0xa4200, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_LPON) */
 		{ 0x820fc000, 0xa4600, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_INT) */
 		{ 0x820fd000, 0xa4800, 0x0800 }, /* WF_LMAC_TOP BN1 (WF_MIB) */
 	};
 	int i;

 	if (addr < 0x100000)
 		return addr;

 	for (i = 0; i < ARRAY_SIZE(fixed_map); i++) {
 		u32 ofs;

 		if (addr < fixed_map[i].phys)
 			continue;

 		ofs = addr - fixed_map[i].phys;
 		if (ofs > fixed_map[i].size)
 			continue;

 		return fixed_map[i].mapped + ofs;
 	}

 	if ((addr >= 0x18000000 && addr < 0x18c00000) ||
 	    (addr >= 0x70000000 && addr < 0x78000000) ||
 	    (addr >= 0x7c000000 && addr < 0x7c400000))
 		return mt7921_reg_map_l1(dev, addr);

 	dev_err(dev->mt76.dev, "Access currently unsupported address %08x\n",
 		addr);

 	return 0;
 }

 static u32 mt7921_rr(struct mt76_dev *mdev, u32 offset)
 {
 	struct mt7921_dev *dev = container_of(mdev, struct mt7921_dev, mt76);
 	u32 addr = __mt7921_reg_addr(dev, offset);

 	return dev->bus_ops->rr(mdev, addr);
 }

 static void mt7921_wr(struct mt76_dev *mdev, u32 offset, u32 val)
 {
 	struct mt7921_dev *dev = container_of(mdev, struct mt7921_dev, mt76);
 	u32 addr = __mt7921_reg_addr(dev, offset);

 	dev->bus_ops->wr(mdev, addr, val);
 }

 static u32 mt7921_rmw(struct mt76_dev *mdev, u32 offset, u32 mask, u32 val)
 {
 	struct mt7921_dev *dev = container_of(mdev, struct mt7921_dev, mt76);
 	u32 addr = __mt7921_reg_addr(dev, offset);

 	return dev->bus_ops->rmw(mdev, addr, mask, val);
 }

 static int mt7921_dma_disable(struct mt7921_dev *dev, bool force)
 {
 	if (force) {
 		/* reset */
 		mt76_clear(dev, MT_WFDMA0_RST,
 			   MT_WFDMA0_RST_DMASHDL_ALL_RST |
 			   MT_WFDMA0_RST_LOGIC_RST);

 		mt76_set(dev, MT_WFDMA0_RST,
 			 MT_WFDMA0_RST_DMASHDL_ALL_RST |
 			 MT_WFDMA0_RST_LOGIC_RST);
 	}

 	/* disable dmashdl */
 	mt76_clear(dev, MT_WFDMA0_GLO_CFG_EXT0,
 		   MT_WFDMA0_CSR_TX_DMASHDL_ENABLE);
 	mt76_set(dev, MT_DMASHDL_SW_CONTROL, MT_DMASHDL_DMASHDL_BYPASS);

 	/* disable WFDMA0 */
 	mt76_clear(dev, MT_WFDMA0_GLO_CFG,
 		   MT_WFDMA0_GLO_CFG_TX_DMA_EN | MT_WFDMA0_GLO_CFG_RX_DMA_EN |
 		   MT_WFDMA0_GLO_CFG_CSR_DISP_BASE_PTR_CHAIN_EN |
 		   MT_WFDMA0_GLO_CFG_OMIT_TX_INFO |
 		   MT_WFDMA0_GLO_CFG_OMIT_RX_INFO |
 		   MT_WFDMA0_GLO_CFG_OMIT_RX_INFO_PFET2);

 	if (!mt76_poll(dev, MT_WFDMA0_GLO_CFG,
 		       MT_WFDMA0_GLO_CFG_TX_DMA_BUSY |
 		       MT_WFDMA0_GLO_CFG_RX_DMA_BUSY, 0, 1000))
 		return -ETIMEDOUT;

 	return 0;
 }

 static int mt7921_dma_enable(struct mt7921_dev *dev)
 {
 	/* configure perfetch settings */
 	mt7921_dma_prefetch(dev);

 	/* reset dma idx */
 	mt76_wr(dev, MT_WFDMA0_RST_DTX_PTR, ~0);

 	/* configure delay interrupt */
 	mt76_wr(dev, MT_WFDMA0_PRI_DLY_INT_CFG0, 0);

 	mt76_set(dev, MT_WFDMA0_GLO_CFG,
 		 MT_WFDMA0_GLO_CFG_TX_WB_DDONE |
 		 MT_WFDMA0_GLO_CFG_FIFO_LITTLE_ENDIAN |
 		 MT_WFDMA0_GLO_CFG_CLK_GAT_DIS |
 		 MT_WFDMA0_GLO_CFG_OMIT_TX_INFO |
 		 MT_WFDMA0_GLO_CFG_CSR_DISP_BASE_PTR_CHAIN_EN |
 		 MT_WFDMA0_GLO_CFG_OMIT_RX_INFO_PFET2);

 	mt76_set(dev, MT_WFDMA0_GLO_CFG,
 		 MT_WFDMA0_GLO_CFG_TX_DMA_EN | MT_WFDMA0_GLO_CFG_RX_DMA_EN);

 	mt76_set(dev, MT_WFDMA_DUMMY_CR, MT_WFDMA_NEED_REINIT);

 	/* enable interrupts for TX/RX rings */
 	mt7921_irq_enable(dev,
 			  MT_INT_RX_DONE_ALL | MT_INT_TX_DONE_ALL |
 			  MT_INT_MCU_CMD);
 	mt76_set(dev, MT_MCU2HOST_SW_INT_ENA, MT_MCU_CMD_WAKE_RX_PCIE);

 	return 0;
 }

 static int mt7921_dma_reset(struct mt7921_dev *dev, bool force)
 {
 	int i, err;

 	err = mt7921_dma_disable(dev, force);
 	if (err)
 		return err;

 	/* reset hw queues */
 	for (i = 0; i < __MT_TXQ_MAX; i++)
 		mt76_queue_reset(dev, dev->mphy.q_tx[i]);

 	for (i = 0; i < __MT_MCUQ_MAX; i++)
 		mt76_queue_reset(dev, dev->mt76.q_mcu[i]);

 	mt76_for_each_q_rx(&dev->mt76, i)
 		mt76_queue_reset(dev, &dev->mt76.q_rx[i]);

 	mt76_tx_status_check(&dev->mt76, true);

 	return mt7921_dma_enable(dev);
 }

 int mt7921_wfsys_reset(struct mt7921_dev *dev)
 {
 	mt76_clear(dev, MT_WFSYS_SW_RST_B, WFSYS_SW_RST_B);
 	msleep(50);
 	mt76_set(dev, MT_WFSYS_SW_RST_B, WFSYS_SW_RST_B);

 	if (!__mt76_poll_msec(&dev->mt76, MT_WFSYS_SW_RST_B,
 			      WFSYS_SW_INIT_DONE, WFSYS_SW_INIT_DONE, 500))
 		return -ETIMEDOUT;

 	return 0;
 }

 int mt7921_wpdma_reset(struct mt7921_dev *dev, bool force)
 {
 	int i, err;

 	/* clean up hw queues */
 	for (i = 0; i < ARRAY_SIZE(dev->mt76.phy.q_tx); i++)
 		mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[i], true);

 	for (i = 0; i < ARRAY_SIZE(dev->mt76.q_mcu); i++)
 		mt76_queue_tx_cleanup(dev, dev->mt76.q_mcu[i], true);

 	mt76_for_each_q_rx(&dev->mt76, i)
 		mt76_queue_rx_cleanup(dev, &dev->mt76.q_rx[i]);

 	if (force) {
 		err = mt7921_wfsys_reset(dev);
 		if (err)
 			return err;
 	}
 	err = mt7921_dma_reset(dev, force);
 	if (err)
 		return err;

 	mt76_for_each_q_rx(&dev->mt76, i)
 		mt76_queue_rx_reset(dev, i);

 	return 0;
 }

 int mt7921_wpdma_reinit_cond(struct mt7921_dev *dev)
 {
 	struct mt76_connac_pm *pm = &dev->pm;
 	int err;

 	/* check if the wpdma must be reinitialized */
 	if (mt7921_dma_need_reinit(dev)) {
 		/* disable interrutpts */
 		mt76_wr(dev, MT_WFDMA0_HOST_INT_ENA, 0);
 		mt76_wr(dev, MT_PCIE_MAC_INT_ENABLE, 0x0);

 		err = mt7921_wpdma_reset(dev, false);
 		if (err) {
 			dev_err(dev->mt76.dev, "wpdma reset failed\n");
 			return err;
 		}

 		/* enable interrutpts */
 		mt76_wr(dev, MT_PCIE_MAC_INT_ENABLE, 0xff);
 		pm->stats.lp_wake++;
 	}

 	return 0;
 }

 int mt7921_dma_init(struct mt7921_dev *dev)
 {
 	struct mt76_bus_ops *bus_ops;
 	int ret;

 	dev->phy.dev = dev;
 	dev->phy.mt76 = &dev->mt76.phy;
 	dev->mt76.phy.priv = &dev->phy;
 	dev->bus_ops = dev->mt76.bus;
 	bus_ops = devm_kmemdup(dev->mt76.dev, dev->bus_ops, sizeof(*bus_ops),
 			       GFP_KERNEL);
 	if (!bus_ops)
 		return -ENOMEM;

 	bus_ops->rr = mt7921_rr;
 	bus_ops->wr = mt7921_wr;
 	bus_ops->rmw = mt7921_rmw;
 	dev->mt76.bus = bus_ops;

 	mt76_dma_attach(&dev->mt76);

 	ret = mt7921_dma_disable(dev, true);
 	if (ret)
 		return ret;

 	ret = mt7921_wfsys_reset(dev);
 	if (ret)
 		return ret;

 	/* init tx queue */
 	ret = mt7921_init_tx_queues(&dev->phy, MT7921_TXQ_BAND0,
 				    MT7921_TX_RING_SIZE);
 	if (ret)
 		return ret;

 	mt76_wr(dev, MT_WFDMA0_TX_RING0_EXT_CTRL, 0x4);

 	/* command to WM */
 	ret = mt76_init_mcu_queue(&dev->mt76, MT_MCUQ_WM, MT7921_TXQ_MCU_WM,
 				  MT7921_TX_MCU_RING_SIZE, MT_TX_RING_BASE);
 	if (ret)
 		return ret;

 	/* firmware download */
 	ret = mt76_init_mcu_queue(&dev->mt76, MT_MCUQ_FWDL, MT7921_TXQ_FWDL,
 				  MT7921_TX_FWDL_RING_SIZE, MT_TX_RING_BASE);
 	if (ret)
 		return ret;

 	/* event from WM before firmware download */
 	ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MCU],
 			       MT7921_RXQ_MCU_WM,
 			       MT7921_RX_MCU_RING_SIZE,
 			       MT_RX_BUF_SIZE, MT_RX_EVENT_RING_BASE);
 	if (ret)
 		return ret;

 	/* Change mcu queue after firmware download */
 	ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MCU_WA],
 			       MT7921_RXQ_MCU_WM,
 			       MT7921_RX_MCU_RING_SIZE,
 			       MT_RX_BUF_SIZE, MT_WFDMA0(0x540));
 	if (ret)
 		return ret;

 	/* rx data */
 	ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MAIN],
 			       MT7921_RXQ_BAND0, MT7921_RX_RING_SIZE,
 			       MT_RX_BUF_SIZE, MT_RX_DATA_RING_BASE);
 	if (ret)
 		return ret;

 	ret = mt76_init_queues(dev, mt7921_poll_rx);
 	if (ret < 0)
 		return ret;

 	netif_tx_napi_add(&dev->mt76.tx_napi_dev, &dev->mt76.tx_napi,
 			  mt7921_poll_tx, NAPI_POLL_WEIGHT);
 	napi_enable(&dev->mt76.tx_napi);

 	return mt7921_dma_enable(dev);
 }

 void mt7921_dma_cleanup(struct mt7921_dev *dev)
 {
 	/* disable */
 	mt76_clear(dev, MT_WFDMA0_GLO_CFG,
 		   MT_WFDMA0_GLO_CFG_TX_DMA_EN |
 		   MT_WFDMA0_GLO_CFG_RX_DMA_EN |
 		   MT_WFDMA0_GLO_CFG_CSR_DISP_BASE_PTR_CHAIN_EN |
 		   MT_WFDMA0_GLO_CFG_OMIT_TX_INFO |
 		   MT_WFDMA0_GLO_CFG_OMIT_RX_INFO |
 		   MT_WFDMA0_GLO_CFG_OMIT_RX_INFO_PFET2);

 	/* reset */
 	mt76_clear(dev, MT_WFDMA0_RST,
 		   MT_WFDMA0_RST_DMASHDL_ALL_RST |
 		   MT_WFDMA0_RST_LOGIC_RST);

 	mt76_set(dev, MT_WFDMA0_RST,
 		 MT_WFDMA0_RST_DMASHDL_ALL_RST |
 		 MT_WFDMA0_RST_LOGIC_RST);

 	mt76_dma_cleanup(&dev->mt76);
 }
	// SPDX-License-Identifier: ISC
	/* Copyright (C) 2020 MediaTek Inc. */

	#include "mt7921.h"
	#include "../dma.h"
	#include "mac.h"

	int mt7921_init_tx_queues(struct mt7921_phy *phy, int idx, int n_desc)
	{
	int i, err;

	err = mt76_init_tx_queue(phy->mt76, 0, idx, n_desc, MT_TX_RING_BASE);
	if (err < 0)
	return err;

	for (i = 0; i <= MT_TXQ_PSD; i++)
	phy->mt76->q_tx[i] = phy->mt76->q_tx[0];

	return 0;
	}

	static int mt7921_poll_tx(struct napi_struct *napi, int budget)
	{
	struct mt7921_dev *dev;

	dev = container_of(napi, struct mt7921_dev, mt76.tx_napi);

	if (!mt76_connac_pm_ref(&dev->mphy, &dev->pm)) {
	napi_complete(napi);
	queue_work(dev->mt76.wq, &dev->pm.wake_work);
	return 0;
	}

	mt7921_mcu_tx_cleanup(dev);
	if (napi_complete(napi))
	mt7921_irq_enable(dev, MT_INT_TX_DONE_ALL);
	mt76_connac_pm_unref(&dev->mphy, &dev->pm);

	return 0;
	}

	static int mt7921_poll_rx(struct napi_struct *napi, int budget)
	{
	struct mt7921_dev *dev;
	int done;

	dev = container_of(napi->dev, struct mt7921_dev, mt76.napi_dev);

	if (!mt76_connac_pm_ref(&dev->mphy, &dev->pm)) {
	napi_complete(napi);
	queue_work(dev->mt76.wq, &dev->pm.wake_work);
	return 0;
	}
	done = mt76_dma_rx_poll(napi, budget);
	mt76_connac_pm_unref(&dev->mphy, &dev->pm);

	return done;
	}

	static void mt7921_dma_prefetch(struct mt7921_dev *dev)
	{
	#define PREFETCH(base, depth) ((base) << 16 \| (depth))

	mt76_wr(dev, MT_WFDMA0_RX_RING0_EXT_CTRL, PREFETCH(0x0, 0x4));
	mt76_wr(dev, MT_WFDMA0_RX_RING2_EXT_CTRL, PREFETCH(0x40, 0x4));
	mt76_wr(dev, MT_WFDMA0_RX_RING3_EXT_CTRL, PREFETCH(0x80, 0x4));
	mt76_wr(dev, MT_WFDMA0_RX_RING4_EXT_CTRL, PREFETCH(0xc0, 0x4));
	mt76_wr(dev, MT_WFDMA0_RX_RING5_EXT_CTRL, PREFETCH(0x100, 0x4));

	mt76_wr(dev, MT_WFDMA0_TX_RING0_EXT_CTRL, PREFETCH(0x140, 0x4));
	mt76_wr(dev, MT_WFDMA0_TX_RING1_EXT_CTRL, PREFETCH(0x180, 0x4));
	mt76_wr(dev, MT_WFDMA0_TX_RING2_EXT_CTRL, PREFETCH(0x1c0, 0x4));
	mt76_wr(dev, MT_WFDMA0_TX_RING3_EXT_CTRL, PREFETCH(0x200, 0x4));
	mt76_wr(dev, MT_WFDMA0_TX_RING4_EXT_CTRL, PREFETCH(0x240, 0x4));
	mt76_wr(dev, MT_WFDMA0_TX_RING5_EXT_CTRL, PREFETCH(0x280, 0x4));
	mt76_wr(dev, MT_WFDMA0_TX_RING6_EXT_CTRL, PREFETCH(0x2c0, 0x4));
	mt76_wr(dev, MT_WFDMA0_TX_RING16_EXT_CTRL, PREFETCH(0x340, 0x4));
	mt76_wr(dev, MT_WFDMA0_TX_RING17_EXT_CTRL, PREFETCH(0x380, 0x4));
	}

	static u32 __mt7921_reg_addr(struct mt7921_dev *dev, u32 addr)
	{
	static const struct {
	u32 phys;
	u32 mapped;
	u32 size;
	} fixed_map[] = {
	{ 0x820d0000, 0x30000, 0x10000 }, /* WF_LMAC_TOP (WF_WTBLON) */
	{ 0x820ed000, 0x24800, 0x0800 }, /* WF_LMAC_TOP BN0 (WF_MIB) */
	{ 0x820e4000, 0x21000, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_TMAC) */
	{ 0x820e7000, 0x21e00, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_DMA) */
	{ 0x820eb000, 0x24200, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_LPON) */
	{ 0x820e2000, 0x20800, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_AGG) */
	{ 0x820e3000, 0x20c00, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_ARB) */
	{ 0x820e5000, 0x21400, 0x0800 }, /* WF_LMAC_TOP BN0 (WF_RMAC) */
	{ 0x00400000, 0x80000, 0x10000 }, /* WF_MCU_SYSRAM */
	{ 0x00410000, 0x90000, 0x10000 }, /* WF_MCU_SYSRAM (configure register) */
	{ 0x40000000, 0x70000, 0x10000 }, /* WF_UMAC_SYSRAM */
	{ 0x54000000, 0x02000, 0x1000 }, /* WFDMA PCIE0 MCU DMA0 */
	{ 0x55000000, 0x03000, 0x1000 }, /* WFDMA PCIE0 MCU DMA1 */
	{ 0x58000000, 0x06000, 0x1000 }, /* WFDMA PCIE1 MCU DMA0 (MEM_DMA) */
	{ 0x59000000, 0x07000, 0x1000 }, /* WFDMA PCIE1 MCU DMA1 */
	{ 0x7c000000, 0xf0000, 0x10000 }, /* CONN_INFRA */
	{ 0x7c020000, 0xd0000, 0x10000 }, /* CONN_INFRA, WFDMA */
	{ 0x7c060000, 0xe0000, 0x10000 }, /* CONN_INFRA, conn_host_csr_top */
	{ 0x80020000, 0xb0000, 0x10000 }, /* WF_TOP_MISC_OFF */
	{ 0x81020000, 0xc0000, 0x10000 }, /* WF_TOP_MISC_ON */
	{ 0x820c0000, 0x08000, 0x4000 }, /* WF_UMAC_TOP (PLE) */
	{ 0x820c8000, 0x0c000, 0x2000 }, /* WF_UMAC_TOP (PSE) */
	{ 0x820cc000, 0x0e000, 0x1000 }, /* WF_UMAC_TOP (PP) */
	{ 0x820cd000, 0x0f000, 0x1000 }, /* WF_MDP_TOP */
	{ 0x820ce000, 0x21c00, 0x0200 }, /* WF_LMAC_TOP (WF_SEC) */
	{ 0x820cf000, 0x22000, 0x1000 }, /* WF_LMAC_TOP (WF_PF) */
	{ 0x820e0000, 0x20000, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_CFG) */
	{ 0x820e1000, 0x20400, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_TRB) */
	{ 0x820e9000, 0x23400, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_WTBLOFF) */
	{ 0x820ea000, 0x24000, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_ETBF) */
	{ 0x820ec000, 0x24600, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_INT) */
	{ 0x820f0000, 0xa0000, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_CFG) */
	{ 0x820f1000, 0xa0600, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_TRB) */
	{ 0x820f2000, 0xa0800, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_AGG) */
	{ 0x820f3000, 0xa0c00, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_ARB) */
	{ 0x820f4000, 0xa1000, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_TMAC) */
	{ 0x820f5000, 0xa1400, 0x0800 }, /* WF_LMAC_TOP BN1 (WF_RMAC) */
	{ 0x820f7000, 0xa1e00, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_DMA) */
	{ 0x820f9000, 0xa3400, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_WTBLOFF) */
	{ 0x820fa000, 0xa4000, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_ETBF) */
	{ 0x820fb000, 0xa4200, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_LPON) */
	{ 0x820fc000, 0xa4600, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_INT) */
	{ 0x820fd000, 0xa4800, 0x0800 }, /* WF_LMAC_TOP BN1 (WF_MIB) */
	};
	int i;

	if (addr < 0x100000)
	return addr;

	for (i = 0; i < ARRAY_SIZE(fixed_map); i++) {
	u32 ofs;

	if (addr < fixed_map[i].phys)
	continue;

	ofs = addr - fixed_map[i].phys;
	if (ofs > fixed_map[i].size)
	continue;

	return fixed_map[i].mapped + ofs;
	}

	if ((addr >= 0x18000000 && addr < 0x18c00000) \|\|
	(addr >= 0x70000000 && addr < 0x78000000) \|\|
	(addr >= 0x7c000000 && addr < 0x7c400000))
	return mt7921_reg_map_l1(dev, addr);

	dev_err(dev->mt76.dev, "Access currently unsupported address %08x\n",
	addr);

	return 0;
	}

	static u32 mt7921_rr(struct mt76_dev *mdev, u32 offset)
	{
	struct mt7921_dev *dev = container_of(mdev, struct mt7921_dev, mt76);
	u32 addr = __mt7921_reg_addr(dev, offset);

	return dev->bus_ops->rr(mdev, addr);
	}

	static void mt7921_wr(struct mt76_dev *mdev, u32 offset, u32 val)
	{
	struct mt7921_dev *dev = container_of(mdev, struct mt7921_dev, mt76);
	u32 addr = __mt7921_reg_addr(dev, offset);

	dev->bus_ops->wr(mdev, addr, val);
	}

	static u32 mt7921_rmw(struct mt76_dev *mdev, u32 offset, u32 mask, u32 val)
	{
	struct mt7921_dev *dev = container_of(mdev, struct mt7921_dev, mt76);
	u32 addr = __mt7921_reg_addr(dev, offset);

	return dev->bus_ops->rmw(mdev, addr, mask, val);
	}

	static int mt7921_dma_disable(struct mt7921_dev *dev, bool force)
	{
	if (force) {
	/* reset */
	mt76_clear(dev, MT_WFDMA0_RST,
	MT_WFDMA0_RST_DMASHDL_ALL_RST \|
	MT_WFDMA0_RST_LOGIC_RST);

	mt76_set(dev, MT_WFDMA0_RST,
	MT_WFDMA0_RST_DMASHDL_ALL_RST \|
	MT_WFDMA0_RST_LOGIC_RST);
	}

	/* disable dmashdl */
	mt76_clear(dev, MT_WFDMA0_GLO_CFG_EXT0,
	MT_WFDMA0_CSR_TX_DMASHDL_ENABLE);
	mt76_set(dev, MT_DMASHDL_SW_CONTROL, MT_DMASHDL_DMASHDL_BYPASS);

	/* disable WFDMA0 */
	mt76_clear(dev, MT_WFDMA0_GLO_CFG,
	MT_WFDMA0_GLO_CFG_TX_DMA_EN \| MT_WFDMA0_GLO_CFG_RX_DMA_EN \|
	MT_WFDMA0_GLO_CFG_CSR_DISP_BASE_PTR_CHAIN_EN \|
	MT_WFDMA0_GLO_CFG_OMIT_TX_INFO \|
	MT_WFDMA0_GLO_CFG_OMIT_RX_INFO \|
	MT_WFDMA0_GLO_CFG_OMIT_RX_INFO_PFET2);

	if (!mt76_poll(dev, MT_WFDMA0_GLO_CFG,
	MT_WFDMA0_GLO_CFG_TX_DMA_BUSY \|
	MT_WFDMA0_GLO_CFG_RX_DMA_BUSY, 0, 1000))
	return -ETIMEDOUT;

	return 0;
	}

	static int mt7921_dma_enable(struct mt7921_dev *dev)
	{
	/* configure perfetch settings */
	mt7921_dma_prefetch(dev);

	/* reset dma idx */
	mt76_wr(dev, MT_WFDMA0_RST_DTX_PTR, ~0);

	/* configure delay interrupt */
	mt76_wr(dev, MT_WFDMA0_PRI_DLY_INT_CFG0, 0);

	mt76_set(dev, MT_WFDMA0_GLO_CFG,
	MT_WFDMA0_GLO_CFG_TX_WB_DDONE \|
	MT_WFDMA0_GLO_CFG_FIFO_LITTLE_ENDIAN \|
	MT_WFDMA0_GLO_CFG_CLK_GAT_DIS \|
	MT_WFDMA0_GLO_CFG_OMIT_TX_INFO \|
	MT_WFDMA0_GLO_CFG_CSR_DISP_BASE_PTR_CHAIN_EN \|
	MT_WFDMA0_GLO_CFG_OMIT_RX_INFO_PFET2);

	mt76_set(dev, MT_WFDMA0_GLO_CFG,
	MT_WFDMA0_GLO_CFG_TX_DMA_EN \| MT_WFDMA0_GLO_CFG_RX_DMA_EN);

	mt76_set(dev, MT_WFDMA_DUMMY_CR, MT_WFDMA_NEED_REINIT);

	/* enable interrupts for TX/RX rings */
	mt7921_irq_enable(dev,
	MT_INT_RX_DONE_ALL \| MT_INT_TX_DONE_ALL \|
	MT_INT_MCU_CMD);
	mt76_set(dev, MT_MCU2HOST_SW_INT_ENA, MT_MCU_CMD_WAKE_RX_PCIE);

	return 0;
	}

	static int mt7921_dma_reset(struct mt7921_dev *dev, bool force)
	{
	int i, err;

	err = mt7921_dma_disable(dev, force);
	if (err)
	return err;

	/* reset hw queues */
	for (i = 0; i < __MT_TXQ_MAX; i++)
	mt76_queue_reset(dev, dev->mphy.q_tx[i]);

	for (i = 0; i < __MT_MCUQ_MAX; i++)
	mt76_queue_reset(dev, dev->mt76.q_mcu[i]);

	mt76_for_each_q_rx(&dev->mt76, i)
	mt76_queue_reset(dev, &dev->mt76.q_rx[i]);

	mt76_tx_status_check(&dev->mt76, true);

	return mt7921_dma_enable(dev);
	}

	int mt7921_wfsys_reset(struct mt7921_dev *dev)
	{
	mt76_clear(dev, MT_WFSYS_SW_RST_B, WFSYS_SW_RST_B);
	msleep(50);
	mt76_set(dev, MT_WFSYS_SW_RST_B, WFSYS_SW_RST_B);

	if (!__mt76_poll_msec(&dev->mt76, MT_WFSYS_SW_RST_B,
	WFSYS_SW_INIT_DONE, WFSYS_SW_INIT_DONE, 500))
	return -ETIMEDOUT;

	return 0;
	}

	int mt7921_wpdma_reset(struct mt7921_dev *dev, bool force)
	{
	int i, err;

	/* clean up hw queues */
	for (i = 0; i < ARRAY_SIZE(dev->mt76.phy.q_tx); i++)
	mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[i], true);

	for (i = 0; i < ARRAY_SIZE(dev->mt76.q_mcu); i++)
	mt76_queue_tx_cleanup(dev, dev->mt76.q_mcu[i], true);

	mt76_for_each_q_rx(&dev->mt76, i)
	mt76_queue_rx_cleanup(dev, &dev->mt76.q_rx[i]);

	if (force) {
	err = mt7921_wfsys_reset(dev);
	if (err)
	return err;
	}
	err = mt7921_dma_reset(dev, force);
	if (err)
	return err;

	mt76_for_each_q_rx(&dev->mt76, i)
	mt76_queue_rx_reset(dev, i);

	return 0;
	}

	int mt7921_wpdma_reinit_cond(struct mt7921_dev *dev)
	{
	struct mt76_connac_pm *pm = &dev->pm;
	int err;

	/* check if the wpdma must be reinitialized */
	if (mt7921_dma_need_reinit(dev)) {
	/* disable interrutpts */
	mt76_wr(dev, MT_WFDMA0_HOST_INT_ENA, 0);
	mt76_wr(dev, MT_PCIE_MAC_INT_ENABLE, 0x0);

	err = mt7921_wpdma_reset(dev, false);
	if (err) {
	dev_err(dev->mt76.dev, "wpdma reset failed\n");
	return err;
	}

	/* enable interrutpts */
	mt76_wr(dev, MT_PCIE_MAC_INT_ENABLE, 0xff);
	pm->stats.lp_wake++;
	}

	return 0;
	}

	int mt7921_dma_init(struct mt7921_dev *dev)
	{
	struct mt76_bus_ops *bus_ops;
	int ret;

	dev->phy.dev = dev;
	dev->phy.mt76 = &dev->mt76.phy;
	dev->mt76.phy.priv = &dev->phy;
	dev->bus_ops = dev->mt76.bus;
	bus_ops = devm_kmemdup(dev->mt76.dev, dev->bus_ops, sizeof(*bus_ops),
	GFP_KERNEL);
	if (!bus_ops)
	return -ENOMEM;

	bus_ops->rr = mt7921_rr;
	bus_ops->wr = mt7921_wr;
	bus_ops->rmw = mt7921_rmw;
	dev->mt76.bus = bus_ops;

	mt76_dma_attach(&dev->mt76);

	ret = mt7921_dma_disable(dev, true);
	if (ret)
	return ret;

	ret = mt7921_wfsys_reset(dev);
	if (ret)
	return ret;

	/* init tx queue */
	ret = mt7921_init_tx_queues(&dev->phy, MT7921_TXQ_BAND0,
	MT7921_TX_RING_SIZE);
	if (ret)
	return ret;

	mt76_wr(dev, MT_WFDMA0_TX_RING0_EXT_CTRL, 0x4);

	/* command to WM */
	ret = mt76_init_mcu_queue(&dev->mt76, MT_MCUQ_WM, MT7921_TXQ_MCU_WM,
	MT7921_TX_MCU_RING_SIZE, MT_TX_RING_BASE);
	if (ret)
	return ret;

	/* firmware download */
	ret = mt76_init_mcu_queue(&dev->mt76, MT_MCUQ_FWDL, MT7921_TXQ_FWDL,
	MT7921_TX_FWDL_RING_SIZE, MT_TX_RING_BASE);
	if (ret)
	return ret;

	/* event from WM before firmware download */
	ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MCU],
	MT7921_RXQ_MCU_WM,
	MT7921_RX_MCU_RING_SIZE,
	MT_RX_BUF_SIZE, MT_RX_EVENT_RING_BASE);
	if (ret)
	return ret;

	/* Change mcu queue after firmware download */
	ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MCU_WA],
	MT7921_RXQ_MCU_WM,
	MT7921_RX_MCU_RING_SIZE,
	MT_RX_BUF_SIZE, MT_WFDMA0(0x540));
	if (ret)
	return ret;

	/* rx data */
	ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MAIN],
	MT7921_RXQ_BAND0, MT7921_RX_RING_SIZE,
	MT_RX_BUF_SIZE, MT_RX_DATA_RING_BASE);
	if (ret)
	return ret;

	ret = mt76_init_queues(dev, mt7921_poll_rx);
	if (ret < 0)
	return ret;

	netif_tx_napi_add(&dev->mt76.tx_napi_dev, &dev->mt76.tx_napi,
	mt7921_poll_tx, NAPI_POLL_WEIGHT);
	napi_enable(&dev->mt76.tx_napi);

	return mt7921_dma_enable(dev);
	}

	void mt7921_dma_cleanup(struct mt7921_dev *dev)
	{
	/* disable */
	mt76_clear(dev, MT_WFDMA0_GLO_CFG,
	MT_WFDMA0_GLO_CFG_TX_DMA_EN \|
	MT_WFDMA0_GLO_CFG_RX_DMA_EN \|
	MT_WFDMA0_GLO_CFG_CSR_DISP_BASE_PTR_CHAIN_EN \|
	MT_WFDMA0_GLO_CFG_OMIT_TX_INFO \|
	MT_WFDMA0_GLO_CFG_OMIT_RX_INFO \|
	MT_WFDMA0_GLO_CFG_OMIT_RX_INFO_PFET2);

	/* reset */
	mt76_clear(dev, MT_WFDMA0_RST,
	MT_WFDMA0_RST_DMASHDL_ALL_RST \|
	MT_WFDMA0_RST_LOGIC_RST);

	mt76_set(dev, MT_WFDMA0_RST,
	MT_WFDMA0_RST_DMASHDL_ALL_RST \|
	MT_WFDMA0_RST_LOGIC_RST);

	mt76_dma_cleanup(&dev->mt76);
	}