| # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) |
| %YAML 1.2 |
| --- |
| $id: http://devicetree.org/schemas/media/allwinner,sun6i-a31-mipi-csi2.yaml# |
| $schema: http://devicetree.org/meta-schemas/core.yaml# |
| |
| title: Allwinner A31 MIPI CSI-2 |
| |
| maintainers: |
| - Paul Kocialkowski <paul.kocialkowski@bootlin.com> |
| |
| properties: |
| compatible: |
| oneOf: |
| - const: allwinner,sun6i-a31-mipi-csi2 |
| - items: |
| - const: allwinner,sun8i-v3s-mipi-csi2 |
| - const: allwinner,sun6i-a31-mipi-csi2 |
| |
| reg: |
| maxItems: 1 |
| |
| interrupts: |
| maxItems: 1 |
| |
| clocks: |
| items: |
| - description: Bus Clock |
| - description: Module Clock |
| |
| clock-names: |
| items: |
| - const: bus |
| - const: mod |
| |
| phys: |
| maxItems: 1 |
| description: MIPI D-PHY |
| |
| phy-names: |
| items: |
| - const: dphy |
| |
| resets: |
| maxItems: 1 |
| |
| ports: |
| $ref: /schemas/graph.yaml#/properties/ports |
| |
| properties: |
| port@0: |
| $ref: /schemas/graph.yaml#/$defs/port-base |
| description: Input port, connect to a MIPI CSI-2 sensor |
| |
| properties: |
| reg: |
| const: 0 |
| |
| endpoint: |
| $ref: video-interfaces.yaml# |
| unevaluatedProperties: false |
| |
| properties: |
| data-lanes: |
| minItems: 1 |
| maxItems: 4 |
| |
| required: |
| - data-lanes |
| |
| unevaluatedProperties: false |
| |
| port@1: |
| $ref: /schemas/graph.yaml#/properties/port |
| description: Output port, connect to a CSI controller |
| |
| required: |
| - port@0 |
| - port@1 |
| |
| required: |
| - compatible |
| - reg |
| - interrupts |
| - clocks |
| - clock-names |
| - phys |
| - phy-names |
| - resets |
| - ports |
| |
| additionalProperties: false |
| |
| examples: |
| - | |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| #include <dt-bindings/clock/sun8i-v3s-ccu.h> |
| #include <dt-bindings/reset/sun8i-v3s-ccu.h> |
| |
| mipi_csi2: csi@1cb1000 { |
| compatible = "allwinner,sun8i-v3s-mipi-csi2", |
| "allwinner,sun6i-a31-mipi-csi2"; |
| reg = <0x01cb1000 0x1000>; |
| interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&ccu CLK_BUS_CSI>, |
| <&ccu CLK_CSI1_SCLK>; |
| clock-names = "bus", "mod"; |
| resets = <&ccu RST_BUS_CSI>; |
| |
| phys = <&dphy>; |
| phy-names = "dphy"; |
| |
| ports { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| mipi_csi2_in: port@0 { |
| reg = <0>; |
| |
| mipi_csi2_in_ov5648: endpoint { |
| data-lanes = <1 2 3 4>; |
| |
| remote-endpoint = <&ov5648_out_mipi_csi2>; |
| }; |
| }; |
| |
| mipi_csi2_out: port@1 { |
| reg = <1>; |
| |
| mipi_csi2_out_csi0: endpoint { |
| remote-endpoint = <&csi0_in_mipi_csi2>; |
| }; |
| }; |
| }; |
| }; |
| |
| ... |