| // SPDX-License-Identifier: GPL-2.0 |
| /* |
| * Copyright (c) 2017-2018 MediaTek Inc. |
| * Author: John Crispin <john@phrozen.org> |
| * Sean Wang <sean.wang@mediatek.com> |
| * Ryder Lee <ryder.lee@mediatek.com> |
| * |
| */ |
| |
| #include <dt-bindings/interrupt-controller/irq.h> |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| #include <dt-bindings/clock/mt2701-clk.h> |
| #include <dt-bindings/pinctrl/mt7623-pinfunc.h> |
| #include <dt-bindings/power/mt2701-power.h> |
| #include <dt-bindings/gpio/gpio.h> |
| #include <dt-bindings/phy/phy.h> |
| #include <dt-bindings/reset/mt2701-resets.h> |
| #include <dt-bindings/thermal/thermal.h> |
| |
| / { |
| compatible = "mediatek,mt7623"; |
| interrupt-parent = <&sysirq>; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| |
| cpu_opp_table: opp-table { |
| compatible = "operating-points-v2"; |
| opp-shared; |
| |
| opp-98000000 { |
| opp-hz = /bits/ 64 <98000000>; |
| opp-microvolt = <1050000>; |
| }; |
| |
| opp-198000000 { |
| opp-hz = /bits/ 64 <198000000>; |
| opp-microvolt = <1050000>; |
| }; |
| |
| opp-398000000 { |
| opp-hz = /bits/ 64 <398000000>; |
| opp-microvolt = <1050000>; |
| }; |
| |
| opp-598000000 { |
| opp-hz = /bits/ 64 <598000000>; |
| opp-microvolt = <1050000>; |
| }; |
| |
| opp-747500000 { |
| opp-hz = /bits/ 64 <747500000>; |
| opp-microvolt = <1050000>; |
| }; |
| |
| opp-1040000000 { |
| opp-hz = /bits/ 64 <1040000000>; |
| opp-microvolt = <1150000>; |
| }; |
| |
| opp-1196000000 { |
| opp-hz = /bits/ 64 <1196000000>; |
| opp-microvolt = <1200000>; |
| }; |
| |
| opp-1300000000 { |
| opp-hz = /bits/ 64 <1300000000>; |
| opp-microvolt = <1300000>; |
| }; |
| }; |
| |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| enable-method = "mediatek,mt6589-smp"; |
| |
| cpu0: cpu@0 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a7"; |
| reg = <0x0>; |
| clocks = <&infracfg CLK_INFRA_CPUSEL>, |
| <&apmixedsys CLK_APMIXED_MAINPLL>; |
| clock-names = "cpu", "intermediate"; |
| operating-points-v2 = <&cpu_opp_table>; |
| #cooling-cells = <2>; |
| clock-frequency = <1300000000>; |
| }; |
| |
| cpu1: cpu@1 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a7"; |
| reg = <0x1>; |
| clocks = <&infracfg CLK_INFRA_CPUSEL>, |
| <&apmixedsys CLK_APMIXED_MAINPLL>; |
| clock-names = "cpu", "intermediate"; |
| operating-points-v2 = <&cpu_opp_table>; |
| #cooling-cells = <2>; |
| clock-frequency = <1300000000>; |
| }; |
| |
| cpu2: cpu@2 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a7"; |
| reg = <0x2>; |
| clocks = <&infracfg CLK_INFRA_CPUSEL>, |
| <&apmixedsys CLK_APMIXED_MAINPLL>; |
| clock-names = "cpu", "intermediate"; |
| operating-points-v2 = <&cpu_opp_table>; |
| #cooling-cells = <2>; |
| clock-frequency = <1300000000>; |
| }; |
| |
| cpu3: cpu@3 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a7"; |
| reg = <0x3>; |
| clocks = <&infracfg CLK_INFRA_CPUSEL>, |
| <&apmixedsys CLK_APMIXED_MAINPLL>; |
| clock-names = "cpu", "intermediate"; |
| operating-points-v2 = <&cpu_opp_table>; |
| #cooling-cells = <2>; |
| clock-frequency = <1300000000>; |
| }; |
| }; |
| |
| pmu { |
| compatible = "arm,cortex-a7-pmu"; |
| interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_LOW>, |
| <GIC_SPI 5 IRQ_TYPE_LEVEL_LOW>, |
| <GIC_SPI 6 IRQ_TYPE_LEVEL_LOW>, |
| <GIC_SPI 7 IRQ_TYPE_LEVEL_LOW>; |
| interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; |
| }; |
| |
| system_clk: dummy13m { |
| compatible = "fixed-clock"; |
| clock-frequency = <13000000>; |
| #clock-cells = <0>; |
| }; |
| |
| rtc32k: oscillator-1 { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <32000>; |
| clock-output-names = "rtc32k"; |
| }; |
| |
| clk26m: oscillator-0 { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <26000000>; |
| clock-output-names = "clk26m"; |
| }; |
| |
| thermal-zones { |
| cpu_thermal: cpu-thermal { |
| polling-delay-passive = <1000>; |
| polling-delay = <1000>; |
| |
| thermal-sensors = <&thermal 0>; |
| |
| trips { |
| cpu_passive: cpu-passive { |
| temperature = <47000>; |
| hysteresis = <2000>; |
| type = "passive"; |
| }; |
| |
| cpu_active: cpu-active { |
| temperature = <67000>; |
| hysteresis = <2000>; |
| type = "active"; |
| }; |
| |
| cpu_hot: cpu-hot { |
| temperature = <87000>; |
| hysteresis = <2000>; |
| type = "hot"; |
| }; |
| |
| cpu-crit { |
| temperature = <107000>; |
| hysteresis = <2000>; |
| type = "critical"; |
| }; |
| }; |
| |
| cooling-maps { |
| map0 { |
| trip = <&cpu_passive>; |
| cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
| }; |
| |
| map1 { |
| trip = <&cpu_active>; |
| cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
| }; |
| |
| map2 { |
| trip = <&cpu_hot>; |
| cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
| }; |
| }; |
| }; |
| }; |
| |
| timer { |
| compatible = "arm,armv7-timer"; |
| interrupt-parent = <&gic>; |
| interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, |
| <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, |
| <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, |
| <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; |
| clock-frequency = <13000000>; |
| arm,cpu-registers-not-fw-configured; |
| }; |
| |
| topckgen: syscon@10000000 { |
| compatible = "mediatek,mt7623-topckgen", |
| "mediatek,mt2701-topckgen", |
| "syscon"; |
| reg = <0 0x10000000 0 0x1000>; |
| #clock-cells = <1>; |
| }; |
| |
| infracfg: syscon@10001000 { |
| compatible = "mediatek,mt7623-infracfg", |
| "mediatek,mt2701-infracfg", |
| "syscon"; |
| reg = <0 0x10001000 0 0x1000>; |
| #clock-cells = <1>; |
| #reset-cells = <1>; |
| }; |
| |
| pericfg: syscon@10003000 { |
| compatible = "mediatek,mt7623-pericfg", |
| "mediatek,mt2701-pericfg", |
| "syscon"; |
| reg = <0 0x10003000 0 0x1000>; |
| #clock-cells = <1>; |
| #reset-cells = <1>; |
| }; |
| |
| pio: pinctrl@10005000 { |
| compatible = "mediatek,mt7623-pinctrl"; |
| reg = <0 0x1000b000 0 0x1000>; |
| mediatek,pctl-regmap = <&syscfg_pctl_a>; |
| pins-are-numbered; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| interrupt-parent = <&gic>; |
| #interrupt-cells = <2>; |
| interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| syscfg_pctl_a: syscfg@10005000 { |
| compatible = "mediatek,mt7623-pctl-a-syscfg", "syscon"; |
| reg = <0 0x10005000 0 0x1000>; |
| }; |
| |
| scpsys: power-controller@10006000 { |
| compatible = "mediatek,mt7623-scpsys", |
| "mediatek,mt2701-scpsys", |
| "syscon"; |
| #power-domain-cells = <1>; |
| reg = <0 0x10006000 0 0x1000>; |
| infracfg = <&infracfg>; |
| clocks = <&topckgen CLK_TOP_MM_SEL>, |
| <&topckgen CLK_TOP_MFG_SEL>, |
| <&topckgen CLK_TOP_ETHIF_SEL>; |
| clock-names = "mm", "mfg", "ethif"; |
| }; |
| |
| watchdog: watchdog@10007000 { |
| compatible = "mediatek,mt7623-wdt", |
| "mediatek,mt6589-wdt"; |
| reg = <0 0x10007000 0 0x100>; |
| }; |
| |
| timer: timer@10008000 { |
| compatible = "mediatek,mt7623-timer", |
| "mediatek,mt6577-timer"; |
| reg = <0 0x10008000 0 0x80>; |
| interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>; |
| clocks = <&system_clk>, <&rtc32k>; |
| clock-names = "system-clk", "rtc-clk"; |
| }; |
| |
| pwrap: pwrap@1000d000 { |
| compatible = "mediatek,mt7623-pwrap", |
| "mediatek,mt2701-pwrap"; |
| reg = <0 0x1000d000 0 0x1000>; |
| reg-names = "pwrap"; |
| interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; |
| resets = <&infracfg MT2701_INFRA_PMIC_WRAP_RST>; |
| reset-names = "pwrap"; |
| clocks = <&infracfg CLK_INFRA_PMICSPI>, |
| <&infracfg CLK_INFRA_PMICWRAP>; |
| clock-names = "spi", "wrap"; |
| }; |
| |
| cir: cir@10013000 { |
| compatible = "mediatek,mt7623-cir"; |
| reg = <0 0x10013000 0 0x1000>; |
| interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>; |
| clocks = <&infracfg CLK_INFRA_IRRX>; |
| clock-names = "clk"; |
| status = "disabled"; |
| }; |
| |
| sysirq: interrupt-controller@10200100 { |
| compatible = "mediatek,mt7623-sysirq", |
| "mediatek,mt6577-sysirq"; |
| interrupt-controller; |
| #interrupt-cells = <3>; |
| interrupt-parent = <&gic>; |
| reg = <0 0x10200100 0 0x1c>; |
| }; |
| |
| efuse: efuse@10206000 { |
| compatible = "mediatek,mt7623-efuse", |
| "mediatek,mt8173-efuse"; |
| reg = <0 0x10206000 0 0x1000>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| thermal_calibration_data: calib@424 { |
| reg = <0x424 0xc>; |
| }; |
| }; |
| |
| apmixedsys: syscon@10209000 { |
| compatible = "mediatek,mt7623-apmixedsys", |
| "mediatek,mt2701-apmixedsys", |
| "syscon"; |
| reg = <0 0x10209000 0 0x1000>; |
| #clock-cells = <1>; |
| }; |
| |
| rng: rng@1020f000 { |
| compatible = "mediatek,mt7623-rng"; |
| reg = <0 0x1020f000 0 0x1000>; |
| clocks = <&infracfg CLK_INFRA_TRNG>; |
| clock-names = "rng"; |
| }; |
| |
| gic: interrupt-controller@10211000 { |
| compatible = "arm,cortex-a7-gic"; |
| interrupt-controller; |
| #interrupt-cells = <3>; |
| interrupt-parent = <&gic>; |
| reg = <0 0x10211000 0 0x1000>, |
| <0 0x10212000 0 0x2000>, |
| <0 0x10214000 0 0x2000>, |
| <0 0x10216000 0 0x2000>; |
| }; |
| |
| auxadc: adc@11001000 { |
| compatible = "mediatek,mt7623-auxadc", |
| "mediatek,mt2701-auxadc"; |
| reg = <0 0x11001000 0 0x1000>; |
| clocks = <&pericfg CLK_PERI_AUXADC>; |
| clock-names = "main"; |
| #io-channel-cells = <1>; |
| }; |
| |
| uart0: serial@11002000 { |
| compatible = "mediatek,mt7623-uart", |
| "mediatek,mt6577-uart"; |
| reg = <0 0x11002000 0 0x400>; |
| interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>; |
| clocks = <&pericfg CLK_PERI_UART0_SEL>, |
| <&pericfg CLK_PERI_UART0>; |
| clock-names = "baud", "bus"; |
| status = "disabled"; |
| }; |
| |
| uart1: serial@11003000 { |
| compatible = "mediatek,mt7623-uart", |
| "mediatek,mt6577-uart"; |
| reg = <0 0x11003000 0 0x400>; |
| interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>; |
| clocks = <&pericfg CLK_PERI_UART1_SEL>, |
| <&pericfg CLK_PERI_UART1>; |
| clock-names = "baud", "bus"; |
| status = "disabled"; |
| }; |
| |
| uart2: serial@11004000 { |
| compatible = "mediatek,mt7623-uart", |
| "mediatek,mt6577-uart"; |
| reg = <0 0x11004000 0 0x400>; |
| interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>; |
| clocks = <&pericfg CLK_PERI_UART2_SEL>, |
| <&pericfg CLK_PERI_UART2>; |
| clock-names = "baud", "bus"; |
| status = "disabled"; |
| }; |
| |
| uart3: serial@11005000 { |
| compatible = "mediatek,mt7623-uart", |
| "mediatek,mt6577-uart"; |
| reg = <0 0x11005000 0 0x400>; |
| interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>; |
| clocks = <&pericfg CLK_PERI_UART3_SEL>, |
| <&pericfg CLK_PERI_UART3>; |
| clock-names = "baud", "bus"; |
| status = "disabled"; |
| }; |
| |
| pwm: pwm@11006000 { |
| compatible = "mediatek,mt7623-pwm"; |
| reg = <0 0x11006000 0 0x1000>; |
| #pwm-cells = <2>; |
| clocks = <&topckgen CLK_TOP_PWM_SEL>, |
| <&pericfg CLK_PERI_PWM>, |
| <&pericfg CLK_PERI_PWM1>, |
| <&pericfg CLK_PERI_PWM2>, |
| <&pericfg CLK_PERI_PWM3>, |
| <&pericfg CLK_PERI_PWM4>, |
| <&pericfg CLK_PERI_PWM5>; |
| clock-names = "top", "main", "pwm1", "pwm2", |
| "pwm3", "pwm4", "pwm5"; |
| status = "disabled"; |
| }; |
| |
| i2c0: i2c@11007000 { |
| compatible = "mediatek,mt7623-i2c", |
| "mediatek,mt6577-i2c"; |
| reg = <0 0x11007000 0 0x70>, |
| <0 0x11000200 0 0x80>; |
| interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_LOW>; |
| clock-div = <16>; |
| clocks = <&pericfg CLK_PERI_I2C0>, |
| <&pericfg CLK_PERI_AP_DMA>; |
| clock-names = "main", "dma"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| i2c1: i2c@11008000 { |
| compatible = "mediatek,mt7623-i2c", |
| "mediatek,mt6577-i2c"; |
| reg = <0 0x11008000 0 0x70>, |
| <0 0x11000280 0 0x80>; |
| interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_LOW>; |
| clock-div = <16>; |
| clocks = <&pericfg CLK_PERI_I2C1>, |
| <&pericfg CLK_PERI_AP_DMA>; |
| clock-names = "main", "dma"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| i2c2: i2c@11009000 { |
| compatible = "mediatek,mt7623-i2c", |
| "mediatek,mt6577-i2c"; |
| reg = <0 0x11009000 0 0x70>, |
| <0 0x11000300 0 0x80>; |
| interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_LOW>; |
| clock-div = <16>; |
| clocks = <&pericfg CLK_PERI_I2C2>, |
| <&pericfg CLK_PERI_AP_DMA>; |
| clock-names = "main", "dma"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| spi0: spi@1100a000 { |
| compatible = "mediatek,mt7623-spi", |
| "mediatek,mt2701-spi"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0 0x1100a000 0 0x100>; |
| interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>; |
| clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, |
| <&topckgen CLK_TOP_SPI0_SEL>, |
| <&pericfg CLK_PERI_SPI0>; |
| clock-names = "parent-clk", "sel-clk", "spi-clk"; |
| status = "disabled"; |
| }; |
| |
| thermal: thermal@1100b000 { |
| #thermal-sensor-cells = <1>; |
| compatible = "mediatek,mt7623-thermal", |
| "mediatek,mt2701-thermal"; |
| reg = <0 0x1100b000 0 0x1000>; |
| interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>; |
| clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>; |
| clock-names = "therm", "auxadc"; |
| resets = <&pericfg MT2701_PERI_THERM_SW_RST>; |
| reset-names = "therm"; |
| mediatek,auxadc = <&auxadc>; |
| mediatek,apmixedsys = <&apmixedsys>; |
| nvmem-cells = <&thermal_calibration_data>; |
| nvmem-cell-names = "calibration-data"; |
| }; |
| |
| btif: serial@1100c000 { |
| compatible = "mediatek,mt7623-btif", |
| "mediatek,mtk-btif"; |
| reg = <0 0x1100c000 0 0x1000>; |
| interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_LOW>; |
| clocks = <&pericfg CLK_PERI_BTIF>; |
| clock-names = "main"; |
| reg-shift = <2>; |
| reg-io-width = <4>; |
| status = "disabled"; |
| }; |
| |
| nandc: nfi@1100d000 { |
| compatible = "mediatek,mt7623-nfc", |
| "mediatek,mt2701-nfc"; |
| reg = <0 0x1100d000 0 0x1000>; |
| interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>; |
| power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>; |
| clocks = <&pericfg CLK_PERI_NFI>, |
| <&pericfg CLK_PERI_NFI_PAD>; |
| clock-names = "nfi_clk", "pad_clk"; |
| status = "disabled"; |
| ecc-engine = <&bch>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| }; |
| |
| bch: ecc@1100e000 { |
| compatible = "mediatek,mt7623-ecc", |
| "mediatek,mt2701-ecc"; |
| reg = <0 0x1100e000 0 0x1000>; |
| interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>; |
| clocks = <&pericfg CLK_PERI_NFI_ECC>; |
| clock-names = "nfiecc_clk"; |
| status = "disabled"; |
| }; |
| |
| nor_flash: spi@11014000 { |
| compatible = "mediatek,mt7623-nor", |
| "mediatek,mt8173-nor"; |
| reg = <0 0x11014000 0 0x1000>; |
| clocks = <&pericfg CLK_PERI_FLASH>, |
| <&topckgen CLK_TOP_FLASH_SEL>; |
| clock-names = "spi", "sf"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| spi1: spi@11016000 { |
| compatible = "mediatek,mt7623-spi", |
| "mediatek,mt2701-spi"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0 0x11016000 0 0x100>; |
| interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>; |
| clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, |
| <&topckgen CLK_TOP_SPI1_SEL>, |
| <&pericfg CLK_PERI_SPI1>; |
| clock-names = "parent-clk", "sel-clk", "spi-clk"; |
| status = "disabled"; |
| }; |
| |
| spi2: spi@11017000 { |
| compatible = "mediatek,mt7623-spi", |
| "mediatek,mt2701-spi"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0 0x11017000 0 0x1000>; |
| interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_LOW>; |
| clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, |
| <&topckgen CLK_TOP_SPI2_SEL>, |
| <&pericfg CLK_PERI_SPI2>; |
| clock-names = "parent-clk", "sel-clk", "spi-clk"; |
| status = "disabled"; |
| }; |
| |
| audsys: clock-controller@11220000 { |
| compatible = "mediatek,mt7623-audsys", |
| "mediatek,mt2701-audsys", |
| "syscon"; |
| reg = <0 0x11220000 0 0x2000>; |
| #clock-cells = <1>; |
| |
| afe: audio-controller { |
| compatible = "mediatek,mt7623-audio", |
| "mediatek,mt2701-audio"; |
| interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>, |
| <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>; |
| interrupt-names = "afe", "asys"; |
| power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>; |
| |
| clocks = <&infracfg CLK_INFRA_AUDIO>, |
| <&topckgen CLK_TOP_AUD_MUX1_SEL>, |
| <&topckgen CLK_TOP_AUD_MUX2_SEL>, |
| <&topckgen CLK_TOP_AUD_48K_TIMING>, |
| <&topckgen CLK_TOP_AUD_44K_TIMING>, |
| <&topckgen CLK_TOP_AUD_K1_SRC_SEL>, |
| <&topckgen CLK_TOP_AUD_K2_SRC_SEL>, |
| <&topckgen CLK_TOP_AUD_K3_SRC_SEL>, |
| <&topckgen CLK_TOP_AUD_K4_SRC_SEL>, |
| <&topckgen CLK_TOP_AUD_K1_SRC_DIV>, |
| <&topckgen CLK_TOP_AUD_K2_SRC_DIV>, |
| <&topckgen CLK_TOP_AUD_K3_SRC_DIV>, |
| <&topckgen CLK_TOP_AUD_K4_SRC_DIV>, |
| <&topckgen CLK_TOP_AUD_I2S1_MCLK>, |
| <&topckgen CLK_TOP_AUD_I2S2_MCLK>, |
| <&topckgen CLK_TOP_AUD_I2S3_MCLK>, |
| <&topckgen CLK_TOP_AUD_I2S4_MCLK>, |
| <&audsys CLK_AUD_I2SO1>, |
| <&audsys CLK_AUD_I2SO2>, |
| <&audsys CLK_AUD_I2SO3>, |
| <&audsys CLK_AUD_I2SO4>, |
| <&audsys CLK_AUD_I2SIN1>, |
| <&audsys CLK_AUD_I2SIN2>, |
| <&audsys CLK_AUD_I2SIN3>, |
| <&audsys CLK_AUD_I2SIN4>, |
| <&audsys CLK_AUD_ASRCO1>, |
| <&audsys CLK_AUD_ASRCO2>, |
| <&audsys CLK_AUD_ASRCO3>, |
| <&audsys CLK_AUD_ASRCO4>, |
| <&audsys CLK_AUD_AFE>, |
| <&audsys CLK_AUD_AFE_CONN>, |
| <&audsys CLK_AUD_A1SYS>, |
| <&audsys CLK_AUD_A2SYS>, |
| <&audsys CLK_AUD_AFE_MRGIF>; |
| |
| clock-names = "infra_sys_audio_clk", |
| "top_audio_mux1_sel", |
| "top_audio_mux2_sel", |
| "top_audio_a1sys_hp", |
| "top_audio_a2sys_hp", |
| "i2s0_src_sel", |
| "i2s1_src_sel", |
| "i2s2_src_sel", |
| "i2s3_src_sel", |
| "i2s0_src_div", |
| "i2s1_src_div", |
| "i2s2_src_div", |
| "i2s3_src_div", |
| "i2s0_mclk_en", |
| "i2s1_mclk_en", |
| "i2s2_mclk_en", |
| "i2s3_mclk_en", |
| "i2so0_hop_ck", |
| "i2so1_hop_ck", |
| "i2so2_hop_ck", |
| "i2so3_hop_ck", |
| "i2si0_hop_ck", |
| "i2si1_hop_ck", |
| "i2si2_hop_ck", |
| "i2si3_hop_ck", |
| "asrc0_out_ck", |
| "asrc1_out_ck", |
| "asrc2_out_ck", |
| "asrc3_out_ck", |
| "audio_afe_pd", |
| "audio_afe_conn_pd", |
| "audio_a1sys_pd", |
| "audio_a2sys_pd", |
| "audio_mrgif_pd"; |
| |
| assigned-clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>, |
| <&topckgen CLK_TOP_AUD_MUX2_SEL>, |
| <&topckgen CLK_TOP_AUD_MUX1_DIV>, |
| <&topckgen CLK_TOP_AUD_MUX2_DIV>; |
| assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL_98M>, |
| <&topckgen CLK_TOP_AUD2PLL_90M>; |
| assigned-clock-rates = <0>, <0>, <49152000>, <45158400>; |
| }; |
| }; |
| |
| mmc0: mmc@11230000 { |
| compatible = "mediatek,mt7623-mmc", |
| "mediatek,mt2701-mmc"; |
| reg = <0 0x11230000 0 0x1000>; |
| interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_LOW>; |
| clocks = <&pericfg CLK_PERI_MSDC30_0>, |
| <&topckgen CLK_TOP_MSDC30_0_SEL>; |
| clock-names = "source", "hclk"; |
| status = "disabled"; |
| }; |
| |
| mmc1: mmc@11240000 { |
| compatible = "mediatek,mt7623-mmc", |
| "mediatek,mt2701-mmc"; |
| reg = <0 0x11240000 0 0x1000>; |
| interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_LOW>; |
| clocks = <&pericfg CLK_PERI_MSDC30_1>, |
| <&topckgen CLK_TOP_MSDC30_1_SEL>; |
| clock-names = "source", "hclk"; |
| status = "disabled"; |
| }; |
| |
| vdecsys: syscon@16000000 { |
| compatible = "mediatek,mt7623-vdecsys", |
| "mediatek,mt2701-vdecsys", |
| "syscon"; |
| reg = <0 0x16000000 0 0x1000>; |
| #clock-cells = <1>; |
| }; |
| |
| hifsys: syscon@1a000000 { |
| compatible = "mediatek,mt7623-hifsys", |
| "mediatek,mt2701-hifsys", |
| "syscon"; |
| reg = <0 0x1a000000 0 0x1000>; |
| #clock-cells = <1>; |
| #reset-cells = <1>; |
| }; |
| |
| pcie: pcie@1a140000 { |
| compatible = "mediatek,mt7623-pcie"; |
| device_type = "pci"; |
| reg = <0 0x1a140000 0 0x1000>, /* PCIe shared registers */ |
| <0 0x1a142000 0 0x1000>, /* Port0 registers */ |
| <0 0x1a143000 0 0x1000>, /* Port1 registers */ |
| <0 0x1a144000 0 0x1000>; /* Port2 registers */ |
| reg-names = "subsys", "port0", "port1", "port2"; |
| #address-cells = <3>; |
| #size-cells = <2>; |
| #interrupt-cells = <1>; |
| interrupt-map-mask = <0xf800 0 0 0>; |
| interrupt-map = <0x0000 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>, |
| <0x0800 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>, |
| <0x1000 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>; |
| clocks = <&topckgen CLK_TOP_ETHIF_SEL>, |
| <&hifsys CLK_HIFSYS_PCIE0>, |
| <&hifsys CLK_HIFSYS_PCIE1>, |
| <&hifsys CLK_HIFSYS_PCIE2>; |
| clock-names = "free_ck", "sys_ck0", "sys_ck1", "sys_ck2"; |
| resets = <&hifsys MT2701_HIFSYS_PCIE0_RST>, |
| <&hifsys MT2701_HIFSYS_PCIE1_RST>, |
| <&hifsys MT2701_HIFSYS_PCIE2_RST>; |
| reset-names = "pcie-rst0", "pcie-rst1", "pcie-rst2"; |
| phys = <&pcie0_port PHY_TYPE_PCIE>, |
| <&pcie1_port PHY_TYPE_PCIE>, |
| <&u3port1 PHY_TYPE_PCIE>; |
| phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2"; |
| power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>; |
| bus-range = <0x00 0xff>; |
| status = "disabled"; |
| ranges = <0x81000000 0 0x1a160000 0 0x1a160000 0 0x00010000 |
| 0x83000000 0 0x60000000 0 0x60000000 0 0x10000000>; |
| |
| pcie@0,0 { |
| reg = <0x0000 0 0 0 0>; |
| #address-cells = <3>; |
| #size-cells = <2>; |
| #interrupt-cells = <1>; |
| interrupt-map-mask = <0 0 0 0>; |
| interrupt-map = <0 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>; |
| ranges; |
| status = "disabled"; |
| }; |
| |
| pcie@1,0 { |
| reg = <0x0800 0 0 0 0>; |
| #address-cells = <3>; |
| #size-cells = <2>; |
| #interrupt-cells = <1>; |
| interrupt-map-mask = <0 0 0 0>; |
| interrupt-map = <0 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>; |
| ranges; |
| status = "disabled"; |
| }; |
| |
| pcie@2,0 { |
| reg = <0x1000 0 0 0 0>; |
| #address-cells = <3>; |
| #size-cells = <2>; |
| #interrupt-cells = <1>; |
| interrupt-map-mask = <0 0 0 0>; |
| interrupt-map = <0 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>; |
| ranges; |
| status = "disabled"; |
| }; |
| }; |
| |
| pcie0_phy: pcie-phy@1a149000 { |
| compatible = "mediatek,generic-tphy-v1"; |
| reg = <0 0x1a149000 0 0x0700>; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| status = "disabled"; |
| |
| pcie0_port: pcie-phy@1a149900 { |
| reg = <0 0x1a149900 0 0x0700>; |
| clocks = <&clk26m>; |
| clock-names = "ref"; |
| #phy-cells = <1>; |
| status = "okay"; |
| }; |
| }; |
| |
| pcie1_phy: pcie-phy@1a14a000 { |
| compatible = "mediatek,generic-tphy-v1"; |
| reg = <0 0x1a14a000 0 0x0700>; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| status = "disabled"; |
| |
| pcie1_port: pcie-phy@1a14a900 { |
| reg = <0 0x1a14a900 0 0x0700>; |
| clocks = <&clk26m>; |
| clock-names = "ref"; |
| #phy-cells = <1>; |
| status = "okay"; |
| }; |
| }; |
| |
| usb1: usb@1a1c0000 { |
| compatible = "mediatek,mt7623-xhci", |
| "mediatek,mt8173-xhci"; |
| reg = <0 0x1a1c0000 0 0x1000>, |
| <0 0x1a1c4700 0 0x0100>; |
| reg-names = "mac", "ippc"; |
| interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_LOW>; |
| clocks = <&hifsys CLK_HIFSYS_USB0PHY>, |
| <&topckgen CLK_TOP_ETHIF_SEL>; |
| clock-names = "sys_ck", "ref_ck"; |
| power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>; |
| phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>; |
| status = "disabled"; |
| }; |
| |
| u3phy1: usb-phy@1a1c4000 { |
| compatible = "mediatek,mt7623-u3phy", |
| "mediatek,mt2701-u3phy"; |
| reg = <0 0x1a1c4000 0 0x0700>; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| status = "disabled"; |
| |
| u2port0: usb-phy@1a1c4800 { |
| reg = <0 0x1a1c4800 0 0x0100>; |
| clocks = <&topckgen CLK_TOP_USB_PHY48M>; |
| clock-names = "ref"; |
| #phy-cells = <1>; |
| status = "okay"; |
| }; |
| |
| u3port0: usb-phy@1a1c4900 { |
| reg = <0 0x1a1c4900 0 0x0700>; |
| clocks = <&clk26m>; |
| clock-names = "ref"; |
| #phy-cells = <1>; |
| status = "okay"; |
| }; |
| }; |
| |
| usb2: usb@1a240000 { |
| compatible = "mediatek,mt7623-xhci", |
| "mediatek,mt8173-xhci"; |
| reg = <0 0x1a240000 0 0x1000>, |
| <0 0x1a244700 0 0x0100>; |
| reg-names = "mac", "ippc"; |
| interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_LOW>; |
| clocks = <&hifsys CLK_HIFSYS_USB1PHY>, |
| <&topckgen CLK_TOP_ETHIF_SEL>; |
| clock-names = "sys_ck", "ref_ck"; |
| power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>; |
| phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>; |
| status = "disabled"; |
| }; |
| |
| u3phy2: usb-phy@1a244000 { |
| compatible = "mediatek,mt7623-u3phy", |
| "mediatek,mt2701-u3phy"; |
| reg = <0 0x1a244000 0 0x0700>; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| status = "disabled"; |
| |
| u2port1: usb-phy@1a244800 { |
| reg = <0 0x1a244800 0 0x0100>; |
| clocks = <&topckgen CLK_TOP_USB_PHY48M>; |
| clock-names = "ref"; |
| #phy-cells = <1>; |
| status = "okay"; |
| }; |
| |
| u3port1: usb-phy@1a244900 { |
| reg = <0 0x1a244900 0 0x0700>; |
| clocks = <&clk26m>; |
| clock-names = "ref"; |
| #phy-cells = <1>; |
| status = "okay"; |
| }; |
| }; |
| |
| ethsys: syscon@1b000000 { |
| compatible = "mediatek,mt7623-ethsys", |
| "mediatek,mt2701-ethsys", |
| "syscon"; |
| reg = <0 0x1b000000 0 0x1000>; |
| #clock-cells = <1>; |
| #reset-cells = <1>; |
| }; |
| |
| hsdma: dma-controller@1b007000 { |
| compatible = "mediatek,mt7623-hsdma"; |
| reg = <0 0x1b007000 0 0x1000>; |
| interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_LOW>; |
| clocks = <ðsys CLK_ETHSYS_HSDMA>; |
| clock-names = "hsdma"; |
| power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>; |
| #dma-cells = <1>; |
| }; |
| |
| eth: ethernet@1b100000 { |
| compatible = "mediatek,mt7623-eth", |
| "mediatek,mt2701-eth", |
| "syscon"; |
| reg = <0 0x1b100000 0 0x20000>; |
| interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW>, |
| <GIC_SPI 199 IRQ_TYPE_LEVEL_LOW>, |
| <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>; |
| clocks = <&topckgen CLK_TOP_ETHIF_SEL>, |
| <ðsys CLK_ETHSYS_ESW>, |
| <ðsys CLK_ETHSYS_GP1>, |
| <ðsys CLK_ETHSYS_GP2>, |
| <&apmixedsys CLK_APMIXED_TRGPLL>; |
| clock-names = "ethif", "esw", "gp1", "gp2", "trgpll"; |
| resets = <ðsys MT2701_ETHSYS_FE_RST>, |
| <ðsys MT2701_ETHSYS_GMAC_RST>, |
| <ðsys MT2701_ETHSYS_PPE_RST>; |
| reset-names = "fe", "gmac", "ppe"; |
| power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>; |
| mediatek,ethsys = <ðsys>; |
| mediatek,pctl = <&syscfg_pctl_a>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| crypto: crypto@1b240000 { |
| compatible = "mediatek,eip97-crypto"; |
| reg = <0 0x1b240000 0 0x20000>; |
| interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>, |
| <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>, |
| <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>, |
| <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>, |
| <GIC_SPI 97 IRQ_TYPE_LEVEL_LOW>; |
| clocks = <ðsys CLK_ETHSYS_CRYPTO>; |
| clock-names = "cryp"; |
| power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>; |
| status = "disabled"; |
| }; |
| |
| bdpsys: syscon@1c000000 { |
| compatible = "mediatek,mt7623-bdpsys", |
| "mediatek,mt2701-bdpsys", |
| "syscon"; |
| reg = <0 0x1c000000 0 0x1000>; |
| #clock-cells = <1>; |
| }; |
| }; |
| |
| &pio { |
| cir_pins_a:cir-default { |
| pins-cir { |
| pinmux = <MT7623_PIN_46_IR_FUNC_IR>; |
| bias-disable; |
| }; |
| }; |
| |
| i2c0_pins_a: i2c0-default { |
| pins-i2c0 { |
| pinmux = <MT7623_PIN_75_SDA0_FUNC_SDA0>, |
| <MT7623_PIN_76_SCL0_FUNC_SCL0>; |
| bias-disable; |
| }; |
| }; |
| |
| i2c1_pins_a: i2c1-default { |
| pin-i2c1 { |
| pinmux = <MT7623_PIN_57_SDA1_FUNC_SDA1>, |
| <MT7623_PIN_58_SCL1_FUNC_SCL1>; |
| bias-disable; |
| }; |
| }; |
| |
| i2c1_pins_b: i2c1-alt { |
| pin-i2c1 { |
| pinmux = <MT7623_PIN_242_URTS2_FUNC_SCL1>, |
| <MT7623_PIN_243_UCTS2_FUNC_SDA1>; |
| bias-disable; |
| }; |
| }; |
| |
| i2c2_pins_a: i2c2-default { |
| pin-i2c2 { |
| pinmux = <MT7623_PIN_77_SDA2_FUNC_SDA2>, |
| <MT7623_PIN_78_SCL2_FUNC_SCL2>; |
| bias-disable; |
| }; |
| }; |
| |
| i2c2_pins_b: i2c2-alt { |
| pin-i2c2 { |
| pinmux = <MT7623_PIN_122_GPIO122_FUNC_SDA2>, |
| <MT7623_PIN_123_HTPLG_FUNC_SCL2>; |
| bias-disable; |
| }; |
| }; |
| |
| i2s0_pins_a: i2s0-default { |
| pin-i2s0 { |
| pinmux = <MT7623_PIN_49_I2S0_DATA_FUNC_I2S0_DATA>, |
| <MT7623_PIN_72_I2S0_DATA_IN_FUNC_I2S0_DATA_IN>, |
| <MT7623_PIN_73_I2S0_LRCK_FUNC_I2S0_LRCK>, |
| <MT7623_PIN_74_I2S0_BCK_FUNC_I2S0_BCK>, |
| <MT7623_PIN_126_I2S0_MCLK_FUNC_I2S0_MCLK>; |
| drive-strength = <MTK_DRIVE_12mA>; |
| bias-pull-down; |
| }; |
| }; |
| |
| i2s1_pins_a: i2s1-default { |
| pin-i2s1 { |
| pinmux = <MT7623_PIN_33_I2S1_DATA_FUNC_I2S1_DATA>, |
| <MT7623_PIN_34_I2S1_DATA_IN_FUNC_I2S1_DATA_IN>, |
| <MT7623_PIN_35_I2S1_BCK_FUNC_I2S1_BCK>, |
| <MT7623_PIN_36_I2S1_LRCK_FUNC_I2S1_LRCK>, |
| <MT7623_PIN_37_I2S1_MCLK_FUNC_I2S1_MCLK>; |
| drive-strength = <MTK_DRIVE_12mA>; |
| bias-pull-down; |
| }; |
| }; |
| |
| key_pins_a: keys-alt { |
| pins-keys { |
| pinmux = <MT7623_PIN_256_GPIO256_FUNC_GPIO256>, |
| <MT7623_PIN_257_GPIO257_FUNC_GPIO257> ; |
| input-enable; |
| }; |
| }; |
| |
| led_pins_a: leds-alt { |
| pins-leds { |
| pinmux = <MT7623_PIN_239_EXT_SDIO0_FUNC_GPIO239>, |
| <MT7623_PIN_240_EXT_XCS_FUNC_GPIO240>, |
| <MT7623_PIN_241_EXT_SCK_FUNC_GPIO241>; |
| }; |
| }; |
| |
| mmc0_pins_default: mmc0default { |
| pins-cmd-dat { |
| pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>, |
| <MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>, |
| <MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>, |
| <MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>, |
| <MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>, |
| <MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>, |
| <MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>, |
| <MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>, |
| <MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>; |
| input-enable; |
| bias-pull-up; |
| }; |
| |
| pins-clk { |
| pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>; |
| bias-pull-down; |
| }; |
| |
| pins-rst { |
| pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>; |
| bias-pull-up; |
| }; |
| }; |
| |
| mmc0_pins_uhs: mmc0 { |
| pins-cmd-dat { |
| pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>, |
| <MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>, |
| <MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>, |
| <MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>, |
| <MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>, |
| <MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>, |
| <MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>, |
| <MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>, |
| <MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>; |
| input-enable; |
| drive-strength = <MTK_DRIVE_2mA>; |
| bias-pull-up = <MTK_PUPD_SET_R1R0_01>; |
| }; |
| |
| pins-clk { |
| pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>; |
| drive-strength = <MTK_DRIVE_2mA>; |
| bias-pull-down = <MTK_PUPD_SET_R1R0_01>; |
| }; |
| |
| pins-rst { |
| pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>; |
| bias-pull-up; |
| }; |
| }; |
| |
| mmc1_pins_default: mmc1default { |
| pins-cmd-dat { |
| pinmux = <MT7623_PIN_107_MSDC1_DAT0_FUNC_MSDC1_DAT0>, |
| <MT7623_PIN_108_MSDC1_DAT1_FUNC_MSDC1_DAT1>, |
| <MT7623_PIN_109_MSDC1_DAT2_FUNC_MSDC1_DAT2>, |
| <MT7623_PIN_110_MSDC1_DAT3_FUNC_MSDC1_DAT3>, |
| <MT7623_PIN_105_MSDC1_CMD_FUNC_MSDC1_CMD>; |
| input-enable; |
| drive-strength = <MTK_DRIVE_4mA>; |
| bias-pull-up = <MTK_PUPD_SET_R1R0_10>; |
| }; |
| |
| pins-clk { |
| pinmux = <MT7623_PIN_106_MSDC1_CLK_FUNC_MSDC1_CLK>; |
| bias-pull-down; |
| drive-strength = <MTK_DRIVE_4mA>; |
| }; |
| |
| pins-wp { |
| pinmux = <MT7623_PIN_29_EINT7_FUNC_MSDC1_WP>; |
| input-enable; |
| bias-pull-up; |
| }; |
| |
| pins-insert { |
| pinmux = <MT7623_PIN_261_MSDC1_INS_FUNC_GPIO261>; |
| bias-pull-up; |
| }; |
| }; |
| |
| mmc1_pins_uhs: mmc1 { |
| pins-cmd-dat { |
| pinmux = <MT7623_PIN_107_MSDC1_DAT0_FUNC_MSDC1_DAT0>, |
| <MT7623_PIN_108_MSDC1_DAT1_FUNC_MSDC1_DAT1>, |
| <MT7623_PIN_109_MSDC1_DAT2_FUNC_MSDC1_DAT2>, |
| <MT7623_PIN_110_MSDC1_DAT3_FUNC_MSDC1_DAT3>, |
| <MT7623_PIN_105_MSDC1_CMD_FUNC_MSDC1_CMD>; |
| input-enable; |
| drive-strength = <MTK_DRIVE_4mA>; |
| bias-pull-up = <MTK_PUPD_SET_R1R0_10>; |
| }; |
| |
| pins-clk { |
| pinmux = <MT7623_PIN_106_MSDC1_CLK_FUNC_MSDC1_CLK>; |
| drive-strength = <MTK_DRIVE_4mA>; |
| bias-pull-down = <MTK_PUPD_SET_R1R0_10>; |
| }; |
| }; |
| |
| nand_pins_default: nanddefault { |
| pins-ale { |
| pinmux = <MT7623_PIN_116_MSDC0_CMD_FUNC_NALE>; |
| drive-strength = <MTK_DRIVE_8mA>; |
| bias-pull-down = <MTK_PUPD_SET_R1R0_10>; |
| }; |
| |
| pins-dat { |
| pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_NLD7>, |
| <MT7623_PIN_112_MSDC0_DAT6_FUNC_NLD6>, |
| <MT7623_PIN_114_MSDC0_DAT4_FUNC_NLD4>, |
| <MT7623_PIN_118_MSDC0_DAT3_FUNC_NLD3>, |
| <MT7623_PIN_121_MSDC0_DAT0_FUNC_NLD0>, |
| <MT7623_PIN_120_MSDC0_DAT1_FUNC_NLD1>, |
| <MT7623_PIN_113_MSDC0_DAT5_FUNC_NLD5>, |
| <MT7623_PIN_115_MSDC0_RSTB_FUNC_NLD8>, |
| <MT7623_PIN_119_MSDC0_DAT2_FUNC_NLD2>; |
| input-enable; |
| drive-strength = <MTK_DRIVE_8mA>; |
| bias-pull-up; |
| }; |
| |
| pins-we { |
| pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_NWEB>; |
| drive-strength = <MTK_DRIVE_8mA>; |
| bias-pull-up = <MTK_PUPD_SET_R1R0_10>; |
| }; |
| }; |
| |
| pcie_default: pcie_pin_default { |
| pins_cmd_dat { |
| pinmux = <MT7623_PIN_208_AUD_EXT_CK1_FUNC_PCIE0_PERST_N>, |
| <MT7623_PIN_209_AUD_EXT_CK2_FUNC_PCIE1_PERST_N>; |
| bias-disable; |
| }; |
| }; |
| |
| pwm_pins_a: pwm-default { |
| pins-pwm { |
| pinmux = <MT7623_PIN_203_PWM0_FUNC_PWM0>, |
| <MT7623_PIN_204_PWM1_FUNC_PWM1>, |
| <MT7623_PIN_205_PWM2_FUNC_PWM2>, |
| <MT7623_PIN_206_PWM3_FUNC_PWM3>, |
| <MT7623_PIN_207_PWM4_FUNC_PWM4>; |
| }; |
| }; |
| |
| spi0_pins_a: spi0-default { |
| pins-spi { |
| pinmux = <MT7623_PIN_53_SPI0_CSN_FUNC_SPI0_CS>, |
| <MT7623_PIN_54_SPI0_CK_FUNC_SPI0_CK>, |
| <MT7623_PIN_55_SPI0_MI_FUNC_SPI0_MI>, |
| <MT7623_PIN_56_SPI0_MO_FUNC_SPI0_MO>; |
| bias-disable; |
| }; |
| }; |
| |
| spi1_pins_a: spi1-default { |
| pins-spi { |
| pinmux = <MT7623_PIN_7_SPI1_CSN_FUNC_SPI1_CS>, |
| <MT7623_PIN_199_SPI1_CK_FUNC_SPI1_CK>, |
| <MT7623_PIN_8_SPI1_MI_FUNC_SPI1_MI>, |
| <MT7623_PIN_9_SPI1_MO_FUNC_SPI1_MO>; |
| }; |
| }; |
| |
| spi2_pins_a: spi2-default { |
| pins-spi { |
| pinmux = <MT7623_PIN_101_SPI2_CSN_FUNC_SPI2_CS>, |
| <MT7623_PIN_104_SPI2_CK_FUNC_SPI2_CK>, |
| <MT7623_PIN_102_SPI2_MI_FUNC_SPI2_MI>, |
| <MT7623_PIN_103_SPI2_MO_FUNC_SPI2_MO>; |
| }; |
| }; |
| |
| uart0_pins_a: uart0-default { |
| pins-dat { |
| pinmux = <MT7623_PIN_79_URXD0_FUNC_URXD0>, |
| <MT7623_PIN_80_UTXD0_FUNC_UTXD0>; |
| }; |
| }; |
| |
| uart1_pins_a: uart1-default { |
| pins-dat { |
| pinmux = <MT7623_PIN_81_URXD1_FUNC_URXD1>, |
| <MT7623_PIN_82_UTXD1_FUNC_UTXD1>; |
| }; |
| }; |
| |
| uart2_pins_a: uart2-default { |
| pins-dat { |
| pinmux = <MT7623_PIN_14_GPIO14_FUNC_URXD2>, |
| <MT7623_PIN_15_GPIO15_FUNC_UTXD2>; |
| }; |
| }; |
| |
| uart2_pins_b: uart2-alt { |
| pins-dat { |
| pinmux = <MT7623_PIN_200_URXD2_FUNC_URXD2>, |
| <MT7623_PIN_201_UTXD2_FUNC_UTXD2>; |
| }; |
| }; |
| }; |
