| /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ |
| /* |
| * Copyright (C) 2018 David Abdurachmanov <david.abdurachmanov@gmail.com> |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License version 2 as |
| * published by the Free Software Foundation. |
| * |
| * This program is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| * |
| * You should have received a copy of the GNU General Public License |
| * along with this program. If not, see <https://www.gnu.org/licenses/>. |
| */ |
| |
| #ifdef __LP64__ |
| #define __ARCH_WANT_NEW_STAT |
| #define __ARCH_WANT_SET_GET_RLIMIT |
| #endif /* __LP64__ */ |
| |
| #include <asm-generic/unistd.h> |
| |
| /* |
| * Allows the instruction cache to be flushed from userspace. Despite RISC-V |
| * having a direct 'fence.i' instruction available to userspace (which we |
| * can't trap!), that's not actually viable when running on Linux because the |
| * kernel might schedule a process on another hart. There is no way for |
| * userspace to handle this without invoking the kernel (as it doesn't know the |
| * thread->hart mappings), so we've defined a RISC-V specific system call to |
| * flush the instruction cache. |
| * |
| * __NR_riscv_flush_icache is defined to flush the instruction cache over an |
| * address range, with the flush applying to either all threads or just the |
| * caller. We don't currently do anything with the address range, that's just |
| * in there for forwards compatibility. |
| */ |
| #ifndef __NR_riscv_flush_icache |
| #define __NR_riscv_flush_icache (__NR_arch_specific_syscall + 15) |
| #endif |
| __SYSCALL(__NR_riscv_flush_icache, sys_riscv_flush_icache) |
