| /* |
| * MPC8555 CDS Device Tree Source |
| * |
| * Copyright 2006 Freescale Semiconductor Inc. |
| * |
| * This program is free software; you can redistribute it and/or modify it |
| * under the terms of the GNU General Public License as published by the |
| * Free Software Foundation; either version 2 of the License, or (at your |
| * option) any later version. |
| */ |
| |
| |
| / { |
| model = "MPC8555CDS"; |
| compatible = "MPC8555CDS", "MPC85xxCDS"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| PowerPC,8555@0 { |
| device_type = "cpu"; |
| reg = <0>; |
| d-cache-line-size = <20>; // 32 bytes |
| i-cache-line-size = <20>; // 32 bytes |
| d-cache-size = <8000>; // L1, 32K |
| i-cache-size = <8000>; // L1, 32K |
| timebase-frequency = <0>; // 33 MHz, from uboot |
| bus-frequency = <0>; // 166 MHz |
| clock-frequency = <0>; // 825 MHz, from uboot |
| }; |
| }; |
| |
| memory { |
| device_type = "memory"; |
| reg = <00000000 08000000>; // 128M at 0x0 |
| }; |
| |
| soc8555@e0000000 { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| device_type = "soc"; |
| ranges = <0 e0000000 00100000>; |
| reg = <e0000000 00001000>; // CCSRBAR 1M |
| bus-frequency = <0>; |
| |
| memory-controller@2000 { |
| compatible = "fsl,8555-memory-controller"; |
| reg = <2000 1000>; |
| interrupt-parent = <&mpic>; |
| interrupts = <12 2>; |
| }; |
| |
| l2-cache-controller@20000 { |
| compatible = "fsl,8555-l2-cache-controller"; |
| reg = <20000 1000>; |
| cache-line-size = <20>; // 32 bytes |
| cache-size = <40000>; // L2, 256K |
| interrupt-parent = <&mpic>; |
| interrupts = <10 2>; |
| }; |
| |
| i2c@3000 { |
| device_type = "i2c"; |
| compatible = "fsl-i2c"; |
| reg = <3000 100>; |
| interrupts = <2b 2>; |
| interrupt-parent = <&mpic>; |
| dfsrr; |
| }; |
| |
| mdio@24520 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| device_type = "mdio"; |
| compatible = "gianfar"; |
| reg = <24520 20>; |
| phy0: ethernet-phy@0 { |
| interrupt-parent = <&mpic>; |
| interrupts = <5 1>; |
| reg = <0>; |
| device_type = "ethernet-phy"; |
| }; |
| phy1: ethernet-phy@1 { |
| interrupt-parent = <&mpic>; |
| interrupts = <5 1>; |
| reg = <1>; |
| device_type = "ethernet-phy"; |
| }; |
| }; |
| |
| ethernet@24000 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| device_type = "network"; |
| model = "TSEC"; |
| compatible = "gianfar"; |
| reg = <24000 1000>; |
| local-mac-address = [ 00 00 00 00 00 00 ]; |
| interrupts = <1d 2 1e 2 22 2>; |
| interrupt-parent = <&mpic>; |
| phy-handle = <&phy0>; |
| }; |
| |
| ethernet@25000 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| device_type = "network"; |
| model = "TSEC"; |
| compatible = "gianfar"; |
| reg = <25000 1000>; |
| local-mac-address = [ 00 00 00 00 00 00 ]; |
| interrupts = <23 2 24 2 28 2>; |
| interrupt-parent = <&mpic>; |
| phy-handle = <&phy1>; |
| }; |
| |
| serial@4500 { |
| device_type = "serial"; |
| compatible = "ns16550"; |
| reg = <4500 100>; // reg base, size |
| clock-frequency = <0>; // should we fill in in uboot? |
| interrupts = <2a 2>; |
| interrupt-parent = <&mpic>; |
| }; |
| |
| serial@4600 { |
| device_type = "serial"; |
| compatible = "ns16550"; |
| reg = <4600 100>; // reg base, size |
| clock-frequency = <0>; // should we fill in in uboot? |
| interrupts = <2a 2>; |
| interrupt-parent = <&mpic>; |
| }; |
| |
| mpic: pic@40000 { |
| clock-frequency = <0>; |
| interrupt-controller; |
| #address-cells = <0>; |
| #interrupt-cells = <2>; |
| reg = <40000 40000>; |
| compatible = "chrp,open-pic"; |
| device_type = "open-pic"; |
| big-endian; |
| }; |
| |
| cpm@919c0 { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| compatible = "fsl,mpc8555-cpm", "fsl,cpm2"; |
| reg = <919c0 30>; |
| ranges; |
| |
| muram@80000 { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0 80000 10000>; |
| |
| data@0 { |
| compatible = "fsl,cpm-muram-data"; |
| reg = <0 2000 9000 1000>; |
| }; |
| }; |
| |
| brg@919f0 { |
| compatible = "fsl,mpc8555-brg", |
| "fsl,cpm2-brg", |
| "fsl,cpm-brg"; |
| reg = <919f0 10 915f0 10>; |
| }; |
| |
| cpmpic: pic@90c00 { |
| interrupt-controller; |
| #address-cells = <0>; |
| #interrupt-cells = <2>; |
| interrupts = <2e 2>; |
| interrupt-parent = <&mpic>; |
| reg = <90c00 80>; |
| compatible = "fsl,mpc8555-cpm-pic", "fsl,cpm2-pic"; |
| }; |
| }; |
| }; |
| |
| pci1: pci@e0008000 { |
| interrupt-map-mask = <1f800 0 0 7>; |
| interrupt-map = < |
| |
| /* IDSEL 0x10 */ |
| 08000 0 0 1 &mpic 0 1 |
| 08000 0 0 2 &mpic 1 1 |
| 08000 0 0 3 &mpic 2 1 |
| 08000 0 0 4 &mpic 3 1 |
| |
| /* IDSEL 0x11 */ |
| 08800 0 0 1 &mpic 0 1 |
| 08800 0 0 2 &mpic 1 1 |
| 08800 0 0 3 &mpic 2 1 |
| 08800 0 0 4 &mpic 3 1 |
| |
| /* IDSEL 0x12 (Slot 1) */ |
| 09000 0 0 1 &mpic 0 1 |
| 09000 0 0 2 &mpic 1 1 |
| 09000 0 0 3 &mpic 2 1 |
| 09000 0 0 4 &mpic 3 1 |
| |
| /* IDSEL 0x13 (Slot 2) */ |
| 09800 0 0 1 &mpic 1 1 |
| 09800 0 0 2 &mpic 2 1 |
| 09800 0 0 3 &mpic 3 1 |
| 09800 0 0 4 &mpic 0 1 |
| |
| /* IDSEL 0x14 (Slot 3) */ |
| 0a000 0 0 1 &mpic 2 1 |
| 0a000 0 0 2 &mpic 3 1 |
| 0a000 0 0 3 &mpic 0 1 |
| 0a000 0 0 4 &mpic 1 1 |
| |
| /* IDSEL 0x15 (Slot 4) */ |
| 0a800 0 0 1 &mpic 3 1 |
| 0a800 0 0 2 &mpic 0 1 |
| 0a800 0 0 3 &mpic 1 1 |
| 0a800 0 0 4 &mpic 2 1 |
| |
| /* Bus 1 (Tundra Bridge) */ |
| /* IDSEL 0x12 (ISA bridge) */ |
| 19000 0 0 1 &mpic 0 1 |
| 19000 0 0 2 &mpic 1 1 |
| 19000 0 0 3 &mpic 2 1 |
| 19000 0 0 4 &mpic 3 1>; |
| interrupt-parent = <&mpic>; |
| interrupts = <18 2>; |
| bus-range = <0 0>; |
| ranges = <02000000 0 80000000 80000000 0 20000000 |
| 01000000 0 00000000 e2000000 0 00100000>; |
| clock-frequency = <3f940aa>; |
| #interrupt-cells = <1>; |
| #size-cells = <2>; |
| #address-cells = <3>; |
| reg = <e0008000 1000>; |
| compatible = "fsl,mpc8540-pci"; |
| device_type = "pci"; |
| |
| i8259@19000 { |
| interrupt-controller; |
| device_type = "interrupt-controller"; |
| reg = <19000 0 0 0 1>; |
| #address-cells = <0>; |
| #interrupt-cells = <2>; |
| compatible = "chrp,iic"; |
| interrupts = <1>; |
| interrupt-parent = <&pci1>; |
| }; |
| }; |
| |
| pci@e0009000 { |
| interrupt-map-mask = <f800 0 0 7>; |
| interrupt-map = < |
| |
| /* IDSEL 0x15 */ |
| a800 0 0 1 &mpic b 1 |
| a800 0 0 2 &mpic b 1 |
| a800 0 0 3 &mpic b 1 |
| a800 0 0 4 &mpic b 1>; |
| interrupt-parent = <&mpic>; |
| interrupts = <19 2>; |
| bus-range = <0 0>; |
| ranges = <02000000 0 a0000000 a0000000 0 20000000 |
| 01000000 0 00000000 e3000000 0 00100000>; |
| clock-frequency = <3f940aa>; |
| #interrupt-cells = <1>; |
| #size-cells = <2>; |
| #address-cells = <3>; |
| reg = <e0009000 1000>; |
| compatible = "fsl,mpc8540-pci"; |
| device_type = "pci"; |
| }; |
| }; |
