| /* |
| * SBC8349E Device Tree Source |
| * |
| * Copyright 2007 Wind River Inc. |
| * |
| * Paul Gortmaker (see MAINTAINERS for contact information) |
| * |
| * -based largely on the Freescale MPC834x_MDS dts. |
| * |
| * This program is free software; you can redistribute it and/or modify it |
| * under the terms of the GNU General Public License as published by the |
| * Free Software Foundation; either version 2 of the License, or (at your |
| * option) any later version. |
| */ |
| |
| /dts-v1/; |
| |
| / { |
| model = "SBC8349E"; |
| compatible = "SBC834xE"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| aliases { |
| ethernet0 = &enet0; |
| ethernet1 = &enet1; |
| serial0 = &serial0; |
| serial1 = &serial1; |
| pci0 = &pci0; |
| }; |
| |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| PowerPC,8349@0 { |
| device_type = "cpu"; |
| reg = <0x0>; |
| d-cache-line-size = <32>; |
| i-cache-line-size = <32>; |
| d-cache-size = <32768>; |
| i-cache-size = <32768>; |
| timebase-frequency = <0>; // from bootloader |
| bus-frequency = <0>; // from bootloader |
| clock-frequency = <0>; // from bootloader |
| }; |
| }; |
| |
| memory { |
| device_type = "memory"; |
| reg = <0x00000000 0x10000000>; // 256MB at 0 |
| }; |
| |
| soc8349@e0000000 { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| device_type = "soc"; |
| ranges = <0x0 0xe0000000 0x00100000>; |
| reg = <0xe0000000 0x00000200>; |
| bus-frequency = <0>; |
| |
| wdt@200 { |
| compatible = "mpc83xx_wdt"; |
| reg = <0x200 0x100>; |
| }; |
| |
| i2c@3000 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| cell-index = <0>; |
| compatible = "fsl-i2c"; |
| reg = <0x3000 0x100>; |
| interrupts = <14 0x8>; |
| interrupt-parent = <&ipic>; |
| dfsrr; |
| }; |
| |
| i2c@3100 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| cell-index = <1>; |
| compatible = "fsl-i2c"; |
| reg = <0x3100 0x100>; |
| interrupts = <15 0x8>; |
| interrupt-parent = <&ipic>; |
| dfsrr; |
| }; |
| |
| spi@7000 { |
| cell-index = <0>; |
| compatible = "fsl,spi"; |
| reg = <0x7000 0x1000>; |
| interrupts = <16 0x8>; |
| interrupt-parent = <&ipic>; |
| mode = "cpu"; |
| }; |
| |
| dma@82a8 { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| compatible = "fsl,mpc8349-dma", "fsl,elo-dma"; |
| reg = <0x82a8 4>; |
| ranges = <0 0x8100 0x1a8>; |
| interrupt-parent = <&ipic>; |
| interrupts = <71 8>; |
| cell-index = <0>; |
| dma-channel@0 { |
| compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; |
| reg = <0 0x80>; |
| cell-index = <0>; |
| interrupt-parent = <&ipic>; |
| interrupts = <71 8>; |
| }; |
| dma-channel@80 { |
| compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; |
| reg = <0x80 0x80>; |
| cell-index = <1>; |
| interrupt-parent = <&ipic>; |
| interrupts = <71 8>; |
| }; |
| dma-channel@100 { |
| compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; |
| reg = <0x100 0x80>; |
| cell-index = <2>; |
| interrupt-parent = <&ipic>; |
| interrupts = <71 8>; |
| }; |
| dma-channel@180 { |
| compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; |
| reg = <0x180 0x28>; |
| cell-index = <3>; |
| interrupt-parent = <&ipic>; |
| interrupts = <71 8>; |
| }; |
| }; |
| |
| /* phy type (ULPI or SERIAL) are only types supported for MPH */ |
| /* port = 0 or 1 */ |
| usb@22000 { |
| compatible = "fsl-usb2-mph"; |
| reg = <0x22000 0x1000>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| interrupt-parent = <&ipic>; |
| interrupts = <39 0x8>; |
| phy_type = "ulpi"; |
| port0; |
| }; |
| |
| enet0: ethernet@24000 { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| cell-index = <0>; |
| device_type = "network"; |
| model = "TSEC"; |
| compatible = "gianfar"; |
| reg = <0x24000 0x1000>; |
| ranges = <0x0 0x24000 0x1000>; |
| local-mac-address = [ 00 00 00 00 00 00 ]; |
| interrupts = <32 0x8 33 0x8 34 0x8>; |
| interrupt-parent = <&ipic>; |
| tbi-handle = <&tbi0>; |
| phy-handle = <&phy0>; |
| linux,network-index = <0>; |
| |
| mdio@520 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| compatible = "fsl,gianfar-mdio"; |
| reg = <0x520 0x20>; |
| |
| phy0: ethernet-phy@19 { |
| interrupt-parent = <&ipic>; |
| interrupts = <20 0x8>; |
| reg = <0x19>; |
| device_type = "ethernet-phy"; |
| }; |
| |
| phy1: ethernet-phy@1a { |
| interrupt-parent = <&ipic>; |
| interrupts = <21 0x8>; |
| reg = <0x1a>; |
| device_type = "ethernet-phy"; |
| }; |
| |
| tbi0: tbi-phy@11 { |
| reg = <0x11>; |
| device_type = "tbi-phy"; |
| }; |
| }; |
| }; |
| |
| enet1: ethernet@25000 { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| cell-index = <1>; |
| device_type = "network"; |
| model = "TSEC"; |
| compatible = "gianfar"; |
| reg = <0x25000 0x1000>; |
| ranges = <0x0 0x25000 0x1000>; |
| local-mac-address = [ 00 00 00 00 00 00 ]; |
| interrupts = <35 0x8 36 0x8 37 0x8>; |
| interrupt-parent = <&ipic>; |
| tbi-handle = <&tbi1>; |
| phy-handle = <&phy1>; |
| linux,network-index = <1>; |
| |
| mdio@520 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| compatible = "fsl,gianfar-tbi"; |
| reg = <0x520 0x20>; |
| |
| tbi1: tbi-phy@11 { |
| reg = <0x11>; |
| device_type = "tbi-phy"; |
| }; |
| }; |
| }; |
| |
| serial0: serial@4500 { |
| cell-index = <0>; |
| device_type = "serial"; |
| compatible = "ns16550"; |
| reg = <0x4500 0x100>; |
| clock-frequency = <0>; |
| interrupts = <9 0x8>; |
| interrupt-parent = <&ipic>; |
| }; |
| |
| serial1: serial@4600 { |
| cell-index = <1>; |
| device_type = "serial"; |
| compatible = "ns16550"; |
| reg = <0x4600 0x100>; |
| clock-frequency = <0>; |
| interrupts = <10 0x8>; |
| interrupt-parent = <&ipic>; |
| }; |
| |
| crypto@30000 { |
| compatible = "fsl,sec2.0"; |
| reg = <0x30000 0x10000>; |
| interrupts = <11 0x8>; |
| interrupt-parent = <&ipic>; |
| fsl,num-channels = <4>; |
| fsl,channel-fifo-len = <24>; |
| fsl,exec-units-mask = <0x7e>; |
| fsl,descriptor-types-mask = <0x01010ebf>; |
| }; |
| |
| /* IPIC |
| * interrupts cell = <intr #, sense> |
| * sense values match linux IORESOURCE_IRQ_* defines: |
| * sense == 8: Level, low assertion |
| * sense == 2: Edge, high-to-low change |
| */ |
| ipic: pic@700 { |
| interrupt-controller; |
| #address-cells = <0>; |
| #interrupt-cells = <2>; |
| reg = <0x700 0x100>; |
| device_type = "ipic"; |
| }; |
| }; |
| |
| localbus@e0005000 { |
| #address-cells = <2>; |
| #size-cells = <1>; |
| compatible = "fsl,mpc8349-localbus", "simple-bus"; |
| reg = <0xe0005000 0x1000>; |
| interrupts = <77 0x8>; |
| interrupt-parent = <&ipic>; |
| ranges = <0x0 0x0 0xff800000 0x00800000 /* 8MB Flash */ |
| 0x1 0x0 0xf8000000 0x00002000 /* 8KB EEPROM */ |
| 0x2 0x0 0x10000000 0x04000000 /* 64MB SDRAM */ |
| 0x3 0x0 0x10000000 0x04000000>; /* 64MB SDRAM */ |
| |
| flash@0,0 { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| compatible = "intel,28F640J3A", "cfi-flash"; |
| reg = <0x0 0x0 0x800000>; |
| bank-width = <2>; |
| device-width = <1>; |
| |
| partition@0 { |
| label = "u-boot"; |
| reg = <0x00000000 0x00040000>; |
| read-only; |
| }; |
| |
| partition@40000 { |
| label = "user"; |
| reg = <0x00040000 0x006c0000>; |
| }; |
| |
| partition@700000 { |
| label = "legacy u-boot"; |
| reg = <0x00700000 0x00100000>; |
| read-only; |
| }; |
| |
| }; |
| }; |
| |
| pci0: pci@e0008500 { |
| interrupt-map-mask = <0xf800 0x0 0x0 0x7>; |
| interrupt-map = < |
| |
| /* IDSEL 0x11 */ |
| 0x8800 0x0 0x0 0x1 &ipic 48 0x8 |
| 0x8800 0x0 0x0 0x2 &ipic 17 0x8 |
| 0x8800 0x0 0x0 0x3 &ipic 18 0x8 |
| 0x8800 0x0 0x0 0x4 &ipic 19 0x8>; |
| |
| interrupt-parent = <&ipic>; |
| interrupts = <0x42 0x8>; |
| bus-range = <0 0>; |
| ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000 |
| 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000 |
| 0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>; |
| clock-frequency = <66666666>; |
| #interrupt-cells = <1>; |
| #size-cells = <2>; |
| #address-cells = <3>; |
| reg = <0xe0008500 0x100 /* internal registers */ |
| 0xe0008300 0x8>; /* config space access registers */ |
| compatible = "fsl,mpc8349-pci"; |
| device_type = "pci"; |
| }; |
| }; |
