| # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| %YAML 1.2 |
| --- |
| $id: http://devicetree.org/schemas/pinctrl/mediatek,mt7986-pinctrl.yaml# |
| $schema: http://devicetree.org/meta-schemas/core.yaml# |
| |
| title: MediaTek MT7986 Pin Controller |
| |
| maintainers: |
| - Sean Wang <sean.wang@kernel.org> |
| |
| description: |
| The MediaTek's MT7986 Pin controller is used to control SoC pins. |
| |
| properties: |
| compatible: |
| enum: |
| - mediatek,mt7986a-pinctrl |
| - mediatek,mt7986b-pinctrl |
| |
| reg: |
| minItems: 8 |
| maxItems: 8 |
| |
| reg-names: |
| items: |
| - const: gpio |
| - const: iocfg_rt |
| - const: iocfg_rb |
| - const: iocfg_lt |
| - const: iocfg_lb |
| - const: iocfg_tr |
| - const: iocfg_tl |
| - const: eint |
| |
| gpio-controller: true |
| |
| "#gpio-cells": |
| const: 2 |
| description: |
| Number of cells in GPIO specifier. Since the generic GPIO binding is used, |
| the amount of cells must be specified as 2. See the below mentioned gpio |
| binding representation for description of particular cells. |
| |
| gpio-ranges: |
| minItems: 1 |
| maxItems: 5 |
| description: |
| GPIO valid number range. |
| |
| interrupt-controller: true |
| |
| interrupts: |
| maxItems: 1 |
| |
| "#interrupt-cells": |
| const: 2 |
| |
| allOf: |
| - $ref: pinctrl.yaml# |
| |
| required: |
| - compatible |
| - reg |
| - reg-names |
| - gpio-controller |
| - "#gpio-cells" |
| |
| patternProperties: |
| '-pins$': |
| type: object |
| additionalProperties: false |
| |
| patternProperties: |
| '^.*mux.*$': |
| type: object |
| additionalProperties: false |
| description: | |
| pinmux configuration nodes. |
| |
| The following table shows the effective values of "group", "function" |
| properties and chip pinout pins |
| |
| groups function pins (in pin#) |
| --------------------------------------------------------------------- |
| "watchdog" "watchdog" 0 |
| "wifi_led" "led" 1, 2 |
| "i2c" "i2c" 3, 4 |
| "uart1_0" "uart" 7, 8, 9, 10 |
| "uart1_rx_tx" "uart" 42, 43 |
| "uart1_cts_rts" "uart" 44, 45 |
| "pcie_clk" "pcie" 9 |
| "pcie_wake" "pcie" 10 |
| "spi1_0" "spi" 11, 12, 13, 14 |
| "pwm1_1" "pwm" 20, |
| "pwm0" "pwm" 21, |
| "pwm1_0" "pwm" 22, |
| "snfi" "flash" 23, 24, 25, 26, 27, 28 |
| "spi1_2" "spi" 29, 30, 31, 32 |
| "emmc_45" "emmc" 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, |
| 32 |
| |
| "spi1_1" "spi" 23, 24, 25, 26 |
| "uart1_2_rx_tx" "uart" 29, 30 |
| "uart1_2_cts_rts" "uart" 31, 32 |
| "uart1_1" "uart" 23, 24, 25, 26 |
| "uart2_0_rx_tx" "uart" 29, 30 |
| "uart2_0_cts_rts" "uart" 31, 32 |
| "spi0" "spi" 33, 34, 35, 36 |
| "spi0_wp_hold" "spi" 37, 38 |
| "uart1_3_rx_tx" "uart" 35, 36 |
| "uart1_3_cts_rts" "uart" 37, 38 |
| "uart2_1" "uart" 33, 34, 35, 36 |
| "spi1_3" "spi" 33, 34, 35, 36 |
| "uart0" "uart" 39, 40 |
| "pcie_pereset" "pcie" 41 |
| "uart1" "uart" 42, 43, 44, 45 |
| "uart2" "uart" 46, 47, 48, 49 |
| "emmc_51" "emmc" 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, |
| 60, 61 |
| |
| "pcm" "audio" 62, 63, 64, 65 |
| "i2s" "audio" 62, 63, 64, 65 |
| "switch_int" "eth" 66 |
| "mdc_mdio" "eth" 67 |
| "wf_2g" "wifi" 74, 75, 76, 77, 78, 79, 80, 81, 82, 83 |
| "wf_5g" "wifi" 91, 92, 93, 94, 95, 96, 97, 98, 99, 100 |
| "wf_dbdc" "wifi" 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, |
| 84, 85 |
| |
| $ref: /schemas/pinctrl/pinmux-node.yaml |
| properties: |
| function: |
| description: |
| A string containing the name of the function to mux to the group. |
| There is no "audio", "pcie" functions on mt7986b, you can only use |
| those functions on mt7986a. |
| enum: [audio, emmc, eth, i2c, led, flash, pcie, pwm, spi, uart, |
| watchdog, wifi] |
| groups: |
| description: |
| An array of strings. Each string contains the name of a group. |
| There is no "pcie_pereset", "uart1", "uart2" "emmc_51", "pcm", and |
| "i2s" groups on mt7986b, you can only use those groups on mt7986a. |
| required: |
| - function |
| - groups |
| |
| allOf: |
| - if: |
| properties: |
| function: |
| const: audio |
| then: |
| properties: |
| groups: |
| enum: [pcm, i2s] |
| - if: |
| properties: |
| function: |
| const: emmc |
| then: |
| properties: |
| groups: |
| enum: [emmc_45, emmc_51] |
| - if: |
| properties: |
| function: |
| const: eth |
| then: |
| properties: |
| groups: |
| enum: [switch_int, mdc_mdio] |
| - if: |
| properties: |
| function: |
| const: i2c |
| then: |
| properties: |
| groups: |
| enum: [i2c] |
| - if: |
| properties: |
| function: |
| const: led |
| then: |
| properties: |
| groups: |
| enum: [wifi_led] |
| - if: |
| properties: |
| function: |
| const: flash |
| then: |
| properties: |
| groups: |
| enum: [snfi] |
| - if: |
| properties: |
| function: |
| const: pcie |
| then: |
| properties: |
| groups: |
| items: |
| enum: [pcie_clk, pcie_wake, pcie_pereset] |
| maxItems: 3 |
| - if: |
| properties: |
| function: |
| const: pwm |
| then: |
| properties: |
| groups: |
| items: |
| enum: [pwm0, pwm1_0, pwm1_1] |
| maxItems: 2 |
| - if: |
| properties: |
| function: |
| const: spi |
| then: |
| properties: |
| groups: |
| items: |
| enum: [spi0, spi0_wp_hold, spi1_0, spi1_1, spi1_2, spi1_3] |
| maxItems: 2 |
| - if: |
| properties: |
| function: |
| const: uart |
| then: |
| properties: |
| groups: |
| items: |
| enum: [uart1_0, uart1_rx_tx, uart1_cts_rts, uart1_1, |
| uart1_2_rx_tx, uart1_2_cts_rts, uart1_3_rx_tx, |
| uart1_3_cts_rts, uart2_0_rx_tx, uart2_0_cts_rts, |
| uart2_1, uart0, uart1, uart2] |
| maxItems: 2 |
| - if: |
| properties: |
| function: |
| const: watchdog |
| then: |
| properties: |
| groups: |
| enum: [watchdog] |
| - if: |
| properties: |
| function: |
| const: wifi |
| then: |
| properties: |
| groups: |
| items: |
| enum: [wf_2g, wf_5g, wf_dbdc] |
| maxItems: 3 |
| '^.*conf.*$': |
| type: object |
| additionalProperties: false |
| description: |
| pinconf configuration nodes. |
| $ref: /schemas/pinctrl/pincfg-node.yaml |
| |
| properties: |
| pins: |
| description: |
| An array of strings. Each string contains the name of a pin. There |
| is no PIN 41 to PIN 65 above on mt7686b, you can only use those |
| pins on mt7986a. |
| items: |
| enum: [SYS_WATCHDOG, WF2G_LED, WF5G_LED, I2C_SCL, I2C_SDA, GPIO_0, |
| GPIO_1, GPIO_2, GPIO_3, GPIO_4, GPIO_5, GPIO_6, GPIO_7, |
| GPIO_8, GPIO_9, GPIO_10, GPIO_11, GPIO_12, GPIO_13, |
| GPIO_14, GPIO_15, PWM0, PWM1, SPI0_CLK, SPI0_MOSI, |
| SPI0_MISO, SPI0_CS, SPI0_HOLD, SPI0_WP, SPI1_CLK, |
| SPI1_MOSI, SPI1_MISO, SPI1_CS, SPI2_CLK, SPI2_MOSI, |
| SPI2_MISO, SPI2_CS, SPI2_HOLD, SPI2_WP, UART0_RXD, |
| UART0_TXD, PCIE_PERESET_N, UART1_RXD, UART1_TXD, UART1_CTS, |
| UART1_RTS, UART2_RXD, UART2_TXD, UART2_CTS, UART2_RTS, |
| EMMC_DATA_0, EMMC_DATA_1, EMMC_DATA_2, EMMC_DATA_3, |
| EMMC_DATA_4, EMMC_DATA_5, EMMC_DATA_6, EMMC_DATA_7, |
| EMMC_CMD, EMMC_CK, EMMC_DSL, EMMC_RSTB, PCM_DTX, PCM_DRX, |
| PCM_CLK, PCM_FS, MT7531_INT, SMI_MDC, SMI_MDIO, |
| WF0_DIG_RESETB, WF0_CBA_RESETB, WF0_XO_REQ, WF0_TOP_CLK, |
| WF0_TOP_DATA, WF0_HB1, WF0_HB2, WF0_HB3, WF0_HB4, WF0_HB0, |
| WF0_HB0_B, WF0_HB5, WF0_HB6, WF0_HB7, WF0_HB8, WF0_HB9, |
| WF0_HB10, WF1_DIG_RESETB, WF1_CBA_RESETB, WF1_XO_REQ, |
| WF1_TOP_CLK, WF1_TOP_DATA, WF1_HB1, WF1_HB2, WF1_HB3, |
| WF1_HB4, WF1_HB0, WF1_HB0_B, WF1_HB5, WF1_HB6, WF1_HB7, |
| WF1_HB8] |
| maxItems: 101 |
| |
| bias-disable: true |
| |
| bias-pull-up: |
| oneOf: |
| - type: boolean |
| description: normal pull up. |
| - enum: [100, 101, 102, 103] |
| description: |
| PUPD/R1/R0 pull down type. See MTK_PUPD_SET_R1R0 defines in |
| dt-bindings/pinctrl/mt65xx.h. |
| |
| bias-pull-down: |
| oneOf: |
| - type: boolean |
| description: normal pull down. |
| - enum: [100, 101, 102, 103] |
| description: |
| PUPD/R1/R0 pull down type. See MTK_PUPD_SET_R1R0 defines in |
| dt-bindings/pinctrl/mt65xx.h. |
| |
| input-enable: true |
| |
| input-disable: true |
| |
| output-enable: true |
| |
| output-low: true |
| |
| output-high: true |
| |
| input-schmitt-enable: true |
| |
| input-schmitt-disable: true |
| |
| drive-strength: |
| enum: [2, 4, 6, 8, 10, 12, 14, 16] |
| |
| mediatek,pull-up-adv: |
| description: | |
| Valid arguments for 'mediatek,pull-up-adv' are '0', '1', '2', '3' |
| Pull up settings for 2 pull resistors, R0 and R1. Valid arguments |
| are described as below: |
| 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled. |
| 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled. |
| 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled. |
| 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled. |
| $ref: /schemas/types.yaml#/definitions/uint32 |
| enum: [0, 1, 2, 3] |
| |
| mediatek,pull-down-adv: |
| description: | |
| Valid arguments for 'mediatek,pull-up-adv' are '0', '1', '2', '3' |
| Pull down settings for 2 pull resistors, R0 and R1. Valid arguments |
| are described as below: |
| 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled. |
| 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled. |
| 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled. |
| 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled. |
| $ref: /schemas/types.yaml#/definitions/uint32 |
| enum: [0, 1, 2, 3] |
| |
| required: |
| - pins |
| |
| additionalProperties: false |
| |
| examples: |
| - | |
| #include <dt-bindings/interrupt-controller/irq.h> |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| #include <dt-bindings/pinctrl/mt65xx.h> |
| |
| soc { |
| #address-cells = <2>; |
| #size-cells = <2>; |
| pio: pinctrl@1001f000 { |
| compatible = "mediatek,mt7986a-pinctrl"; |
| reg = <0 0x1001f000 0 0x1000>, |
| <0 0x11c30000 0 0x1000>, |
| <0 0x11c40000 0 0x1000>, |
| <0 0x11e20000 0 0x1000>, |
| <0 0x11e30000 0 0x1000>, |
| <0 0x11f00000 0 0x1000>, |
| <0 0x11f10000 0 0x1000>, |
| <0 0x1000b000 0 0x1000>; |
| reg-names = "gpio", "iocfg_rt", "iocfg_rb", "iocfg_lt", |
| "iocfg_lb", "iocfg_tr", "iocfg_tl", "eint"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| gpio-ranges = <&pio 0 0 100>; |
| interrupt-controller; |
| interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-parent = <&gic>; |
| #interrupt-cells = <2>; |
| |
| pcie_pins: pcie-pins { |
| mux { |
| function = "pcie"; |
| groups = "pcie_clk", "pcie_wake", "pcie_pereset"; |
| }; |
| }; |
| |
| pwm_pins: pwm-pins { |
| mux { |
| function = "pwm"; |
| groups = "pwm0", "pwm1_0"; |
| }; |
| }; |
| |
| spi0_pins: spi0-pins { |
| mux { |
| function = "spi"; |
| groups = "spi0", "spi0_wp_hold"; |
| }; |
| }; |
| |
| uart1_pins: uart1-pins { |
| mux { |
| function = "uart"; |
| groups = "uart1"; |
| }; |
| }; |
| |
| uart1_3_pins: uart1-3-pins { |
| mux { |
| function = "uart"; |
| groups = "uart1_3_rx_tx", "uart1_3_cts_rts"; |
| }; |
| }; |
| |
| uart2_pins: uart2-pins { |
| mux { |
| function = "uart"; |
| groups = "uart2"; |
| }; |
| }; |
| |
| mmc0_pins_default: mmc0-pins { |
| mux { |
| function = "emmc"; |
| groups = "emmc_51"; |
| }; |
| conf-cmd-dat { |
| pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2", |
| "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5", |
| "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD"; |
| input-enable; |
| drive-strength = <4>; |
| bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */ |
| }; |
| conf-clk { |
| pins = "EMMC_CK"; |
| drive-strength = <6>; |
| bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */ |
| }; |
| conf-ds { |
| pins = "EMMC_DSL"; |
| bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */ |
| }; |
| conf-rst { |
| pins = "EMMC_RSTB"; |
| drive-strength = <4>; |
| bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */ |
| }; |
| }; |
| |
| }; |
| }; |
