blob: fa90981db40b38d378e42bed0a949a6776acbbcd [file] [log] [blame]
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/qcom,msm8994-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm MSM8994 TLMM pin controller
maintainers:
- Bjorn Andersson <andersson@kernel.org>
- Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
description:
Top Level Mode Multiplexer pin controller in Qualcomm MSM8994 SoC.
properties:
compatible:
enum:
- qcom,msm8992-pinctrl
- qcom,msm8994-pinctrl
reg:
maxItems: 1
interrupts:
maxItems: 1
gpio-reserved-ranges:
minItems: 1
maxItems: 73
gpio-line-names:
maxItems: 146
patternProperties:
"-state$":
oneOf:
- $ref: "#/$defs/qcom-msm8994-tlmm-state"
- patternProperties:
"-pins$":
$ref: "#/$defs/qcom-msm8994-tlmm-state"
additionalProperties: false
$defs:
qcom-msm8994-tlmm-state:
type: object
description:
Pinctrl node's client devices use subnodes for desired pin configuration.
Client device subnodes use below standard properties.
$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
unevaluatedProperties: false
properties:
pins:
description:
List of gpio pins affected by the properties specified in this
subnode.
items:
oneOf:
- pattern: "^gpio([0-9]|[1-9][0-9]|1[0-3][0-9]|14[0-5])$"
- enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc1_rclk, sdc2_clk,
sdc2_cmd, sdc2_data, sdc3_clk, sdc3_cmd, sdc3_data ]
minItems: 1
maxItems: 36
function:
description:
Specify the alternative function to be configured for the specified
pins.
enum: [ gpio, audio_ref_clk, blsp_i2c1, blsp_i2c2, blsp_i2c3,
blsp_i2c4, blsp_i2c5, blsp_i2c6, blsp_i2c7, blsp_i2c8,
blsp_i2c9, blsp_i2c10, blsp_i2c11, blsp_i2c12, blsp_spi1,
blsp_spi1_cs1, blsp_spi1_cs2, blsp_spi1_cs3, blsp_spi2,
blsp_spi2_cs1, blsp_spi2_cs2, blsp_spi2_cs3, blsp_spi3,
blsp_spi4, blsp_spi5, blsp_spi6, blsp_spi7, blsp_spi8,
blsp_spi9, blsp_spi10, blsp_spi10_cs1, blsp_spi10_cs2,
blsp_spi10_cs3, blsp_spi11, blsp_spi12, blsp_uart1, blsp_uart2,
blsp_uart3, blsp_uart4, blsp_uart5, blsp_uart6, blsp_uart7,
blsp_uart8, blsp_uart9, blsp_uart10, blsp_uart11, blsp_uart12,
blsp_uim1, blsp_uim2, blsp_uim3, blsp_uim4, blsp_uim5,
blsp_uim6, blsp_uim7, blsp_uim8, blsp_uim9, blsp_uim10,
blsp_uim11, blsp_uim12, blsp11_i2c_scl_b, blsp11_i2c_sda_b,
blsp11_uart_rx_b, blsp11_uart_tx_b, cam_mclk0, cam_mclk1,
cam_mclk2, cam_mclk3, cci_async_in0, cci_async_in1,
cci_async_in2, cci_i2c0, cci_i2c1, cci_timer0, cci_timer1,
cci_timer2, cci_timer3, cci_timer4, gcc_gp1_clk_a,
gcc_gp1_clk_b, gcc_gp2_clk_a, gcc_gp2_clk_b, gcc_gp3_clk_a,
gcc_gp3_clk_b, gp_mn, gp_pdm0, gp_pdm1, gp_pdm2, gp0_clk,
gp1_clk, gps_tx, gsm_tx, hdmi_cec, hdmi_ddc, hdmi_hpd,
hdmi_rcv, mdp_vsync, mss_lte, nav_pps, nav_tsync,
qdss_cti_trig_in_a, qdss_cti_trig_in_b, qdss_cti_trig_in_c,
qdss_cti_trig_in_d, qdss_cti_trig_out_a, qdss_cti_trig_out_b,
qdss_cti_trig_out_c, qdss_cti_trig_out_d, qdss_traceclk_a,
qdss_traceclk_b, qdss_tracectl_a, qdss_tracectl_b,
qdss_tracedata_a, qdss_tracedata_b, qua_mi2s, pci_e0, pci_e1,
pri_mi2s, sdc4, sec_mi2s, slimbus, spkr_i2s, ter_mi2s, tsif1,
tsif2, uim_batt_alarm, uim1, uim2, uim3, uim4 ]
required:
- pins
allOf:
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
required:
- compatible
- reg
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
tlmm: pinctrl@fd510000 {
compatible = "qcom,msm8994-pinctrl";
reg = <0xfd510000 0x4000>;
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
gpio-ranges = <&tlmm 0 0 146>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
blsp1-uart2-default-state {
function = "blsp_uart2";
pins = "gpio4", "gpio5";
drive-strength = <16>;
bias-disable;
};
blsp1-spi1-default-state {
default-pins {
pins = "gpio0", "gpio1", "gpio3";
function = "blsp_spi1";
drive-strength = <10>;
bias-pull-down;
};
cs-pins {
pins = "gpio8";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
};
};