| #ifndef A2XX_XML |
| #define A2XX_XML |
| |
| /* Autogenerated file, DO NOT EDIT manually! |
| |
| This file was generated by the rules-ng-ng headergen tool in this git repository: |
| http://github.com/freedreno/envytools/ |
| git clone https://github.com/freedreno/envytools.git |
| |
| The rules-ng-ng source files this header was generated from are: |
| - /home/robclark/src/envytools/rnndb/adreno.xml ( 594 bytes, from 2020-07-23 21:58:14) |
| - /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2020-07-23 21:58:14) |
| - /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 90159 bytes, from 2020-07-23 21:58:14) |
| - /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 14386 bytes, from 2020-07-23 21:58:14) |
| - /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 65048 bytes, from 2020-07-23 21:58:14) |
| - /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 84226 bytes, from 2020-07-23 21:58:14) |
| - /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112556 bytes, from 2020-07-23 21:58:14) |
| - /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 149461 bytes, from 2020-07-23 21:58:14) |
| - /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 184695 bytes, from 2020-07-23 21:58:14) |
| - /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 11218 bytes, from 2020-07-23 21:58:14) |
| - /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2020-07-23 21:58:14) |
| - /home/robclark/src/envytools/rnndb/adreno/adreno_control_regs.xml ( 4559 bytes, from 2020-07-23 21:58:14) |
| - /home/robclark/src/envytools/rnndb/adreno/adreno_pipe_regs.xml ( 2872 bytes, from 2020-07-23 21:58:14) |
| |
| Copyright (C) 2013-2020 by the following authors: |
| - Rob Clark <robdclark@gmail.com> (robclark) |
| - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin) |
| |
| Permission is hereby granted, free of charge, to any person obtaining |
| a copy of this software and associated documentation files (the |
| "Software"), to deal in the Software without restriction, including |
| without limitation the rights to use, copy, modify, merge, publish, |
| distribute, sublicense, and/or sell copies of the Software, and to |
| permit persons to whom the Software is furnished to do so, subject to |
| the following conditions: |
| |
| The above copyright notice and this permission notice (including the |
| next paragraph) shall be included in all copies or substantial |
| portions of the Software. |
| |
| THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
| EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. |
| IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE |
| LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION |
| OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION |
| WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
| */ |
| |
| |
| enum a2xx_rb_dither_type { |
| DITHER_PIXEL = 0, |
| DITHER_SUBPIXEL = 1, |
| }; |
| |
| enum a2xx_colorformatx { |
| COLORX_4_4_4_4 = 0, |
| COLORX_1_5_5_5 = 1, |
| COLORX_5_6_5 = 2, |
| COLORX_8 = 3, |
| COLORX_8_8 = 4, |
| COLORX_8_8_8_8 = 5, |
| COLORX_S8_8_8_8 = 6, |
| COLORX_16_FLOAT = 7, |
| COLORX_16_16_FLOAT = 8, |
| COLORX_16_16_16_16_FLOAT = 9, |
| COLORX_32_FLOAT = 10, |
| COLORX_32_32_FLOAT = 11, |
| COLORX_32_32_32_32_FLOAT = 12, |
| COLORX_2_3_3 = 13, |
| COLORX_8_8_8 = 14, |
| }; |
| |
| enum a2xx_sq_surfaceformat { |
| FMT_1_REVERSE = 0, |
| FMT_1 = 1, |
| FMT_8 = 2, |
| FMT_1_5_5_5 = 3, |
| FMT_5_6_5 = 4, |
| FMT_6_5_5 = 5, |
| FMT_8_8_8_8 = 6, |
| FMT_2_10_10_10 = 7, |
| FMT_8_A = 8, |
| FMT_8_B = 9, |
| FMT_8_8 = 10, |
| FMT_Cr_Y1_Cb_Y0 = 11, |
| FMT_Y1_Cr_Y0_Cb = 12, |
| FMT_5_5_5_1 = 13, |
| FMT_8_8_8_8_A = 14, |
| FMT_4_4_4_4 = 15, |
| FMT_8_8_8 = 16, |
| FMT_DXT1 = 18, |
| FMT_DXT2_3 = 19, |
| FMT_DXT4_5 = 20, |
| FMT_10_10_10_2 = 21, |
| FMT_24_8 = 22, |
| FMT_16 = 24, |
| FMT_16_16 = 25, |
| FMT_16_16_16_16 = 26, |
| FMT_16_EXPAND = 27, |
| FMT_16_16_EXPAND = 28, |
| FMT_16_16_16_16_EXPAND = 29, |
| FMT_16_FLOAT = 30, |
| FMT_16_16_FLOAT = 31, |
| FMT_16_16_16_16_FLOAT = 32, |
| FMT_32 = 33, |
| FMT_32_32 = 34, |
| FMT_32_32_32_32 = 35, |
| FMT_32_FLOAT = 36, |
| FMT_32_32_FLOAT = 37, |
| FMT_32_32_32_32_FLOAT = 38, |
| FMT_ATI_TC_RGB = 39, |
| FMT_ATI_TC_RGBA = 40, |
| FMT_ATI_TC_555_565_RGB = 41, |
| FMT_ATI_TC_555_565_RGBA = 42, |
| FMT_ATI_TC_RGBA_INTERP = 43, |
| FMT_ATI_TC_555_565_RGBA_INTERP = 44, |
| FMT_ETC1_RGBA_INTERP = 46, |
| FMT_ETC1_RGB = 47, |
| FMT_ETC1_RGBA = 48, |
| FMT_DXN = 49, |
| FMT_2_3_3 = 51, |
| FMT_2_10_10_10_AS_16_16_16_16 = 54, |
| FMT_10_10_10_2_AS_16_16_16_16 = 55, |
| FMT_32_32_32_FLOAT = 57, |
| FMT_DXT3A = 58, |
| FMT_DXT5A = 59, |
| FMT_CTX1 = 60, |
| }; |
| |
| enum a2xx_sq_ps_vtx_mode { |
| POSITION_1_VECTOR = 0, |
| POSITION_2_VECTORS_UNUSED = 1, |
| POSITION_2_VECTORS_SPRITE = 2, |
| POSITION_2_VECTORS_EDGE = 3, |
| POSITION_2_VECTORS_KILL = 4, |
| POSITION_2_VECTORS_SPRITE_KILL = 5, |
| POSITION_2_VECTORS_EDGE_KILL = 6, |
| MULTIPASS = 7, |
| }; |
| |
| enum a2xx_sq_sample_cntl { |
| CENTROIDS_ONLY = 0, |
| CENTERS_ONLY = 1, |
| CENTROIDS_AND_CENTERS = 2, |
| }; |
| |
| enum a2xx_dx_clip_space { |
| DXCLIP_OPENGL = 0, |
| DXCLIP_DIRECTX = 1, |
| }; |
| |
| enum a2xx_pa_su_sc_polymode { |
| POLY_DISABLED = 0, |
| POLY_DUALMODE = 1, |
| }; |
| |
| enum a2xx_rb_edram_mode { |
| EDRAM_NOP = 0, |
| COLOR_DEPTH = 4, |
| DEPTH_ONLY = 5, |
| EDRAM_COPY = 6, |
| }; |
| |
| enum a2xx_pa_sc_pattern_bit_order { |
| LITTLE = 0, |
| BIG = 1, |
| }; |
| |
| enum a2xx_pa_sc_auto_reset_cntl { |
| NEVER = 0, |
| EACH_PRIMITIVE = 1, |
| EACH_PACKET = 2, |
| }; |
| |
| enum a2xx_pa_pixcenter { |
| PIXCENTER_D3D = 0, |
| PIXCENTER_OGL = 1, |
| }; |
| |
| enum a2xx_pa_roundmode { |
| TRUNCATE = 0, |
| ROUND = 1, |
| ROUNDTOEVEN = 2, |
| ROUNDTOODD = 3, |
| }; |
| |
| enum a2xx_pa_quantmode { |
| ONE_SIXTEENTH = 0, |
| ONE_EIGTH = 1, |
| ONE_QUARTER = 2, |
| ONE_HALF = 3, |
| ONE = 4, |
| }; |
| |
| enum a2xx_rb_copy_sample_select { |
| SAMPLE_0 = 0, |
| SAMPLE_1 = 1, |
| SAMPLE_2 = 2, |
| SAMPLE_3 = 3, |
| SAMPLE_01 = 4, |
| SAMPLE_23 = 5, |
| SAMPLE_0123 = 6, |
| }; |
| |
| enum a2xx_rb_blend_opcode { |
| BLEND2_DST_PLUS_SRC = 0, |
| BLEND2_SRC_MINUS_DST = 1, |
| BLEND2_MIN_DST_SRC = 2, |
| BLEND2_MAX_DST_SRC = 3, |
| BLEND2_DST_MINUS_SRC = 4, |
| BLEND2_DST_PLUS_SRC_BIAS = 5, |
| }; |
| |
| enum a2xx_su_perfcnt_select { |
| PERF_PAPC_PASX_REQ = 0, |
| PERF_PAPC_PASX_FIRST_VECTOR = 2, |
| PERF_PAPC_PASX_SECOND_VECTOR = 3, |
| PERF_PAPC_PASX_FIRST_DEAD = 4, |
| PERF_PAPC_PASX_SECOND_DEAD = 5, |
| PERF_PAPC_PASX_VTX_KILL_DISCARD = 6, |
| PERF_PAPC_PASX_VTX_NAN_DISCARD = 7, |
| PERF_PAPC_PA_INPUT_PRIM = 8, |
| PERF_PAPC_PA_INPUT_NULL_PRIM = 9, |
| PERF_PAPC_PA_INPUT_EVENT_FLAG = 10, |
| PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT = 11, |
| PERF_PAPC_PA_INPUT_END_OF_PACKET = 12, |
| PERF_PAPC_CLPR_CULL_PRIM = 13, |
| PERF_PAPC_CLPR_VV_CULL_PRIM = 15, |
| PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM = 17, |
| PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM = 18, |
| PERF_PAPC_CLPR_CULL_TO_NULL_PRIM = 19, |
| PERF_PAPC_CLPR_VV_CLIP_PRIM = 21, |
| PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE = 23, |
| PERF_PAPC_CLPR_CLIP_PLANE_CNT_1 = 24, |
| PERF_PAPC_CLPR_CLIP_PLANE_CNT_2 = 25, |
| PERF_PAPC_CLPR_CLIP_PLANE_CNT_3 = 26, |
| PERF_PAPC_CLPR_CLIP_PLANE_CNT_4 = 27, |
| PERF_PAPC_CLPR_CLIP_PLANE_CNT_5 = 28, |
| PERF_PAPC_CLPR_CLIP_PLANE_CNT_6 = 29, |
| PERF_PAPC_CLPR_CLIP_PLANE_NEAR = 30, |
| PERF_PAPC_CLPR_CLIP_PLANE_FAR = 31, |
| PERF_PAPC_CLPR_CLIP_PLANE_LEFT = 32, |
| PERF_PAPC_CLPR_CLIP_PLANE_RIGHT = 33, |
| PERF_PAPC_CLPR_CLIP_PLANE_TOP = 34, |
| PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM = 35, |
| PERF_PAPC_CLSM_NULL_PRIM = 36, |
| PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM = 37, |
| PERF_PAPC_CLSM_CLIP_PRIM = 38, |
| PERF_PAPC_CLSM_CULL_TO_NULL_PRIM = 39, |
| PERF_PAPC_CLSM_OUT_PRIM_CNT_1 = 40, |
| PERF_PAPC_CLSM_OUT_PRIM_CNT_2 = 41, |
| PERF_PAPC_CLSM_OUT_PRIM_CNT_3 = 42, |
| PERF_PAPC_CLSM_OUT_PRIM_CNT_4 = 43, |
| PERF_PAPC_CLSM_OUT_PRIM_CNT_5 = 44, |
| PERF_PAPC_CLSM_OUT_PRIM_CNT_6_7 = 45, |
| PERF_PAPC_CLSM_NON_TRIVIAL_CULL = 46, |
| PERF_PAPC_SU_INPUT_PRIM = 47, |
| PERF_PAPC_SU_INPUT_CLIP_PRIM = 48, |
| PERF_PAPC_SU_INPUT_NULL_PRIM = 49, |
| PERF_PAPC_SU_ZERO_AREA_CULL_PRIM = 50, |
| PERF_PAPC_SU_BACK_FACE_CULL_PRIM = 51, |
| PERF_PAPC_SU_FRONT_FACE_CULL_PRIM = 52, |
| PERF_PAPC_SU_POLYMODE_FACE_CULL = 53, |
| PERF_PAPC_SU_POLYMODE_BACK_CULL = 54, |
| PERF_PAPC_SU_POLYMODE_FRONT_CULL = 55, |
| PERF_PAPC_SU_POLYMODE_INVALID_FILL = 56, |
| PERF_PAPC_SU_OUTPUT_PRIM = 57, |
| PERF_PAPC_SU_OUTPUT_CLIP_PRIM = 58, |
| PERF_PAPC_SU_OUTPUT_NULL_PRIM = 59, |
| PERF_PAPC_SU_OUTPUT_EVENT_FLAG = 60, |
| PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT = 61, |
| PERF_PAPC_SU_OUTPUT_END_OF_PACKET = 62, |
| PERF_PAPC_SU_OUTPUT_POLYMODE_FACE = 63, |
| PERF_PAPC_SU_OUTPUT_POLYMODE_BACK = 64, |
| PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT = 65, |
| PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE = 66, |
| PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK = 67, |
| PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT = 68, |
| PERF_PAPC_PASX_REQ_IDLE = 69, |
| PERF_PAPC_PASX_REQ_BUSY = 70, |
| PERF_PAPC_PASX_REQ_STALLED = 71, |
| PERF_PAPC_PASX_REC_IDLE = 72, |
| PERF_PAPC_PASX_REC_BUSY = 73, |
| PERF_PAPC_PASX_REC_STARVED_SX = 74, |
| PERF_PAPC_PASX_REC_STALLED = 75, |
| PERF_PAPC_PASX_REC_STALLED_POS_MEM = 76, |
| PERF_PAPC_PASX_REC_STALLED_CCGSM_IN = 77, |
| PERF_PAPC_CCGSM_IDLE = 78, |
| PERF_PAPC_CCGSM_BUSY = 79, |
| PERF_PAPC_CCGSM_STALLED = 80, |
| PERF_PAPC_CLPRIM_IDLE = 81, |
| PERF_PAPC_CLPRIM_BUSY = 82, |
| PERF_PAPC_CLPRIM_STALLED = 83, |
| PERF_PAPC_CLPRIM_STARVED_CCGSM = 84, |
| PERF_PAPC_CLIPSM_IDLE = 85, |
| PERF_PAPC_CLIPSM_BUSY = 86, |
| PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH = 87, |
| PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ = 88, |
| PERF_PAPC_CLIPSM_WAIT_CLIPGA = 89, |
| PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP = 90, |
| PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM = 91, |
| PERF_PAPC_CLIPGA_IDLE = 92, |
| PERF_PAPC_CLIPGA_BUSY = 93, |
| PERF_PAPC_CLIPGA_STARVED_VTE_CLIP = 94, |
| PERF_PAPC_CLIPGA_STALLED = 95, |
| PERF_PAPC_CLIP_IDLE = 96, |
| PERF_PAPC_CLIP_BUSY = 97, |
| PERF_PAPC_SU_IDLE = 98, |
| PERF_PAPC_SU_BUSY = 99, |
| PERF_PAPC_SU_STARVED_CLIP = 100, |
| PERF_PAPC_SU_STALLED_SC = 101, |
| PERF_PAPC_SU_FACENESS_CULL = 102, |
| }; |
| |
| enum a2xx_sc_perfcnt_select { |
| SC_SR_WINDOW_VALID = 0, |
| SC_CW_WINDOW_VALID = 1, |
| SC_QM_WINDOW_VALID = 2, |
| SC_FW_WINDOW_VALID = 3, |
| SC_EZ_WINDOW_VALID = 4, |
| SC_IT_WINDOW_VALID = 5, |
| SC_STARVED_BY_PA = 6, |
| SC_STALLED_BY_RB_TILE = 7, |
| SC_STALLED_BY_RB_SAMP = 8, |
| SC_STARVED_BY_RB_EZ = 9, |
| SC_STALLED_BY_SAMPLE_FF = 10, |
| SC_STALLED_BY_SQ = 11, |
| SC_STALLED_BY_SP = 12, |
| SC_TOTAL_NO_PRIMS = 13, |
| SC_NON_EMPTY_PRIMS = 14, |
| SC_NO_TILES_PASSING_QM = 15, |
| SC_NO_PIXELS_PRE_EZ = 16, |
| SC_NO_PIXELS_POST_EZ = 17, |
| }; |
| |
| enum a2xx_vgt_perfcount_select { |
| VGT_SQ_EVENT_WINDOW_ACTIVE = 0, |
| VGT_SQ_SEND = 1, |
| VGT_SQ_STALLED = 2, |
| VGT_SQ_STARVED_BUSY = 3, |
| VGT_SQ_STARVED_IDLE = 4, |
| VGT_SQ_STATIC = 5, |
| VGT_PA_EVENT_WINDOW_ACTIVE = 6, |
| VGT_PA_CLIP_V_SEND = 7, |
| VGT_PA_CLIP_V_STALLED = 8, |
| VGT_PA_CLIP_V_STARVED_BUSY = 9, |
| VGT_PA_CLIP_V_STARVED_IDLE = 10, |
| VGT_PA_CLIP_V_STATIC = 11, |
| VGT_PA_CLIP_P_SEND = 12, |
| VGT_PA_CLIP_P_STALLED = 13, |
| VGT_PA_CLIP_P_STARVED_BUSY = 14, |
| VGT_PA_CLIP_P_STARVED_IDLE = 15, |
| VGT_PA_CLIP_P_STATIC = 16, |
| VGT_PA_CLIP_S_SEND = 17, |
| VGT_PA_CLIP_S_STALLED = 18, |
| VGT_PA_CLIP_S_STARVED_BUSY = 19, |
| VGT_PA_CLIP_S_STARVED_IDLE = 20, |
| VGT_PA_CLIP_S_STATIC = 21, |
| RBIU_FIFOS_EVENT_WINDOW_ACTIVE = 22, |
| RBIU_IMMED_DATA_FIFO_STARVED = 23, |
| RBIU_IMMED_DATA_FIFO_STALLED = 24, |
| RBIU_DMA_REQUEST_FIFO_STARVED = 25, |
| RBIU_DMA_REQUEST_FIFO_STALLED = 26, |
| RBIU_DRAW_INITIATOR_FIFO_STARVED = 27, |
| RBIU_DRAW_INITIATOR_FIFO_STALLED = 28, |
| BIN_PRIM_NEAR_CULL = 29, |
| BIN_PRIM_ZERO_CULL = 30, |
| BIN_PRIM_FAR_CULL = 31, |
| BIN_PRIM_BIN_CULL = 32, |
| BIN_PRIM_FACE_CULL = 33, |
| SPARE34 = 34, |
| SPARE35 = 35, |
| SPARE36 = 36, |
| SPARE37 = 37, |
| SPARE38 = 38, |
| SPARE39 = 39, |
| TE_SU_IN_VALID = 40, |
| TE_SU_IN_READ = 41, |
| TE_SU_IN_PRIM = 42, |
| TE_SU_IN_EOP = 43, |
| TE_SU_IN_NULL_PRIM = 44, |
| TE_WK_IN_VALID = 45, |
| TE_WK_IN_READ = 46, |
| TE_OUT_PRIM_VALID = 47, |
| TE_OUT_PRIM_READ = 48, |
| }; |
| |
| enum a2xx_tcr_perfcount_select { |
| DGMMPD_IPMUX0_STALL = 0, |
| DGMMPD_IPMUX_ALL_STALL = 4, |
| OPMUX0_L2_WRITES = 5, |
| }; |
| |
| enum a2xx_tp_perfcount_select { |
| POINT_QUADS = 0, |
| BILIN_QUADS = 1, |
| ANISO_QUADS = 2, |
| MIP_QUADS = 3, |
| VOL_QUADS = 4, |
| MIP_VOL_QUADS = 5, |
| MIP_ANISO_QUADS = 6, |
| VOL_ANISO_QUADS = 7, |
| ANISO_2_1_QUADS = 8, |
| ANISO_4_1_QUADS = 9, |
| ANISO_6_1_QUADS = 10, |
| ANISO_8_1_QUADS = 11, |
| ANISO_10_1_QUADS = 12, |
| ANISO_12_1_QUADS = 13, |
| ANISO_14_1_QUADS = 14, |
| ANISO_16_1_QUADS = 15, |
| MIP_VOL_ANISO_QUADS = 16, |
| ALIGN_2_QUADS = 17, |
| ALIGN_4_QUADS = 18, |
| PIX_0_QUAD = 19, |
| PIX_1_QUAD = 20, |
| PIX_2_QUAD = 21, |
| PIX_3_QUAD = 22, |
| PIX_4_QUAD = 23, |
| TP_MIPMAP_LOD0 = 24, |
| TP_MIPMAP_LOD1 = 25, |
| TP_MIPMAP_LOD2 = 26, |
| TP_MIPMAP_LOD3 = 27, |
| TP_MIPMAP_LOD4 = 28, |
| TP_MIPMAP_LOD5 = 29, |
| TP_MIPMAP_LOD6 = 30, |
| TP_MIPMAP_LOD7 = 31, |
| TP_MIPMAP_LOD8 = 32, |
| TP_MIPMAP_LOD9 = 33, |
| TP_MIPMAP_LOD10 = 34, |
| TP_MIPMAP_LOD11 = 35, |
| TP_MIPMAP_LOD12 = 36, |
| TP_MIPMAP_LOD13 = 37, |
| TP_MIPMAP_LOD14 = 38, |
| }; |
| |
| enum a2xx_tcm_perfcount_select { |
| QUAD0_RD_LAT_FIFO_EMPTY = 0, |
| QUAD0_RD_LAT_FIFO_4TH_FULL = 3, |
| QUAD0_RD_LAT_FIFO_HALF_FULL = 4, |
| QUAD0_RD_LAT_FIFO_FULL = 5, |
| QUAD0_RD_LAT_FIFO_LT_4TH_FULL = 6, |
| READ_STARVED_QUAD0 = 28, |
| READ_STARVED = 32, |
| READ_STALLED_QUAD0 = 33, |
| READ_STALLED = 37, |
| VALID_READ_QUAD0 = 38, |
| TC_TP_STARVED_QUAD0 = 42, |
| TC_TP_STARVED = 46, |
| }; |
| |
| enum a2xx_tcf_perfcount_select { |
| VALID_CYCLES = 0, |
| SINGLE_PHASES = 1, |
| ANISO_PHASES = 2, |
| MIP_PHASES = 3, |
| VOL_PHASES = 4, |
| MIP_VOL_PHASES = 5, |
| MIP_ANISO_PHASES = 6, |
| VOL_ANISO_PHASES = 7, |
| ANISO_2_1_PHASES = 8, |
| ANISO_4_1_PHASES = 9, |
| ANISO_6_1_PHASES = 10, |
| ANISO_8_1_PHASES = 11, |
| ANISO_10_1_PHASES = 12, |
| ANISO_12_1_PHASES = 13, |
| ANISO_14_1_PHASES = 14, |
| ANISO_16_1_PHASES = 15, |
| MIP_VOL_ANISO_PHASES = 16, |
| ALIGN_2_PHASES = 17, |
| ALIGN_4_PHASES = 18, |
| TPC_BUSY = 19, |
| TPC_STALLED = 20, |
| TPC_STARVED = 21, |
| TPC_WORKING = 22, |
| TPC_WALKER_BUSY = 23, |
| TPC_WALKER_STALLED = 24, |
| TPC_WALKER_WORKING = 25, |
| TPC_ALIGNER_BUSY = 26, |
| TPC_ALIGNER_STALLED = 27, |
| TPC_ALIGNER_STALLED_BY_BLEND = 28, |
| TPC_ALIGNER_STALLED_BY_CACHE = 29, |
| TPC_ALIGNER_WORKING = 30, |
| TPC_BLEND_BUSY = 31, |
| TPC_BLEND_SYNC = 32, |
| TPC_BLEND_STARVED = 33, |
| TPC_BLEND_WORKING = 34, |
| OPCODE_0x00 = 35, |
| OPCODE_0x01 = 36, |
| OPCODE_0x04 = 37, |
| OPCODE_0x10 = 38, |
| OPCODE_0x11 = 39, |
| OPCODE_0x12 = 40, |
| OPCODE_0x13 = 41, |
| OPCODE_0x18 = 42, |
| OPCODE_0x19 = 43, |
| OPCODE_0x1A = 44, |
| OPCODE_OTHER = 45, |
| IN_FIFO_0_EMPTY = 56, |
| IN_FIFO_0_LT_HALF_FULL = 57, |
| IN_FIFO_0_HALF_FULL = 58, |
| IN_FIFO_0_FULL = 59, |
| IN_FIFO_TPC_EMPTY = 72, |
| IN_FIFO_TPC_LT_HALF_FULL = 73, |
| IN_FIFO_TPC_HALF_FULL = 74, |
| IN_FIFO_TPC_FULL = 75, |
| TPC_TC_XFC = 76, |
| TPC_TC_STATE = 77, |
| TC_STALL = 78, |
| QUAD0_TAPS = 79, |
| QUADS = 83, |
| TCA_SYNC_STALL = 84, |
| TAG_STALL = 85, |
| TCB_SYNC_STALL = 88, |
| TCA_VALID = 89, |
| PROBES_VALID = 90, |
| MISS_STALL = 91, |
| FETCH_FIFO_STALL = 92, |
| TCO_STALL = 93, |
| ANY_STALL = 94, |
| TAG_MISSES = 95, |
| TAG_HITS = 96, |
| SUB_TAG_MISSES = 97, |
| SET0_INVALIDATES = 98, |
| SET1_INVALIDATES = 99, |
| SET2_INVALIDATES = 100, |
| SET3_INVALIDATES = 101, |
| SET0_TAG_MISSES = 102, |
| SET1_TAG_MISSES = 103, |
| SET2_TAG_MISSES = 104, |
| SET3_TAG_MISSES = 105, |
| SET0_TAG_HITS = 106, |
| SET1_TAG_HITS = 107, |
| SET2_TAG_HITS = 108, |
| SET3_TAG_HITS = 109, |
| SET0_SUB_TAG_MISSES = 110, |
| SET1_SUB_TAG_MISSES = 111, |
| SET2_SUB_TAG_MISSES = 112, |
| SET3_SUB_TAG_MISSES = 113, |
| SET0_EVICT1 = 114, |
| SET0_EVICT2 = 115, |
| SET0_EVICT3 = 116, |
| SET0_EVICT4 = 117, |
| SET0_EVICT5 = 118, |
| SET0_EVICT6 = 119, |
| SET0_EVICT7 = 120, |
| SET0_EVICT8 = 121, |
| SET1_EVICT1 = 130, |
| SET1_EVICT2 = 131, |
| SET1_EVICT3 = 132, |
| SET1_EVICT4 = 133, |
| SET1_EVICT5 = 134, |
| SET1_EVICT6 = 135, |
| SET1_EVICT7 = 136, |
| SET1_EVICT8 = 137, |
| SET2_EVICT1 = 146, |
| SET2_EVICT2 = 147, |
| SET2_EVICT3 = 148, |
| SET2_EVICT4 = 149, |
| SET2_EVICT5 = 150, |
| SET2_EVICT6 = 151, |
| SET2_EVICT7 = 152, |
| SET2_EVICT8 = 153, |
| SET3_EVICT1 = 162, |
| SET3_EVICT2 = 163, |
| SET3_EVICT3 = 164, |
| SET3_EVICT4 = 165, |
| SET3_EVICT5 = 166, |
| SET3_EVICT6 = 167, |
| SET3_EVICT7 = 168, |
| SET3_EVICT8 = 169, |
| FF_EMPTY = 178, |
| FF_LT_HALF_FULL = 179, |
| FF_HALF_FULL = 180, |
| FF_FULL = 181, |
| FF_XFC = 182, |
| FF_STALLED = 183, |
| FG_MASKS = 184, |
| FG_LEFT_MASKS = 185, |
| FG_LEFT_MASK_STALLED = 186, |
| FG_LEFT_NOT_DONE_STALL = 187, |
| FG_LEFT_FG_STALL = 188, |
| FG_LEFT_SECTORS = 189, |
| FG0_REQUESTS = 195, |
| FG0_STALLED = 196, |
| MEM_REQ512 = 199, |
| MEM_REQ_SENT = 200, |
| MEM_LOCAL_READ_REQ = 202, |
| TC0_MH_STALLED = 203, |
| }; |
| |
| enum a2xx_sq_perfcnt_select { |
| SQ_PIXEL_VECTORS_SUB = 0, |
| SQ_VERTEX_VECTORS_SUB = 1, |
| SQ_ALU0_ACTIVE_VTX_SIMD0 = 2, |
| SQ_ALU1_ACTIVE_VTX_SIMD0 = 3, |
| SQ_ALU0_ACTIVE_PIX_SIMD0 = 4, |
| SQ_ALU1_ACTIVE_PIX_SIMD0 = 5, |
| SQ_ALU0_ACTIVE_VTX_SIMD1 = 6, |
| SQ_ALU1_ACTIVE_VTX_SIMD1 = 7, |
| SQ_ALU0_ACTIVE_PIX_SIMD1 = 8, |
| SQ_ALU1_ACTIVE_PIX_SIMD1 = 9, |
| SQ_EXPORT_CYCLES = 10, |
| SQ_ALU_CST_WRITTEN = 11, |
| SQ_TEX_CST_WRITTEN = 12, |
| SQ_ALU_CST_STALL = 13, |
| SQ_ALU_TEX_STALL = 14, |
| SQ_INST_WRITTEN = 15, |
| SQ_BOOLEAN_WRITTEN = 16, |
| SQ_LOOPS_WRITTEN = 17, |
| SQ_PIXEL_SWAP_IN = 18, |
| SQ_PIXEL_SWAP_OUT = 19, |
| SQ_VERTEX_SWAP_IN = 20, |
| SQ_VERTEX_SWAP_OUT = 21, |
| SQ_ALU_VTX_INST_ISSUED = 22, |
| SQ_TEX_VTX_INST_ISSUED = 23, |
| SQ_VC_VTX_INST_ISSUED = 24, |
| SQ_CF_VTX_INST_ISSUED = 25, |
| SQ_ALU_PIX_INST_ISSUED = 26, |
| SQ_TEX_PIX_INST_ISSUED = 27, |
| SQ_VC_PIX_INST_ISSUED = 28, |
| SQ_CF_PIX_INST_ISSUED = 29, |
| SQ_ALU0_FIFO_EMPTY_SIMD0 = 30, |
| SQ_ALU1_FIFO_EMPTY_SIMD0 = 31, |
| SQ_ALU0_FIFO_EMPTY_SIMD1 = 32, |
| SQ_ALU1_FIFO_EMPTY_SIMD1 = 33, |
| SQ_ALU_NOPS = 34, |
| SQ_PRED_SKIP = 35, |
| SQ_SYNC_ALU_STALL_SIMD0_VTX = 36, |
| SQ_SYNC_ALU_STALL_SIMD1_VTX = 37, |
| SQ_SYNC_TEX_STALL_VTX = 38, |
| SQ_SYNC_VC_STALL_VTX = 39, |
| SQ_CONSTANTS_USED_SIMD0 = 40, |
| SQ_CONSTANTS_SENT_SP_SIMD0 = 41, |
| SQ_GPR_STALL_VTX = 42, |
| SQ_GPR_STALL_PIX = 43, |
| SQ_VTX_RS_STALL = 44, |
| SQ_PIX_RS_STALL = 45, |
| SQ_SX_PC_FULL = 46, |
| SQ_SX_EXP_BUFF_FULL = 47, |
| SQ_SX_POS_BUFF_FULL = 48, |
| SQ_INTERP_QUADS = 49, |
| SQ_INTERP_ACTIVE = 50, |
| SQ_IN_PIXEL_STALL = 51, |
| SQ_IN_VTX_STALL = 52, |
| SQ_VTX_CNT = 53, |
| SQ_VTX_VECTOR2 = 54, |
| SQ_VTX_VECTOR3 = 55, |
| SQ_VTX_VECTOR4 = 56, |
| SQ_PIXEL_VECTOR1 = 57, |
| SQ_PIXEL_VECTOR23 = 58, |
| SQ_PIXEL_VECTOR4 = 59, |
| SQ_CONSTANTS_USED_SIMD1 = 60, |
| SQ_CONSTANTS_SENT_SP_SIMD1 = 61, |
| SQ_SX_MEM_EXP_FULL = 62, |
| SQ_ALU0_ACTIVE_VTX_SIMD2 = 63, |
| SQ_ALU1_ACTIVE_VTX_SIMD2 = 64, |
| SQ_ALU0_ACTIVE_PIX_SIMD2 = 65, |
| SQ_ALU1_ACTIVE_PIX_SIMD2 = 66, |
| SQ_ALU0_ACTIVE_VTX_SIMD3 = 67, |
| SQ_PERFCOUNT_VTX_QUAL_TP_DONE = 68, |
| SQ_ALU0_ACTIVE_PIX_SIMD3 = 69, |
| SQ_PERFCOUNT_PIX_QUAL_TP_DONE = 70, |
| SQ_ALU0_FIFO_EMPTY_SIMD2 = 71, |
| SQ_ALU1_FIFO_EMPTY_SIMD2 = 72, |
| SQ_ALU0_FIFO_EMPTY_SIMD3 = 73, |
| SQ_ALU1_FIFO_EMPTY_SIMD3 = 74, |
| SQ_SYNC_ALU_STALL_SIMD2_VTX = 75, |
| SQ_PERFCOUNT_VTX_POP_THREAD = 76, |
| SQ_SYNC_ALU_STALL_SIMD0_PIX = 77, |
| SQ_SYNC_ALU_STALL_SIMD1_PIX = 78, |
| SQ_SYNC_ALU_STALL_SIMD2_PIX = 79, |
| SQ_PERFCOUNT_PIX_POP_THREAD = 80, |
| SQ_SYNC_TEX_STALL_PIX = 81, |
| SQ_SYNC_VC_STALL_PIX = 82, |
| SQ_CONSTANTS_USED_SIMD2 = 83, |
| SQ_CONSTANTS_SENT_SP_SIMD2 = 84, |
| SQ_PERFCOUNT_VTX_DEALLOC_ACK = 85, |
| SQ_PERFCOUNT_PIX_DEALLOC_ACK = 86, |
| SQ_ALU0_FIFO_FULL_SIMD0 = 87, |
| SQ_ALU1_FIFO_FULL_SIMD0 = 88, |
| SQ_ALU0_FIFO_FULL_SIMD1 = 89, |
| SQ_ALU1_FIFO_FULL_SIMD1 = 90, |
| SQ_ALU0_FIFO_FULL_SIMD2 = 91, |
| SQ_ALU1_FIFO_FULL_SIMD2 = 92, |
| SQ_ALU0_FIFO_FULL_SIMD3 = 93, |
| SQ_ALU1_FIFO_FULL_SIMD3 = 94, |
| VC_PERF_STATIC = 95, |
| VC_PERF_STALLED = 96, |
| VC_PERF_STARVED = 97, |
| VC_PERF_SEND = 98, |
| VC_PERF_ACTUAL_STARVED = 99, |
| PIXEL_THREAD_0_ACTIVE = 100, |
| VERTEX_THREAD_0_ACTIVE = 101, |
| PIXEL_THREAD_0_NUMBER = 102, |
| VERTEX_THREAD_0_NUMBER = 103, |
| VERTEX_EVENT_NUMBER = 104, |
| PIXEL_EVENT_NUMBER = 105, |
| PTRBUFF_EF_PUSH = 106, |
| PTRBUFF_EF_POP_EVENT = 107, |
| PTRBUFF_EF_POP_NEW_VTX = 108, |
| PTRBUFF_EF_POP_DEALLOC = 109, |
| PTRBUFF_EF_POP_PVECTOR = 110, |
| PTRBUFF_EF_POP_PVECTOR_X = 111, |
| PTRBUFF_EF_POP_PVECTOR_VNZ = 112, |
| PTRBUFF_PB_DEALLOC = 113, |
| PTRBUFF_PI_STATE_PPB_POP = 114, |
| PTRBUFF_PI_RTR = 115, |
| PTRBUFF_PI_READ_EN = 116, |
| PTRBUFF_PI_BUFF_SWAP = 117, |
| PTRBUFF_SQ_FREE_BUFF = 118, |
| PTRBUFF_SQ_DEC = 119, |
| PTRBUFF_SC_VALID_CNTL_EVENT = 120, |
| PTRBUFF_SC_VALID_IJ_XFER = 121, |
| PTRBUFF_SC_NEW_VECTOR_1_Q = 122, |
| PTRBUFF_QUAL_NEW_VECTOR = 123, |
| PTRBUFF_QUAL_EVENT = 124, |
| PTRBUFF_END_BUFFER = 125, |
| PTRBUFF_FILL_QUAD = 126, |
| VERTS_WRITTEN_SPI = 127, |
| TP_FETCH_INSTR_EXEC = 128, |
| TP_FETCH_INSTR_REQ = 129, |
| TP_DATA_RETURN = 130, |
| SPI_WRITE_CYCLES_SP = 131, |
| SPI_WRITES_SP = 132, |
| SP_ALU_INSTR_EXEC = 133, |
| SP_CONST_ADDR_TO_SQ = 134, |
| SP_PRED_KILLS_TO_SQ = 135, |
| SP_EXPORT_CYCLES_TO_SX = 136, |
| SP_EXPORTS_TO_SX = 137, |
| SQ_CYCLES_ELAPSED = 138, |
| SQ_TCFS_OPT_ALLOC_EXEC = 139, |
| SQ_TCFS_NO_OPT_ALLOC = 140, |
| SQ_ALU0_NO_OPT_ALLOC = 141, |
| SQ_ALU1_NO_OPT_ALLOC = 142, |
| SQ_TCFS_ARB_XFC_CNT = 143, |
| SQ_ALU0_ARB_XFC_CNT = 144, |
| SQ_ALU1_ARB_XFC_CNT = 145, |
| SQ_TCFS_CFS_UPDATE_CNT = 146, |
| SQ_ALU0_CFS_UPDATE_CNT = 147, |
| SQ_ALU1_CFS_UPDATE_CNT = 148, |
| SQ_VTX_PUSH_THREAD_CNT = 149, |
| SQ_VTX_POP_THREAD_CNT = 150, |
| SQ_PIX_PUSH_THREAD_CNT = 151, |
| SQ_PIX_POP_THREAD_CNT = 152, |
| SQ_PIX_TOTAL = 153, |
| SQ_PIX_KILLED = 154, |
| }; |
| |
| enum a2xx_sx_perfcnt_select { |
| SX_EXPORT_VECTORS = 0, |
| SX_DUMMY_QUADS = 1, |
| SX_ALPHA_FAIL = 2, |
| SX_RB_QUAD_BUSY = 3, |
| SX_RB_COLOR_BUSY = 4, |
| SX_RB_QUAD_STALL = 5, |
| SX_RB_COLOR_STALL = 6, |
| }; |
| |
| enum a2xx_rbbm_perfcount1_sel { |
| RBBM1_COUNT = 0, |
| RBBM1_NRT_BUSY = 1, |
| RBBM1_RB_BUSY = 2, |
| RBBM1_SQ_CNTX0_BUSY = 3, |
| RBBM1_SQ_CNTX17_BUSY = 4, |
| RBBM1_VGT_BUSY = 5, |
| RBBM1_VGT_NODMA_BUSY = 6, |
| RBBM1_PA_BUSY = 7, |
| RBBM1_SC_CNTX_BUSY = 8, |
| RBBM1_TPC_BUSY = 9, |
| RBBM1_TC_BUSY = 10, |
| RBBM1_SX_BUSY = 11, |
| RBBM1_CP_COHER_BUSY = 12, |
| RBBM1_CP_NRT_BUSY = 13, |
| RBBM1_GFX_IDLE_STALL = 14, |
| RBBM1_INTERRUPT = 15, |
| }; |
| |
| enum a2xx_cp_perfcount_sel { |
| ALWAYS_COUNT = 0, |
| TRANS_FIFO_FULL = 1, |
| TRANS_FIFO_AF = 2, |
| RCIU_PFPTRANS_WAIT = 3, |
| RCIU_NRTTRANS_WAIT = 6, |
| CSF_NRT_READ_WAIT = 8, |
| CSF_I1_FIFO_FULL = 9, |
| CSF_I2_FIFO_FULL = 10, |
| CSF_ST_FIFO_FULL = 11, |
| CSF_RING_ROQ_FULL = 13, |
| CSF_I1_ROQ_FULL = 14, |
| CSF_I2_ROQ_FULL = 15, |
| CSF_ST_ROQ_FULL = 16, |
| MIU_TAG_MEM_FULL = 18, |
| MIU_WRITECLEAN = 19, |
| MIU_NRT_WRITE_STALLED = 22, |
| MIU_NRT_READ_STALLED = 23, |
| ME_WRITE_CONFIRM_FIFO_FULL = 24, |
| ME_VS_DEALLOC_FIFO_FULL = 25, |
| ME_PS_DEALLOC_FIFO_FULL = 26, |
| ME_REGS_VS_EVENT_FIFO_FULL = 27, |
| ME_REGS_PS_EVENT_FIFO_FULL = 28, |
| ME_REGS_CF_EVENT_FIFO_FULL = 29, |
| ME_MICRO_RB_STARVED = 30, |
| ME_MICRO_I1_STARVED = 31, |
| ME_MICRO_I2_STARVED = 32, |
| ME_MICRO_ST_STARVED = 33, |
| RCIU_RBBM_DWORD_SENT = 40, |
| ME_BUSY_CLOCKS = 41, |
| ME_WAIT_CONTEXT_AVAIL = 42, |
| PFP_TYPE0_PACKET = 43, |
| PFP_TYPE3_PACKET = 44, |
| CSF_RB_WPTR_NEQ_RPTR = 45, |
| CSF_I1_SIZE_NEQ_ZERO = 46, |
| CSF_I2_SIZE_NEQ_ZERO = 47, |
| CSF_RBI1I2_FETCHING = 48, |
| }; |
| |
| enum a2xx_rb_perfcnt_select { |
| RBPERF_CNTX_BUSY = 0, |
| RBPERF_CNTX_BUSY_MAX = 1, |
| RBPERF_SX_QUAD_STARVED = 2, |
| RBPERF_SX_QUAD_STARVED_MAX = 3, |
| RBPERF_GA_GC_CH0_SYS_REQ = 4, |
| RBPERF_GA_GC_CH0_SYS_REQ_MAX = 5, |
| RBPERF_GA_GC_CH1_SYS_REQ = 6, |
| RBPERF_GA_GC_CH1_SYS_REQ_MAX = 7, |
| RBPERF_MH_STARVED = 8, |
| RBPERF_MH_STARVED_MAX = 9, |
| RBPERF_AZ_BC_COLOR_BUSY = 10, |
| RBPERF_AZ_BC_COLOR_BUSY_MAX = 11, |
| RBPERF_AZ_BC_Z_BUSY = 12, |
| RBPERF_AZ_BC_Z_BUSY_MAX = 13, |
| RBPERF_RB_SC_TILE_RTR_N = 14, |
| RBPERF_RB_SC_TILE_RTR_N_MAX = 15, |
| RBPERF_RB_SC_SAMP_RTR_N = 16, |
| RBPERF_RB_SC_SAMP_RTR_N_MAX = 17, |
| RBPERF_RB_SX_QUAD_RTR_N = 18, |
| RBPERF_RB_SX_QUAD_RTR_N_MAX = 19, |
| RBPERF_RB_SX_COLOR_RTR_N = 20, |
| RBPERF_RB_SX_COLOR_RTR_N_MAX = 21, |
| RBPERF_RB_SC_SAMP_LZ_BUSY = 22, |
| RBPERF_RB_SC_SAMP_LZ_BUSY_MAX = 23, |
| RBPERF_ZXP_STALL = 24, |
| RBPERF_ZXP_STALL_MAX = 25, |
| RBPERF_EVENT_PENDING = 26, |
| RBPERF_EVENT_PENDING_MAX = 27, |
| RBPERF_RB_MH_VALID = 28, |
| RBPERF_RB_MH_VALID_MAX = 29, |
| RBPERF_SX_RB_QUAD_SEND = 30, |
| RBPERF_SX_RB_COLOR_SEND = 31, |
| RBPERF_SC_RB_TILE_SEND = 32, |
| RBPERF_SC_RB_SAMPLE_SEND = 33, |
| RBPERF_SX_RB_MEM_EXPORT = 34, |
| RBPERF_SX_RB_QUAD_EVENT = 35, |
| RBPERF_SC_RB_TILE_EVENT_FILTERED = 36, |
| RBPERF_SC_RB_TILE_EVENT_ALL = 37, |
| RBPERF_RB_SC_EZ_SEND = 38, |
| RBPERF_RB_SX_INDEX_SEND = 39, |
| RBPERF_GMEM_INTFO_RD = 40, |
| RBPERF_GMEM_INTF1_RD = 41, |
| RBPERF_GMEM_INTFO_WR = 42, |
| RBPERF_GMEM_INTF1_WR = 43, |
| RBPERF_RB_CP_CONTEXT_DONE = 44, |
| RBPERF_RB_CP_CACHE_FLUSH = 45, |
| RBPERF_ZPASS_DONE = 46, |
| RBPERF_ZCMD_VALID = 47, |
| RBPERF_CCMD_VALID = 48, |
| RBPERF_ACCUM_GRANT = 49, |
| RBPERF_ACCUM_C0_GRANT = 50, |
| RBPERF_ACCUM_C1_GRANT = 51, |
| RBPERF_ACCUM_FULL_BE_WR = 52, |
| RBPERF_ACCUM_REQUEST_NO_GRANT = 53, |
| RBPERF_ACCUM_TIMEOUT_PULSE = 54, |
| RBPERF_ACCUM_LIN_TIMEOUT_PULSE = 55, |
| RBPERF_ACCUM_CAM_HIT_FLUSHING = 56, |
| }; |
| |
| enum a2xx_mh_perfcnt_select { |
| CP_R0_REQUESTS = 0, |
| CP_R1_REQUESTS = 1, |
| CP_R2_REQUESTS = 2, |
| CP_R3_REQUESTS = 3, |
| CP_R4_REQUESTS = 4, |
| CP_TOTAL_READ_REQUESTS = 5, |
| CP_TOTAL_WRITE_REQUESTS = 6, |
| CP_TOTAL_REQUESTS = 7, |
| CP_DATA_BYTES_WRITTEN = 8, |
| CP_WRITE_CLEAN_RESPONSES = 9, |
| CP_R0_READ_BURSTS_RECEIVED = 10, |
| CP_R1_READ_BURSTS_RECEIVED = 11, |
| CP_R2_READ_BURSTS_RECEIVED = 12, |
| CP_R3_READ_BURSTS_RECEIVED = 13, |
| CP_R4_READ_BURSTS_RECEIVED = 14, |
| CP_TOTAL_READ_BURSTS_RECEIVED = 15, |
| CP_R0_DATA_BEATS_READ = 16, |
| CP_R1_DATA_BEATS_READ = 17, |
| CP_R2_DATA_BEATS_READ = 18, |
| CP_R3_DATA_BEATS_READ = 19, |
| CP_R4_DATA_BEATS_READ = 20, |
| CP_TOTAL_DATA_BEATS_READ = 21, |
| VGT_R0_REQUESTS = 22, |
| VGT_R1_REQUESTS = 23, |
| VGT_TOTAL_REQUESTS = 24, |
| VGT_R0_READ_BURSTS_RECEIVED = 25, |
| VGT_R1_READ_BURSTS_RECEIVED = 26, |
| VGT_TOTAL_READ_BURSTS_RECEIVED = 27, |
| VGT_R0_DATA_BEATS_READ = 28, |
| VGT_R1_DATA_BEATS_READ = 29, |
| VGT_TOTAL_DATA_BEATS_READ = 30, |
| TC_TOTAL_REQUESTS = 31, |
| TC_ROQ_REQUESTS = 32, |
| TC_INFO_SENT = 33, |
| TC_READ_BURSTS_RECEIVED = 34, |
| TC_DATA_BEATS_READ = 35, |
| TCD_BURSTS_READ = 36, |
| RB_REQUESTS = 37, |
| RB_DATA_BYTES_WRITTEN = 38, |
| RB_WRITE_CLEAN_RESPONSES = 39, |
| AXI_READ_REQUESTS_ID_0 = 40, |
| AXI_READ_REQUESTS_ID_1 = 41, |
| AXI_READ_REQUESTS_ID_2 = 42, |
| AXI_READ_REQUESTS_ID_3 = 43, |
| AXI_READ_REQUESTS_ID_4 = 44, |
| AXI_READ_REQUESTS_ID_5 = 45, |
| AXI_READ_REQUESTS_ID_6 = 46, |
| AXI_READ_REQUESTS_ID_7 = 47, |
| AXI_TOTAL_READ_REQUESTS = 48, |
| AXI_WRITE_REQUESTS_ID_0 = 49, |
| AXI_WRITE_REQUESTS_ID_1 = 50, |
| AXI_WRITE_REQUESTS_ID_2 = 51, |
| AXI_WRITE_REQUESTS_ID_3 = 52, |
| AXI_WRITE_REQUESTS_ID_4 = 53, |
| AXI_WRITE_REQUESTS_ID_5 = 54, |
| AXI_WRITE_REQUESTS_ID_6 = 55, |
| AXI_WRITE_REQUESTS_ID_7 = 56, |
| AXI_TOTAL_WRITE_REQUESTS = 57, |
| AXI_TOTAL_REQUESTS_ID_0 = 58, |
| AXI_TOTAL_REQUESTS_ID_1 = 59, |
| AXI_TOTAL_REQUESTS_ID_2 = 60, |
| AXI_TOTAL_REQUESTS_ID_3 = 61, |
| AXI_TOTAL_REQUESTS_ID_4 = 62, |
| AXI_TOTAL_REQUESTS_ID_5 = 63, |
| AXI_TOTAL_REQUESTS_ID_6 = 64, |
| AXI_TOTAL_REQUESTS_ID_7 = 65, |
| AXI_TOTAL_REQUESTS = 66, |
| AXI_READ_CHANNEL_BURSTS_ID_0 = 67, |
| AXI_READ_CHANNEL_BURSTS_ID_1 = 68, |
| AXI_READ_CHANNEL_BURSTS_ID_2 = 69, |
| AXI_READ_CHANNEL_BURSTS_ID_3 = 70, |
| AXI_READ_CHANNEL_BURSTS_ID_4 = 71, |
| AXI_READ_CHANNEL_BURSTS_ID_5 = 72, |
| AXI_READ_CHANNEL_BURSTS_ID_6 = 73, |
| AXI_READ_CHANNEL_BURSTS_ID_7 = 74, |
| AXI_READ_CHANNEL_TOTAL_BURSTS = 75, |
| AXI_READ_CHANNEL_DATA_BEATS_READ_ID_0 = 76, |
| AXI_READ_CHANNEL_DATA_BEATS_READ_ID_1 = 77, |
| AXI_READ_CHANNEL_DATA_BEATS_READ_ID_2 = 78, |
| AXI_READ_CHANNEL_DATA_BEATS_READ_ID_3 = 79, |
| AXI_READ_CHANNEL_DATA_BEATS_READ_ID_4 = 80, |
| AXI_READ_CHANNEL_DATA_BEATS_READ_ID_5 = 81, |
| AXI_READ_CHANNEL_DATA_BEATS_READ_ID_6 = 82, |
| AXI_READ_CHANNEL_DATA_BEATS_READ_ID_7 = 83, |
| AXI_READ_CHANNEL_TOTAL_DATA_BEATS_READ = 84, |
| AXI_WRITE_CHANNEL_BURSTS_ID_0 = 85, |
| AXI_WRITE_CHANNEL_BURSTS_ID_1 = 86, |
| AXI_WRITE_CHANNEL_BURSTS_ID_2 = 87, |
| AXI_WRITE_CHANNEL_BURSTS_ID_3 = 88, |
| AXI_WRITE_CHANNEL_BURSTS_ID_4 = 89, |
| AXI_WRITE_CHANNEL_BURSTS_ID_5 = 90, |
| AXI_WRITE_CHANNEL_BURSTS_ID_6 = 91, |
| AXI_WRITE_CHANNEL_BURSTS_ID_7 = 92, |
| AXI_WRITE_CHANNEL_TOTAL_BURSTS = 93, |
| AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_0 = 94, |
| AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_1 = 95, |
| AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_2 = 96, |
| AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_3 = 97, |
| AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_4 = 98, |
| AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_5 = 99, |
| AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_6 = 100, |
| AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_7 = 101, |
| AXI_WRITE_CHANNEL_TOTAL_DATA_BYTES_WRITTEN = 102, |
| AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_0 = 103, |
| AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_1 = 104, |
| AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_2 = 105, |
| AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_3 = 106, |
| AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_4 = 107, |
| AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_5 = 108, |
| AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_6 = 109, |
| AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_7 = 110, |
| AXI_WRITE_RESPONSE_CHANNEL_TOTAL_RESPONSES = 111, |
| TOTAL_MMU_MISSES = 112, |
| MMU_READ_MISSES = 113, |
| MMU_WRITE_MISSES = 114, |
| TOTAL_MMU_HITS = 115, |
| MMU_READ_HITS = 116, |
| MMU_WRITE_HITS = 117, |
| SPLIT_MODE_TC_HITS = 118, |
| SPLIT_MODE_TC_MISSES = 119, |
| SPLIT_MODE_NON_TC_HITS = 120, |
| SPLIT_MODE_NON_TC_MISSES = 121, |
| STALL_AWAITING_TLB_MISS_FETCH = 122, |
| MMU_TLB_MISS_READ_BURSTS_RECEIVED = 123, |
| MMU_TLB_MISS_DATA_BEATS_READ = 124, |
| CP_CYCLES_HELD_OFF = 125, |
| VGT_CYCLES_HELD_OFF = 126, |
| TC_CYCLES_HELD_OFF = 127, |
| TC_ROQ_CYCLES_HELD_OFF = 128, |
| TC_CYCLES_HELD_OFF_TCD_FULL = 129, |
| RB_CYCLES_HELD_OFF = 130, |
| TOTAL_CYCLES_ANY_CLNT_HELD_OFF = 131, |
| TLB_MISS_CYCLES_HELD_OFF = 132, |
| AXI_READ_REQUEST_HELD_OFF = 133, |
| AXI_WRITE_REQUEST_HELD_OFF = 134, |
| AXI_REQUEST_HELD_OFF = 135, |
| AXI_REQUEST_HELD_OFF_INFLIGHT_LIMIT = 136, |
| AXI_WRITE_DATA_HELD_OFF = 137, |
| CP_SAME_PAGE_BANK_REQUESTS = 138, |
| VGT_SAME_PAGE_BANK_REQUESTS = 139, |
| TC_SAME_PAGE_BANK_REQUESTS = 140, |
| TC_ARB_HOLD_SAME_PAGE_BANK_REQUESTS = 141, |
| RB_SAME_PAGE_BANK_REQUESTS = 142, |
| TOTAL_SAME_PAGE_BANK_REQUESTS = 143, |
| CP_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT = 144, |
| VGT_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT = 145, |
| TC_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT = 146, |
| RB_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT = 147, |
| TOTAL_SAME_PAGE_BANK_KILLED_FAIRNESS_LIMIT = 148, |
| TOTAL_MH_READ_REQUESTS = 149, |
| TOTAL_MH_WRITE_REQUESTS = 150, |
| TOTAL_MH_REQUESTS = 151, |
| MH_BUSY = 152, |
| CP_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE = 153, |
| VGT_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE = 154, |
| TC_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE = 155, |
| RB_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE = 156, |
| TC_ROQ_N_VALID_ENTRIES = 157, |
| ARQ_N_ENTRIES = 158, |
| WDB_N_ENTRIES = 159, |
| MH_READ_LATENCY_OUTST_REQ_SUM = 160, |
| MC_READ_LATENCY_OUTST_REQ_SUM = 161, |
| MC_TOTAL_READ_REQUESTS = 162, |
| ELAPSED_CYCLES_MH_GATED_CLK = 163, |
| ELAPSED_CLK_CYCLES = 164, |
| CP_W_16B_REQUESTS = 165, |
| CP_W_32B_REQUESTS = 166, |
| TC_16B_REQUESTS = 167, |
| TC_32B_REQUESTS = 168, |
| PA_REQUESTS = 169, |
| PA_DATA_BYTES_WRITTEN = 170, |
| PA_WRITE_CLEAN_RESPONSES = 171, |
| PA_CYCLES_HELD_OFF = 172, |
| AXI_READ_REQUEST_DATA_BEATS_ID_0 = 173, |
| AXI_READ_REQUEST_DATA_BEATS_ID_1 = 174, |
| AXI_READ_REQUEST_DATA_BEATS_ID_2 = 175, |
| AXI_READ_REQUEST_DATA_BEATS_ID_3 = 176, |
| AXI_READ_REQUEST_DATA_BEATS_ID_4 = 177, |
| AXI_READ_REQUEST_DATA_BEATS_ID_5 = 178, |
| AXI_READ_REQUEST_DATA_BEATS_ID_6 = 179, |
| AXI_READ_REQUEST_DATA_BEATS_ID_7 = 180, |
| AXI_TOTAL_READ_REQUEST_DATA_BEATS = 181, |
| }; |
| |
| enum adreno_mmu_clnt_beh { |
| BEH_NEVR = 0, |
| BEH_TRAN_RNG = 1, |
| BEH_TRAN_FLT = 2, |
| }; |
| |
| enum sq_tex_clamp { |
| SQ_TEX_WRAP = 0, |
| SQ_TEX_MIRROR = 1, |
| SQ_TEX_CLAMP_LAST_TEXEL = 2, |
| SQ_TEX_MIRROR_ONCE_LAST_TEXEL = 3, |
| SQ_TEX_CLAMP_HALF_BORDER = 4, |
| SQ_TEX_MIRROR_ONCE_HALF_BORDER = 5, |
| SQ_TEX_CLAMP_BORDER = 6, |
| SQ_TEX_MIRROR_ONCE_BORDER = 7, |
| }; |
| |
| enum sq_tex_swiz { |
| SQ_TEX_X = 0, |
| SQ_TEX_Y = 1, |
| SQ_TEX_Z = 2, |
| SQ_TEX_W = 3, |
| SQ_TEX_ZERO = 4, |
| SQ_TEX_ONE = 5, |
| }; |
| |
| enum sq_tex_filter { |
| SQ_TEX_FILTER_POINT = 0, |
| SQ_TEX_FILTER_BILINEAR = 1, |
| SQ_TEX_FILTER_BASEMAP = 2, |
| SQ_TEX_FILTER_USE_FETCH_CONST = 3, |
| }; |
| |
| enum sq_tex_aniso_filter { |
| SQ_TEX_ANISO_FILTER_DISABLED = 0, |
| SQ_TEX_ANISO_FILTER_MAX_1_1 = 1, |
| SQ_TEX_ANISO_FILTER_MAX_2_1 = 2, |
| SQ_TEX_ANISO_FILTER_MAX_4_1 = 3, |
| SQ_TEX_ANISO_FILTER_MAX_8_1 = 4, |
| SQ_TEX_ANISO_FILTER_MAX_16_1 = 5, |
| SQ_TEX_ANISO_FILTER_USE_FETCH_CONST = 7, |
| }; |
| |
| enum sq_tex_dimension { |
| SQ_TEX_DIMENSION_1D = 0, |
| SQ_TEX_DIMENSION_2D = 1, |
| SQ_TEX_DIMENSION_3D = 2, |
| SQ_TEX_DIMENSION_CUBE = 3, |
| }; |
| |
| enum sq_tex_border_color { |
| SQ_TEX_BORDER_COLOR_BLACK = 0, |
| SQ_TEX_BORDER_COLOR_WHITE = 1, |
| SQ_TEX_BORDER_COLOR_ACBYCR_BLACK = 2, |
| SQ_TEX_BORDER_COLOR_ACBCRY_BLACK = 3, |
| }; |
| |
| enum sq_tex_sign { |
| SQ_TEX_SIGN_UNSIGNED = 0, |
| SQ_TEX_SIGN_SIGNED = 1, |
| SQ_TEX_SIGN_UNSIGNED_BIASED = 2, |
| SQ_TEX_SIGN_GAMMA = 3, |
| }; |
| |
| enum sq_tex_endian { |
| SQ_TEX_ENDIAN_NONE = 0, |
| SQ_TEX_ENDIAN_8IN16 = 1, |
| SQ_TEX_ENDIAN_8IN32 = 2, |
| SQ_TEX_ENDIAN_16IN32 = 3, |
| }; |
| |
| enum sq_tex_clamp_policy { |
| SQ_TEX_CLAMP_POLICY_D3D = 0, |
| SQ_TEX_CLAMP_POLICY_OGL = 1, |
| }; |
| |
| enum sq_tex_num_format { |
| SQ_TEX_NUM_FORMAT_FRAC = 0, |
| SQ_TEX_NUM_FORMAT_INT = 1, |
| }; |
| |
| enum sq_tex_type { |
| SQ_TEX_TYPE_0 = 0, |
| SQ_TEX_TYPE_1 = 1, |
| SQ_TEX_TYPE_2 = 2, |
| SQ_TEX_TYPE_3 = 3, |
| }; |
| |
| #define REG_A2XX_RBBM_PATCH_RELEASE 0x00000001 |
| |
| #define REG_A2XX_RBBM_CNTL 0x0000003b |
| |
| #define REG_A2XX_RBBM_SOFT_RESET 0x0000003c |
| |
| #define REG_A2XX_CP_PFP_UCODE_ADDR 0x000000c0 |
| |
| #define REG_A2XX_CP_PFP_UCODE_DATA 0x000000c1 |
| |
| #define REG_A2XX_MH_MMU_CONFIG 0x00000040 |
| #define A2XX_MH_MMU_CONFIG_MMU_ENABLE 0x00000001 |
| #define A2XX_MH_MMU_CONFIG_SPLIT_MODE_ENABLE 0x00000002 |
| #define A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__MASK 0x00000030 |
| #define A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__SHIFT 4 |
| static inline uint32_t A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) |
| { |
| return ((val) << A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__MASK; |
| } |
| #define A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__MASK 0x000000c0 |
| #define A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__SHIFT 6 |
| static inline uint32_t A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) |
| { |
| return ((val) << A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__MASK; |
| } |
| #define A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__MASK 0x00000300 |
| #define A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__SHIFT 8 |
| static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) |
| { |
| return ((val) << A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__MASK; |
| } |
| #define A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__MASK 0x00000c00 |
| #define A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__SHIFT 10 |
| static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) |
| { |
| return ((val) << A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__MASK; |
| } |
| #define A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__MASK 0x00003000 |
| #define A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__SHIFT 12 |
| static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) |
| { |
| return ((val) << A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__MASK; |
| } |
| #define A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__MASK 0x0000c000 |
| #define A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__SHIFT 14 |
| static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) |
| { |
| return ((val) << A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__MASK; |
| } |
| #define A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__MASK 0x00030000 |
| #define A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__SHIFT 16 |
| static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) |
| { |
| return ((val) << A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__MASK; |
| } |
| #define A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__MASK 0x000c0000 |
| #define A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__SHIFT 18 |
| static inline uint32_t A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) |
| { |
| return ((val) << A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__MASK; |
| } |
| #define A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__MASK 0x00300000 |
| #define A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__SHIFT 20 |
| static inline uint32_t A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) |
| { |
| return ((val) << A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__MASK; |
| } |
| #define A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__MASK 0x00c00000 |
| #define A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__SHIFT 22 |
| static inline uint32_t A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) |
| { |
| return ((val) << A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__MASK; |
| } |
| #define A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__MASK 0x03000000 |
| #define A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__SHIFT 24 |
| static inline uint32_t A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) |
| { |
| return ((val) << A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__MASK; |
| } |
| |
| #define REG_A2XX_MH_MMU_VA_RANGE 0x00000041 |
| #define A2XX_MH_MMU_VA_RANGE_NUM_64KB_REGIONS__MASK 0x00000fff |
| #define A2XX_MH_MMU_VA_RANGE_NUM_64KB_REGIONS__SHIFT 0 |
| static inline uint32_t A2XX_MH_MMU_VA_RANGE_NUM_64KB_REGIONS(uint32_t val) |
| { |
| return ((val) << A2XX_MH_MMU_VA_RANGE_NUM_64KB_REGIONS__SHIFT) & A2XX_MH_MMU_VA_RANGE_NUM_64KB_REGIONS__MASK; |
| } |
| #define A2XX_MH_MMU_VA_RANGE_VA_BASE__MASK 0xfffff000 |
| #define A2XX_MH_MMU_VA_RANGE_VA_BASE__SHIFT 12 |
| static inline uint32_t A2XX_MH_MMU_VA_RANGE_VA_BASE(uint32_t val) |
| { |
| return ((val) << A2XX_MH_MMU_VA_RANGE_VA_BASE__SHIFT) & A2XX_MH_MMU_VA_RANGE_VA_BASE__MASK; |
| } |
| |
| #define REG_A2XX_MH_MMU_PT_BASE 0x00000042 |
| |
| #define REG_A2XX_MH_MMU_PAGE_FAULT 0x00000043 |
| |
| #define REG_A2XX_MH_MMU_TRAN_ERROR 0x00000044 |
| |
| #define REG_A2XX_MH_MMU_INVALIDATE 0x00000045 |
| #define A2XX_MH_MMU_INVALIDATE_INVALIDATE_ALL 0x00000001 |
| #define A2XX_MH_MMU_INVALIDATE_INVALIDATE_TC 0x00000002 |
| |
| #define REG_A2XX_MH_MMU_MPU_BASE 0x00000046 |
| |
| #define REG_A2XX_MH_MMU_MPU_END 0x00000047 |
| |
| #define REG_A2XX_NQWAIT_UNTIL 0x00000394 |
| |
| #define REG_A2XX_RBBM_PERFCOUNTER1_SELECT 0x00000395 |
| |
| #define REG_A2XX_RBBM_PERFCOUNTER1_LO 0x00000397 |
| |
| #define REG_A2XX_RBBM_PERFCOUNTER1_HI 0x00000398 |
| |
| #define REG_A2XX_RBBM_DEBUG 0x0000039b |
| |
| #define REG_A2XX_RBBM_PM_OVERRIDE1 0x0000039c |
| #define A2XX_RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE 0x00000001 |
| #define A2XX_RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE 0x00000002 |
| #define A2XX_RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE 0x00000004 |
| #define A2XX_RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE 0x00000008 |
| #define A2XX_RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE 0x00000010 |
| #define A2XX_RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE 0x00000020 |
| #define A2XX_RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE 0x00000040 |
| #define A2XX_RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE 0x00000080 |
| #define A2XX_RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE 0x00000100 |
| #define A2XX_RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE 0x00000200 |
| #define A2XX_RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE 0x00000400 |
| #define A2XX_RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE 0x00000800 |
| #define A2XX_RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE 0x00001000 |
| #define A2XX_RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE 0x00002000 |
| #define A2XX_RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE 0x00004000 |
| #define A2XX_RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE 0x00008000 |
| #define A2XX_RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE 0x00010000 |
| #define A2XX_RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE 0x00020000 |
| #define A2XX_RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE 0x00040000 |
| #define A2XX_RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE 0x00080000 |
| #define A2XX_RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE 0x00100000 |
| #define A2XX_RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE 0x00200000 |
| #define A2XX_RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE 0x00400000 |
| #define A2XX_RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE 0x00800000 |
| #define A2XX_RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE 0x01000000 |
| #define A2XX_RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE 0x02000000 |
| #define A2XX_RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE 0x04000000 |
| #define A2XX_RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE 0x08000000 |
| #define A2XX_RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE 0x10000000 |
| #define A2XX_RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE 0x20000000 |
| #define A2XX_RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE 0x40000000 |
| #define A2XX_RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE 0x80000000 |
| |
| #define REG_A2XX_RBBM_PM_OVERRIDE2 0x0000039d |
| |
| #define REG_A2XX_RBBM_DEBUG_OUT 0x000003a0 |
| |
| #define REG_A2XX_RBBM_DEBUG_CNTL 0x000003a1 |
| |
| #define REG_A2XX_RBBM_READ_ERROR 0x000003b3 |
| |
| #define REG_A2XX_RBBM_INT_CNTL 0x000003b4 |
| #define A2XX_RBBM_INT_CNTL_RDERR_INT_MASK 0x00000001 |
| #define A2XX_RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK 0x00000002 |
| #define A2XX_RBBM_INT_CNTL_GUI_IDLE_INT_MASK 0x00080000 |
| |
| #define REG_A2XX_RBBM_INT_STATUS 0x000003b5 |
| |
| #define REG_A2XX_RBBM_INT_ACK 0x000003b6 |
| |
| #define REG_A2XX_MASTER_INT_SIGNAL 0x000003b7 |
| #define A2XX_MASTER_INT_SIGNAL_MH_INT_STAT 0x00000020 |
| #define A2XX_MASTER_INT_SIGNAL_SQ_INT_STAT 0x04000000 |
| #define A2XX_MASTER_INT_SIGNAL_CP_INT_STAT 0x40000000 |
| #define A2XX_MASTER_INT_SIGNAL_RBBM_INT_STAT 0x80000000 |
| |
| #define REG_A2XX_RBBM_PERIPHID1 0x000003f9 |
| |
| #define REG_A2XX_RBBM_PERIPHID2 0x000003fa |
| |
| #define REG_A2XX_CP_PERFMON_CNTL 0x00000444 |
| |
| #define REG_A2XX_CP_PERFCOUNTER_SELECT 0x00000445 |
| |
| #define REG_A2XX_CP_PERFCOUNTER_LO 0x00000446 |
| |
| #define REG_A2XX_CP_PERFCOUNTER_HI 0x00000447 |
| |
| #define REG_A2XX_RBBM_STATUS 0x000005d0 |
| #define A2XX_RBBM_STATUS_CMDFIFO_AVAIL__MASK 0x0000001f |
| #define A2XX_RBBM_STATUS_CMDFIFO_AVAIL__SHIFT 0 |
| static inline uint32_t A2XX_RBBM_STATUS_CMDFIFO_AVAIL(uint32_t val) |
| { |
| return ((val) << A2XX_RBBM_STATUS_CMDFIFO_AVAIL__SHIFT) & A2XX_RBBM_STATUS_CMDFIFO_AVAIL__MASK; |
| } |
| #define A2XX_RBBM_STATUS_TC_BUSY 0x00000020 |
| #define A2XX_RBBM_STATUS_HIRQ_PENDING 0x00000100 |
| #define A2XX_RBBM_STATUS_CPRQ_PENDING 0x00000200 |
| #define A2XX_RBBM_STATUS_CFRQ_PENDING 0x00000400 |
| #define A2XX_RBBM_STATUS_PFRQ_PENDING 0x00000800 |
| #define A2XX_RBBM_STATUS_VGT_BUSY_NO_DMA 0x00001000 |
| #define A2XX_RBBM_STATUS_RBBM_WU_BUSY 0x00004000 |
| #define A2XX_RBBM_STATUS_CP_NRT_BUSY 0x00010000 |
| #define A2XX_RBBM_STATUS_MH_BUSY 0x00040000 |
| #define A2XX_RBBM_STATUS_MH_COHERENCY_BUSY 0x00080000 |
| #define A2XX_RBBM_STATUS_SX_BUSY 0x00200000 |
| #define A2XX_RBBM_STATUS_TPC_BUSY 0x00400000 |
| #define A2XX_RBBM_STATUS_SC_CNTX_BUSY 0x01000000 |
| #define A2XX_RBBM_STATUS_PA_BUSY 0x02000000 |
| #define A2XX_RBBM_STATUS_VGT_BUSY 0x04000000 |
| #define A2XX_RBBM_STATUS_SQ_CNTX17_BUSY 0x08000000 |
| #define A2XX_RBBM_STATUS_SQ_CNTX0_BUSY 0x10000000 |
| #define A2XX_RBBM_STATUS_RB_CNTX_BUSY 0x40000000 |
| #define A2XX_RBBM_STATUS_GUI_ACTIVE 0x80000000 |
| |
| #define REG_A2XX_MH_ARBITER_CONFIG 0x00000a40 |
| #define A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT__MASK 0x0000003f |
| #define A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT__SHIFT 0 |
| static inline uint32_t A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT(uint32_t val) |
| { |
| return ((val) << A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT__SHIFT) & A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT__MASK; |
| } |
| #define A2XX_MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY 0x00000040 |
| #define A2XX_MH_ARBITER_CONFIG_L1_ARB_ENABLE 0x00000080 |
| #define A2XX_MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE 0x00000100 |
| #define A2XX_MH_ARBITER_CONFIG_L2_ARB_CONTROL 0x00000200 |
| #define A2XX_MH_ARBITER_CONFIG_PAGE_SIZE__MASK 0x00001c00 |
| #define A2XX_MH_ARBITER_CONFIG_PAGE_SIZE__SHIFT 10 |
| static inline uint32_t A2XX_MH_ARBITER_CONFIG_PAGE_SIZE(uint32_t val) |
| { |
| return ((val) << A2XX_MH_ARBITER_CONFIG_PAGE_SIZE__SHIFT) & A2XX_MH_ARBITER_CONFIG_PAGE_SIZE__MASK; |
| } |
| #define A2XX_MH_ARBITER_CONFIG_TC_REORDER_ENABLE 0x00002000 |
| #define A2XX_MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE 0x00004000 |
| #define A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE 0x00008000 |
| #define A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT__MASK 0x003f0000 |
| #define A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT__SHIFT 16 |
| static inline uint32_t A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT(uint32_t val) |
| { |
| return ((val) << A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT__SHIFT) & A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT__MASK; |
| } |
| #define A2XX_MH_ARBITER_CONFIG_CP_CLNT_ENABLE 0x00400000 |
| #define A2XX_MH_ARBITER_CONFIG_VGT_CLNT_ENABLE 0x00800000 |
| #define A2XX_MH_ARBITER_CONFIG_TC_CLNT_ENABLE 0x01000000 |
| #define A2XX_MH_ARBITER_CONFIG_RB_CLNT_ENABLE 0x02000000 |
| #define A2XX_MH_ARBITER_CONFIG_PA_CLNT_ENABLE 0x04000000 |
| |
| #define REG_A2XX_MH_INTERRUPT_MASK 0x00000a42 |
| #define A2XX_MH_INTERRUPT_MASK_AXI_READ_ERROR 0x00000001 |
| #define A2XX_MH_INTERRUPT_MASK_AXI_WRITE_ERROR 0x00000002 |
| #define A2XX_MH_INTERRUPT_MASK_MMU_PAGE_FAULT 0x00000004 |
| |
| #define REG_A2XX_MH_INTERRUPT_STATUS 0x00000a43 |
| |
| #define REG_A2XX_MH_INTERRUPT_CLEAR 0x00000a44 |
| |
| #define REG_A2XX_MH_CLNT_INTF_CTRL_CONFIG1 0x00000a54 |
| |
| #define REG_A2XX_MH_CLNT_INTF_CTRL_CONFIG2 0x00000a55 |
| |
| #define REG_A2XX_A220_VSC_BIN_SIZE 0x00000c01 |
| #define A2XX_A220_VSC_BIN_SIZE_WIDTH__MASK 0x0000001f |
| #define A2XX_A220_VSC_BIN_SIZE_WIDTH__SHIFT 0 |
| static inline uint32_t A2XX_A220_VSC_BIN_SIZE_WIDTH(uint32_t val) |
| { |
| return ((val >> 5) << A2XX_A220_VSC_BIN_SIZE_WIDTH__SHIFT) & A2XX_A220_VSC_BIN_SIZE_WIDTH__MASK; |
| } |
| #define A2XX_A220_VSC_BIN_SIZE_HEIGHT__MASK 0x000003e0 |
| #define A2XX_A220_VSC_BIN_SIZE_HEIGHT__SHIFT 5 |
| static inline uint32_t A2XX_A220_VSC_BIN_SIZE_HEIGHT(uint32_t val) |
| { |
| return ((val >> 5) << A2XX_A220_VSC_BIN_SIZE_HEIGHT__SHIFT) & A2XX_A220_VSC_BIN_SIZE_HEIGHT__MASK; |
| } |
| |
| static inline uint32_t REG_A2XX_VSC_PIPE(uint32_t i0) { return 0x00000c06 + 0x3*i0; } |
| |
| static inline uint32_t REG_A2XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c06 + 0x3*i0; } |
| |
| static inline uint32_t REG_A2XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { return 0x00000c07 + 0x3*i0; } |
| |
| static inline uint32_t REG_A2XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x00000c08 + 0x3*i0; } |
| |
| #define REG_A2XX_PC_DEBUG_CNTL 0x00000c38 |
| |
| #define REG_A2XX_PC_DEBUG_DATA 0x00000c39 |
| |
| #define REG_A2XX_PA_SC_VIZ_QUERY_STATUS 0x00000c44 |
| |
| #define REG_A2XX_GRAS_DEBUG_CNTL 0x00000c80 |
| |
| #define REG_A2XX_PA_SU_DEBUG_CNTL 0x00000c80 |
| |
| #define REG_A2XX_GRAS_DEBUG_DATA 0x00000c81 |
| |
| #define REG_A2XX_PA_SU_DEBUG_DATA 0x00000c81 |
| |
| #define REG_A2XX_PA_SU_FACE_DATA 0x00000c86 |
| #define A2XX_PA_SU_FACE_DATA_BASE_ADDR__MASK 0xffffffe0 |
| #define A2XX_PA_SU_FACE_DATA_BASE_ADDR__SHIFT 5 |
| static inline uint32_t A2XX_PA_SU_FACE_DATA_BASE_ADDR(uint32_t val) |
| { |
| return ((val) << A2XX_PA_SU_FACE_DATA_BASE_ADDR__SHIFT) & A2XX_PA_SU_FACE_DATA_BASE_ADDR__MASK; |
| } |
| |
| #define REG_A2XX_SQ_GPR_MANAGEMENT 0x00000d00 |
| #define A2XX_SQ_GPR_MANAGEMENT_REG_DYNAMIC 0x00000001 |
| #define A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_PIX__MASK 0x00000ff0 |
| #define A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_PIX__SHIFT 4 |
| static inline uint32_t A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_PIX(uint32_t val) |
| { |
| return ((val) << A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_PIX__SHIFT) & A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_PIX__MASK; |
| } |
| #define A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_VTX__MASK 0x000ff000 |
| #define A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_VTX__SHIFT 12 |
| static inline uint32_t A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_VTX(uint32_t val) |
| { |
| return ((val) << A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_VTX__SHIFT) & A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_VTX__MASK; |
| } |
| |
| #define REG_A2XX_SQ_FLOW_CONTROL 0x00000d01 |
| |
| #define REG_A2XX_SQ_INST_STORE_MANAGMENT 0x00000d02 |
| #define A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_PIX__MASK 0x00000fff |
| #define A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_PIX__SHIFT 0 |
| static inline uint32_t A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_PIX(uint32_t val) |
| { |
| return ((val) << A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_PIX__SHIFT) & A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_PIX__MASK; |
| } |
| #define A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_VTX__MASK 0x0fff0000 |
| #define A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_VTX__SHIFT 16 |
| static inline uint32_t A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_VTX(uint32_t val) |
| { |
| return ((val) << A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_VTX__SHIFT) & A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_VTX__MASK; |
| } |
| |
| #define REG_A2XX_SQ_DEBUG_MISC 0x00000d05 |
| |
| #define REG_A2XX_SQ_INT_CNTL 0x00000d34 |
| |
| #define REG_A2XX_SQ_INT_STATUS 0x00000d35 |
| |
| #define REG_A2XX_SQ_INT_ACK 0x00000d36 |
| |
| #define REG_A2XX_SQ_DEBUG_INPUT_FSM 0x00000dae |
| |
| #define REG_A2XX_SQ_DEBUG_CONST_MGR_FSM 0x00000daf |
| |
| #define REG_A2XX_SQ_DEBUG_TP_FSM 0x00000db0 |
| |
| #define REG_A2XX_SQ_DEBUG_FSM_ALU_0 0x00000db1 |
| |
| #define REG_A2XX_SQ_DEBUG_FSM_ALU_1 0x00000db2 |
| |
| #define REG_A2XX_SQ_DEBUG_EXP_ALLOC 0x00000db3 |
| |
| #define REG_A2XX_SQ_DEBUG_PTR_BUFF 0x00000db4 |
| |
| #define REG_A2XX_SQ_DEBUG_GPR_VTX 0x00000db5 |
| |
| #define REG_A2XX_SQ_DEBUG_GPR_PIX 0x00000db6 |
| |
| #define REG_A2XX_SQ_DEBUG_TB_STATUS_SEL 0x00000db7 |
| |
| #define REG_A2XX_SQ_DEBUG_VTX_TB_0 0x00000db8 |
| |
| #define REG_A2XX_SQ_DEBUG_VTX_TB_1 0x00000db9 |
| |
| #define REG_A2XX_SQ_DEBUG_VTX_TB_STATUS_REG 0x00000dba |
| |
| #define REG_A2XX_SQ_DEBUG_VTX_TB_STATE_MEM 0x00000dbb |
| |
| #define REG_A2XX_SQ_DEBUG_PIX_TB_0 0x00000dbc |
| |
| #define REG_A2XX_SQ_DEBUG_PIX_TB_STATUS_REG_0 0x00000dbd |
| |
| #define REG_A2XX_SQ_DEBUG_PIX_TB_STATUS_REG_1 0x00000dbe |
| |
| #define REG_A2XX_SQ_DEBUG_PIX_TB_STATUS_REG_2 0x00000dbf |
| |
| #define REG_A2XX_SQ_DEBUG_PIX_TB_STATUS_REG_3 0x00000dc0 |
| |
| #define REG_A2XX_SQ_DEBUG_PIX_TB_STATE_MEM 0x00000dc1 |
| |
| #define REG_A2XX_TC_CNTL_STATUS 0x00000e00 |
| #define A2XX_TC_CNTL_STATUS_L2_INVALIDATE 0x00000001 |
| |
| #define REG_A2XX_TP0_CHICKEN 0x00000e1e |
| |
| #define REG_A2XX_RB_BC_CONTROL 0x00000f01 |
| #define A2XX_RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE 0x00000001 |
| #define A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT__MASK 0x00000006 |
| #define A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT__SHIFT 1 |
| static inline uint32_t A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT(uint32_t val) |
| { |
| return ((val) << A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT__SHIFT) & A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT__MASK; |
| } |
| #define A2XX_RB_BC_CONTROL_DISABLE_EDRAM_CAM 0x00000008 |
| #define A2XX_RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH 0x00000010 |
| #define A2XX_RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP 0x00000020 |
| #define A2XX_RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP 0x00000040 |
| #define A2XX_RB_BC_CONTROL_ENABLE_AZ_THROTTLE 0x00000080 |
| #define A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT__MASK 0x00001f00 |
| #define A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT__SHIFT 8 |
| static inline uint32_t A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT(uint32_t val) |
| { |
| return ((val) << A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT__SHIFT) & A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT__MASK; |
| } |
| #define A2XX_RB_BC_CONTROL_ENABLE_CRC_UPDATE 0x00004000 |
| #define A2XX_RB_BC_CONTROL_CRC_MODE 0x00008000 |
| #define A2XX_RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS 0x00010000 |
| #define A2XX_RB_BC_CONTROL_DISABLE_ACCUM 0x00020000 |
| #define A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK__MASK 0x003c0000 |
| #define A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK__SHIFT 18 |
| static inline uint32_t A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK(uint32_t val) |
| { |
| return ((val) << A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK__SHIFT) & A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK__MASK; |
| } |
| #define A2XX_RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE 0x00400000 |
| #define A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT__MASK 0x07800000 |
| #define A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT__SHIFT 23 |
| static inline uint32_t A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT(uint32_t val) |
| { |
| return ((val) << A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT__SHIFT) & A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT__MASK; |
| } |
| #define A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT__MASK 0x18000000 |
| #define A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT__SHIFT 27 |
| static inline uint32_t A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT(uint32_t val) |
| { |
| return ((val) << A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT__SHIFT) & A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT__MASK; |
| } |
| #define A2XX_RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE 0x20000000 |
| #define A2XX_RB_BC_CONTROL_CRC_SYSTEM 0x40000000 |
| #define A2XX_RB_BC_CONTROL_RESERVED6 0x80000000 |
| |
| #define REG_A2XX_RB_EDRAM_INFO 0x00000f02 |
| |
| #define REG_A2XX_RB_DEBUG_CNTL 0x00000f26 |
| |
| #define REG_A2XX_RB_DEBUG_DATA 0x00000f27 |
| |
| #define REG_A2XX_RB_SURFACE_INFO 0x00002000 |
| #define A2XX_RB_SURFACE_INFO_SURFACE_PITCH__MASK 0x00003fff |
| #define A2XX_RB_SURFACE_INFO_SURFACE_PITCH__SHIFT 0 |
| static inline uint32_t A2XX_RB_SURFACE_INFO_SURFACE_PITCH(uint32_t val) |
| { |
| return ((val) << A2XX_RB_SURFACE_INFO_SURFACE_PITCH__SHIFT) & A2XX_RB_SURFACE_INFO_SURFACE_PITCH__MASK; |
| } |
| #define A2XX_RB_SURFACE_INFO_MSAA_SAMPLES__MASK 0x0000c000 |
| #define A2XX_RB_SURFACE_INFO_MSAA_SAMPLES__SHIFT 14 |
| static inline uint32_t A2XX_RB_SURFACE_INFO_MSAA_SAMPLES(uint32_t val) |
| { |
| return ((val) << A2XX_RB_SURFACE_INFO_MSAA_SAMPLES__SHIFT) & A2XX_RB_SURFACE_INFO_MSAA_SAMPLES__MASK; |
| } |
| |
| #define REG_A2XX_RB_COLOR_INFO 0x00002001 |
| #define A2XX_RB_COLOR_INFO_FORMAT__MASK 0x0000000f |
| #define A2XX_RB_COLOR_INFO_FORMAT__SHIFT 0 |
| static inline uint32_t A2XX_RB_COLOR_INFO_FORMAT(enum a2xx_colorformatx val) |
| { |
| return ((val) << A2XX_RB_COLOR_INFO_FORMAT__SHIFT) & A2XX_RB_COLOR_INFO_FORMAT__MASK; |
| } |
| #define A2XX_RB_COLOR_INFO_ROUND_MODE__MASK 0x00000030 |
| #define A2XX_RB_COLOR_INFO_ROUND_MODE__SHIFT 4 |
| static inline uint32_t A2XX_RB_COLOR_INFO_ROUND_MODE(uint32_t val) |
| { |
| return ((val) << A2XX_RB_COLOR_INFO_ROUND_MODE__SHIFT) & A2XX_RB_COLOR_INFO_ROUND_MODE__MASK; |
| } |
| #define A2XX_RB_COLOR_INFO_LINEAR 0x00000040 |
| #define A2XX_RB_COLOR_INFO_ENDIAN__MASK 0x00000180 |
| #define A2XX_RB_COLOR_INFO_ENDIAN__SHIFT 7 |
| static inline uint32_t A2XX_RB_COLOR_INFO_ENDIAN(uint32_t val) |
| { |
| return ((val) << A2XX_RB_COLOR_INFO_ENDIAN__SHIFT) & A2XX_RB_COLOR_INFO_ENDIAN__MASK; |
| } |
| #define A2XX_RB_COLOR_INFO_SWAP__MASK 0x00000600 |
| #define A2XX_RB_COLOR_INFO_SWAP__SHIFT 9 |
| static inline uint32_t A2XX_RB_COLOR_INFO_SWAP(uint32_t val) |
| { |
| return ((val) << A2XX_RB_COLOR_INFO_SWAP__SHIFT) & A2XX_RB_COLOR_INFO_SWAP__MASK; |
| } |
| #define A2XX_RB_COLOR_INFO_BASE__MASK 0xfffff000 |
| #define A2XX_RB_COLOR_INFO_BASE__SHIFT 12 |
| static inline uint32_t A2XX_RB_COLOR_INFO_BASE(uint32_t val) |
| { |
| return ((val >> 12) << A2XX_RB_COLOR_INFO_BASE__SHIFT) & A2XX_RB_COLOR_INFO_BASE__MASK; |
| } |
| |
| #define REG_A2XX_RB_DEPTH_INFO 0x00002002 |
| #define A2XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK 0x00000001 |
| #define A2XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT 0 |
| static inline uint32_t A2XX_RB_DEPTH_INFO_DEPTH_FORMAT(enum adreno_rb_depth_format val) |
| { |
| return ((val) << A2XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT) & A2XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK; |
| } |
| #define A2XX_RB_DEPTH_INFO_DEPTH_BASE__MASK 0xfffff000 |
| #define A2XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT 12 |
| static inline uint32_t A2XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val) |
| { |
| return ((val >> 12) << A2XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT) & A2XX_RB_DEPTH_INFO_DEPTH_BASE__MASK; |
| } |
| |
| #define REG_A2XX_A225_RB_COLOR_INFO3 0x00002005 |
| |
| #define REG_A2XX_COHER_DEST_BASE_0 0x00002006 |
| |
| #define REG_A2XX_PA_SC_SCREEN_SCISSOR_TL 0x0000200e |
| #define A2XX_PA_SC_SCREEN_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000 |
| #define A2XX_PA_SC_SCREEN_SCISSOR_TL_X__MASK 0x00007fff |
| #define A2XX_PA_SC_SCREEN_SCISSOR_TL_X__SHIFT 0 |
| static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_TL_X(uint32_t val) |
| { |
| return ((val) << A2XX_PA_SC_SCREEN_SCISSOR_TL_X__SHIFT) & A2XX_PA_SC_SCREEN_SCISSOR_TL_X__MASK; |
| } |
| #define A2XX_PA_SC_SCREEN_SCISSOR_TL_Y__MASK 0x7fff0000 |
| #define A2XX_PA_SC_SCREEN_SCISSOR_TL_Y__SHIFT 16 |
| static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_TL_Y(uint32_t val) |
| { |
| return ((val) << A2XX_PA_SC_SCREEN_SCISSOR_TL_Y__SHIFT) & A2XX_PA_SC_SCREEN_SCISSOR_TL_Y__MASK; |
| } |
| |
| #define REG_A2XX_PA_SC_SCREEN_SCISSOR_BR 0x0000200f |
| #define A2XX_PA_SC_SCREEN_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000 |
| #define A2XX_PA_SC_SCREEN_SCISSOR_BR_X__MASK 0x00007fff |
| #define A2XX_PA_SC_SCREEN_SCISSOR_BR_X__SHIFT 0 |
| static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_BR_X(uint32_t val) |
| { |
| return ((val) << A2XX_PA_SC_SCREEN_SCISSOR_BR_X__SHIFT) & A2XX_PA_SC_SCREEN_SCISSOR_BR_X__MASK; |
| } |
| #define A2XX_PA_SC_SCREEN_SCISSOR_BR_Y__MASK 0x7fff0000 |
| #define A2XX_PA_SC_SCREEN_SCISSOR_BR_Y__SHIFT 16 |
| static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_BR_Y(uint32_t val) |
| { |
| return ((val) << A2XX_PA_SC_SCREEN_SCISSOR_BR_Y__SHIFT) & A2XX_PA_SC_SCREEN_SCISSOR_BR_Y__MASK; |
| } |
| |
| #define REG_A2XX_PA_SC_WINDOW_OFFSET 0x00002080 |
| #define A2XX_PA_SC_WINDOW_OFFSET_X__MASK 0x00007fff |
| #define A2XX_PA_SC_WINDOW_OFFSET_X__SHIFT 0 |
| static inline uint32_t A2XX_PA_SC_WINDOW_OFFSET_X(int32_t val) |
| { |
| return ((val) << A2XX_PA_SC_WINDOW_OFFSET_X__SHIFT) & A2XX_PA_SC_WINDOW_OFFSET_X__MASK; |
| } |
| #define A2XX_PA_SC_WINDOW_OFFSET_Y__MASK 0x7fff0000 |
| #define A2XX_PA_SC_WINDOW_OFFSET_Y__SHIFT 16 |
| static inline uint32_t A2XX_PA_SC_WINDOW_OFFSET_Y(int32_t val) |
| { |
| return ((val) << A2XX_PA_SC_WINDOW_OFFSET_Y__SHIFT) & A2XX_PA_SC_WINDOW_OFFSET_Y__MASK; |
| } |
| #define A2XX_PA_SC_WINDOW_OFFSET_DISABLE 0x80000000 |
| |
| #define REG_A2XX_PA_SC_WINDOW_SCISSOR_TL 0x00002081 |
| #define A2XX_PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000 |
| #define A2XX_PA_SC_WINDOW_SCISSOR_TL_X__MASK 0x00007fff |
| #define A2XX_PA_SC_WINDOW_SCISSOR_TL_X__SHIFT 0 |
| static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_TL_X(uint32_t val) |
| { |
| return ((val) << A2XX_PA_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A2XX_PA_SC_WINDOW_SCISSOR_TL_X__MASK; |
| } |
| #define A2XX_PA_SC_WINDOW_SCISSOR_TL_Y__MASK 0x7fff0000 |
| #define A2XX_PA_SC_WINDOW_SCISSOR_TL_Y__SHIFT 16 |
| static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_TL_Y(uint32_t val) |
| { |
| return ((val) << A2XX_PA_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A2XX_PA_SC_WINDOW_SCISSOR_TL_Y__MASK; |
| } |
| |
| #define REG_A2XX_PA_SC_WINDOW_SCISSOR_BR 0x00002082 |
| #define A2XX_PA_SC_WINDOW_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000 |
| #define A2XX_PA_SC_WINDOW_SCISSOR_BR_X__MASK 0x00007fff |
| #define A2XX_PA_SC_WINDOW_SCISSOR_BR_X__SHIFT 0 |
| static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_BR_X(uint32_t val) |
| { |
| return ((val) << A2XX_PA_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A2XX_PA_SC_WINDOW_SCISSOR_BR_X__MASK; |
| } |
| #define A2XX_PA_SC_WINDOW_SCISSOR_BR_Y__MASK 0x7fff0000 |
| #define A2XX_PA_SC_WINDOW_SCISSOR_BR_Y__SHIFT 16 |
| static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_BR_Y(uint32_t val) |
| { |
| return ((val) << A2XX_PA_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A2XX_PA_SC_WINDOW_SCISSOR_BR_Y__MASK; |
| } |
| |
| #define REG_A2XX_UNKNOWN_2010 0x00002010 |
| |
| #define REG_A2XX_VGT_MAX_VTX_INDX 0x00002100 |
| |
| #define REG_A2XX_VGT_MIN_VTX_INDX 0x00002101 |
| |
| #define REG_A2XX_VGT_INDX_OFFSET 0x00002102 |
| |
| #define REG_A2XX_A225_PC_MULTI_PRIM_IB_RESET_INDX 0x00002103 |
| |
| #define REG_A2XX_RB_COLOR_MASK 0x00002104 |
| #define A2XX_RB_COLOR_MASK_WRITE_RED 0x00000001 |
| #define A2XX_RB_COLOR_MASK_WRITE_GREEN 0x00000002 |
| #define A2XX_RB_COLOR_MASK_WRITE_BLUE 0x00000004 |
| #define A2XX_RB_COLOR_MASK_WRITE_ALPHA 0x00000008 |
| |
| #define REG_A2XX_RB_BLEND_RED 0x00002105 |
| |
| #define REG_A2XX_RB_BLEND_GREEN 0x00002106 |
| |
| #define REG_A2XX_RB_BLEND_BLUE 0x00002107 |
| |
| #define REG_A2XX_RB_BLEND_ALPHA 0x00002108 |
| |
| #define REG_A2XX_RB_FOG_COLOR 0x00002109 |
| #define A2XX_RB_FOG_COLOR_FOG_RED__MASK 0x000000ff |
| #define A2XX_RB_FOG_COLOR_FOG_RED__SHIFT 0 |
| static inline uint32_t A2XX_RB_FOG_COLOR_FOG_RED(uint32_t val) |
| { |
| return ((val) << A2XX_RB_FOG_COLOR_FOG_RED__SHIFT) & A2XX_RB_FOG_COLOR_FOG_RED__MASK; |
| } |
| #define A2XX_RB_FOG_COLOR_FOG_GREEN__MASK 0x0000ff00 |
| #define A2XX_RB_FOG_COLOR_FOG_GREEN__SHIFT 8 |
| static inline uint32_t A2XX_RB_FOG_COLOR_FOG_GREEN(uint32_t val) |
| { |
| return ((val) << A2XX_RB_FOG_COLOR_FOG_GREEN__SHIFT) & A2XX_RB_FOG_COLOR_FOG_GREEN__MASK; |
| } |
| #define A2XX_RB_FOG_COLOR_FOG_BLUE__MASK 0x00ff0000 |
| #define A2XX_RB_FOG_COLOR_FOG_BLUE__SHIFT 16 |
| static inline uint32_t A2XX_RB_FOG_COLOR_FOG_BLUE(uint32_t val) |
| { |
| return ((val) << A2XX_RB_FOG_COLOR_FOG_BLUE__SHIFT) & A2XX_RB_FOG_COLOR_FOG_BLUE__MASK; |
| } |
| |
| #define REG_A2XX_RB_STENCILREFMASK_BF 0x0000210c |
| #define A2XX_RB_STENCILREFMASK_BF_STENCILREF__MASK 0x000000ff |
| #define A2XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT 0 |
| static inline uint32_t A2XX_RB_STENCILREFMASK_BF_STENCILREF(uint32_t val) |
| { |
| return ((val) << A2XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT) & A2XX_RB_STENCILREFMASK_BF_STENCILREF__MASK; |
| } |
| #define A2XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK 0x0000ff00 |
| #define A2XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT 8 |
| static inline uint32_t A2XX_RB_STENCILREFMASK_BF_STENCILMASK(uint32_t val) |
| { |
| return ((val) << A2XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT) & A2XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK; |
| } |
| #define A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK 0x00ff0000 |
| #define A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT 16 |
| static inline uint32_t A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(uint32_t val) |
| { |
| return ((val) << A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT) & A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK; |
| } |
| |
| #define REG_A2XX_RB_STENCILREFMASK 0x0000210d |
| #define A2XX_RB_STENCILREFMASK_STENCILREF__MASK 0x000000ff |
| #define A2XX_RB_STENCILREFMASK_STENCILREF__SHIFT 0 |
| static inline uint32_t A2XX_RB_STENCILREFMASK_STENCILREF(uint32_t val) |
| { |
| return ((val) << A2XX_RB_STENCILREFMASK_STENCILREF__SHIFT) & A2XX_RB_STENCILREFMASK_STENCILREF__MASK; |
| } |
| #define A2XX_RB_STENCILREFMASK_STENCILMASK__MASK 0x0000ff00 |
| #define A2XX_RB_STENCILREFMASK_STENCILMASK__SHIFT 8 |
| static inline uint32_t A2XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val) |
| { |
| return ((val) << A2XX_RB_STENCILREFMASK_STENCILMASK__SHIFT) & A2XX_RB_STENCILREFMASK_STENCILMASK__MASK; |
| } |
| #define A2XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK 0x00ff0000 |
| #define A2XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT 16 |
| static inline uint32_t A2XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val) |
| { |
| return ((val) << A2XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT) & A2XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK; |
| } |
| |
| #define REG_A2XX_RB_ALPHA_REF 0x0000210e |
| |
| #define REG_A2XX_PA_CL_VPORT_XSCALE 0x0000210f |
| #define A2XX_PA_CL_VPORT_XSCALE__MASK 0xffffffff |
| #define A2XX_PA_CL_VPORT_XSCALE__SHIFT 0 |
| static inline uint32_t A2XX_PA_CL_VPORT_XSCALE(float val) |
| { |
| return ((fui(val)) << A2XX_PA_CL_VPORT_XSCALE__SHIFT) & A2XX_PA_CL_VPORT_XSCALE__MASK; |
| } |
| |
| #define REG_A2XX_PA_CL_VPORT_XOFFSET 0x00002110 |
| #define A2XX_PA_CL_VPORT_XOFFSET__MASK 0xffffffff |
| #define A2XX_PA_CL_VPORT_XOFFSET__SHIFT 0 |
| static inline uint32_t A2XX_PA_CL_VPORT_XOFFSET(float val) |
| { |
| return ((fui(val)) << A2XX_PA_CL_VPORT_XOFFSET__SHIFT) & A2XX_PA_CL_VPORT_XOFFSET__MASK; |
| } |
| |
| #define REG_A2XX_PA_CL_VPORT_YSCALE 0x00002111 |
| #define A2XX_PA_CL_VPORT_YSCALE__MASK 0xffffffff |
| #define A2XX_PA_CL_VPORT_YSCALE__SHIFT 0 |
| static inline uint32_t A2XX_PA_CL_VPORT_YSCALE(float val) |
| { |
| return ((fui(val)) << A2XX_PA_CL_VPORT_YSCALE__SHIFT) & A2XX_PA_CL_VPORT_YSCALE__MASK; |
| } |
| |
| #define REG_A2XX_PA_CL_VPORT_YOFFSET 0x00002112 |
| #define A2XX_PA_CL_VPORT_YOFFSET__MASK 0xffffffff |
| #define A2XX_PA_CL_VPORT_YOFFSET__SHIFT 0 |
| static inline uint32_t A2XX_PA_CL_VPORT_YOFFSET(float val) |
| { |
| return ((fui(val)) << A2XX_PA_CL_VPORT_YOFFSET__SHIFT) & A2XX_PA_CL_VPORT_YOFFSET__MASK; |
| } |
| |
| #define REG_A2XX_PA_CL_VPORT_ZSCALE 0x00002113 |
| #define A2XX_PA_CL_VPORT_ZSCALE__MASK 0xffffffff |
| #define A2XX_PA_CL_VPORT_ZSCALE__SHIFT 0 |
| static inline uint32_t A2XX_PA_CL_VPORT_ZSCALE(float val) |
| { |
| return ((fui(val)) << A2XX_PA_CL_VPORT_ZSCALE__SHIFT) & A2XX_PA_CL_VPORT_ZSCALE__MASK; |
| } |
| |
| #define REG_A2XX_PA_CL_VPORT_ZOFFSET 0x00002114 |
| #define A2XX_PA_CL_VPORT_ZOFFSET__MASK 0xffffffff |
| #define A2XX_PA_CL_VPORT_ZOFFSET__SHIFT 0 |
| static inline uint32_t A2XX_PA_CL_VPORT_ZOFFSET(float val) |
| { |
| return ((fui(val)) << A2XX_PA_CL_VPORT_ZOFFSET__SHIFT) & A2XX_PA_CL_VPORT_ZOFFSET__MASK; |
| } |
| |
| #define REG_A2XX_SQ_PROGRAM_CNTL 0x00002180 |
| #define A2XX_SQ_PROGRAM_CNTL_VS_REGS__MASK 0x000000ff |
| #define A2XX_SQ_PROGRAM_CNTL_VS_REGS__SHIFT 0 |
| static inline uint32_t A2XX_SQ_PROGRAM_CNTL_VS_REGS(uint32_t val) |
| { |
| return ((val) << A2XX_SQ_PROGRAM_CNTL_VS_REGS__SHIFT) & A2XX_SQ_PROGRAM_CNTL_VS_REGS__MASK; |
| } |
| #define A2XX_SQ_PROGRAM_CNTL_PS_REGS__MASK 0x0000ff00 |
| #define A2XX_SQ_PROGRAM_CNTL_PS_REGS__SHIFT 8 |
| static inline uint32_t A2XX_SQ_PROGRAM_CNTL_PS_REGS(uint32_t val) |
| { |
| return ((val) << A2XX_SQ_PROGRAM_CNTL_PS_REGS__SHIFT) & A2XX_SQ_PROGRAM_CNTL_PS_REGS__MASK; |
| } |
| #define A2XX_SQ_PROGRAM_CNTL_VS_RESOURCE 0x00010000 |
| #define A2XX_SQ_PROGRAM_CNTL_PS_RESOURCE 0x00020000 |
| #define A2XX_SQ_PROGRAM_CNTL_PARAM_GEN 0x00040000 |
| #define A2XX_SQ_PROGRAM_CNTL_GEN_INDEX_PIX 0x00080000 |
| #define A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT__MASK 0x00f00000 |
| #define A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT__SHIFT 20 |
| static inline uint32_t A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT(uint32_t val) |
| { |
| return ((val) << A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT__SHIFT) & A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT__MASK; |
| } |
| #define A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE__MASK 0x07000000 |
| #define A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE__SHIFT 24 |
| static inline uint32_t A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE(enum a2xx_sq_ps_vtx_mode val) |
| { |
| return ((val) << A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE__SHIFT) & A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE__MASK; |
| } |
| #define A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE__MASK 0x78000000 |
| #define A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE__SHIFT 27 |
| static inline uint32_t A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE(uint32_t val) |
| { |
| return ((val) << A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE__SHIFT) & A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE__MASK; |
| } |
| #define A2XX_SQ_PROGRAM_CNTL_GEN_INDEX_VTX 0x80000000 |
| |
| #define REG_A2XX_SQ_CONTEXT_MISC 0x00002181 |
| #define A2XX_SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE 0x00000001 |
| #define A2XX_SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY 0x00000002 |
| #define A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL__MASK 0x0000000c |
| #define A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL__SHIFT 2 |
| static inline uint32_t A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL(enum a2xx_sq_sample_cntl val) |
| { |
| return ((val) << A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL__SHIFT) & A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL__MASK; |
| } |
| #define A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS__MASK 0x0000ff00 |
| #define A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS__SHIFT 8 |
| static inline uint32_t A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS(uint32_t val) |
| { |
| return ((val) << A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS__SHIFT) & A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS__MASK; |
| } |
| #define A2XX_SQ_CONTEXT_MISC_PERFCOUNTER_REF 0x00010000 |
| #define A2XX_SQ_CONTEXT_MISC_YEILD_OPTIMIZE 0x00020000 |
| #define A2XX_SQ_CONTEXT_MISC_TX_CACHE_SEL 0x00040000 |
| |
| #define REG_A2XX_SQ_INTERPOLATOR_CNTL 0x00002182 |
| #define A2XX_SQ_INTERPOLATOR_CNTL_PARAM_SHADE__MASK 0x0000ffff |
| #define A2XX_SQ_INTERPOLATOR_CNTL_PARAM_SHADE__SHIFT 0 |
| static inline uint32_t A2XX_SQ_INTERPOLATOR_CNTL_PARAM_SHADE(uint32_t val) |
| { |
| return ((val) << A2XX_SQ_INTERPOLATOR_CNTL_PARAM_SHADE__SHIFT) & A2XX_SQ_INTERPOLATOR_CNTL_PARAM_SHADE__MASK; |
| } |
| #define A2XX_SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN__MASK 0xffff0000 |
| #define A2XX_SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN__SHIFT 16 |
| static inline uint32_t A2XX_SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN(uint32_t val) |
| { |
| return ((val) << A2XX_SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN__SHIFT) & A2XX_SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN__MASK; |
| } |
| |
| #define REG_A2XX_SQ_WRAPPING_0 0x00002183 |
| #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_0__MASK 0x0000000f |
| #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_0__SHIFT 0 |
| static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_0(uint32_t val) |
| { |
| return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_0__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_0__MASK; |
| } |
| #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_1__MASK 0x000000f0 |
| #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_1__SHIFT 4 |
| static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_1(uint32_t val) |
| { |
| return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_1__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_1__MASK; |
| } |
| #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_2__MASK 0x00000f00 |
| #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_2__SHIFT 8 |
| static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_2(uint32_t val) |
| { |
| return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_2__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_2__MASK; |
| } |
| #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_3__MASK 0x0000f000 |
| #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_3__SHIFT 12 |
| static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_3(uint32_t val) |
| { |
| return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_3__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_3__MASK; |
| } |
| #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_4__MASK 0x000f0000 |
| #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_4__SHIFT 16 |
| static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_4(uint32_t val) |
| { |
| return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_4__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_4__MASK; |
| } |
| #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_5__MASK 0x00f00000 |
| #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_5__SHIFT 20 |
| static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_5(uint32_t val) |
| { |
| return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_5__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_5__MASK; |
| } |
| #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_6__MASK 0x0f000000 |
| #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_6__SHIFT 24 |
| static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_6(uint32_t val) |
| { |
| return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_6__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_6__MASK; |
| } |
| #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_7__MASK 0xf0000000 |
| #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_7__SHIFT 28 |
| static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_7(uint32_t val) |
| { |
| return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_7__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_7__MASK; |
| } |
| |
| #define REG_A2XX_SQ_WRAPPING_1 0x00002184 |
| #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_8__MASK 0x0000000f |
| #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_8__SHIFT 0 |
| static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_8(uint32_t val) |
| { |
| return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_8__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_8__MASK; |
| } |
| #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_9__MASK 0x000000f0 |
| #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_9__SHIFT 4 |
| static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_9(uint32_t val) |
| { |
| return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_9__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_9__MASK; |
| } |
| #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_10__MASK 0x00000f00 |
| #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_10__SHIFT 8 |
| static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_10(uint32_t val) |
| { |
| return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_10__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_10__MASK; |
| } |
| #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_11__MASK 0x0000f000 |
| #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_11__SHIFT 12 |
| static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_11(uint32_t val) |
| { |
| return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_11__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_11__MASK; |
| } |
| #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_12__MASK 0x000f0000 |
| #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_12__SHIFT 16 |
| static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_12(uint32_t val) |
| { |
| return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_12__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_12__MASK; |
| } |
| #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_13__MASK 0x00f00000 |
| #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_13__SHIFT 20 |
| static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_13(uint32_t val) |
| { |
| return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_13__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_13__MASK; |
| } |
| #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_14__MASK 0x0f000000 |
| #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_14__SHIFT 24 |
| static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_14(uint32_t val) |
| { |
| return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_14__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_14__MASK; |
| } |
| #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_15__MASK 0xf0000000 |
| #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_15__SHIFT 28 |
| static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_15(uint32_t val) |
| { |
| return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_15__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_15__MASK; |
| } |
| |
| #define REG_A2XX_SQ_PS_PROGRAM 0x000021f6 |
| #define A2XX_SQ_PS_PROGRAM_BASE__MASK 0x00000fff |
| #define A2XX_SQ_PS_PROGRAM_BASE__SHIFT 0 |
| static inline uint32_t A2XX_SQ_PS_PROGRAM_BASE(uint32_t val) |
| { |
| return ((val) << A2XX_SQ_PS_PROGRAM_BASE__SHIFT) & A2XX_SQ_PS_PROGRAM_BASE__MASK; |
| } |
| #define A2XX_SQ_PS_PROGRAM_SIZE__MASK 0x00fff000 |
| #define A2XX_SQ_PS_PROGRAM_SIZE__SHIFT 12 |
| static inline uint32_t A2XX_SQ_PS_PROGRAM_SIZE(uint32_t val) |
| { |
| return ((val) << A2XX_SQ_PS_PROGRAM_SIZE__SHIFT) & A2XX_SQ_PS_PROGRAM_SIZE__MASK; |
| } |
| |
| #define REG_A2XX_SQ_VS_PROGRAM 0x000021f7 |
| #define A2XX_SQ_VS_PROGRAM_BASE__MASK 0x00000fff |
| #define A2XX_SQ_VS_PROGRAM_BASE__SHIFT 0 |
| static inline uint32_t A2XX_SQ_VS_PROGRAM_BASE(uint32_t val) |
| { |
| return ((val) << A2XX_SQ_VS_PROGRAM_BASE__SHIFT) & A2XX_SQ_VS_PROGRAM_BASE__MASK; |
| } |
| #define A2XX_SQ_VS_PROGRAM_SIZE__MASK 0x00fff000 |
| #define A2XX_SQ_VS_PROGRAM_SIZE__SHIFT 12 |
| static inline uint32_t A2XX_SQ_VS_PROGRAM_SIZE(uint32_t val) |
| { |
| return ((val) << A2XX_SQ_VS_PROGRAM_SIZE__SHIFT) & A2XX_SQ_VS_PROGRAM_SIZE__MASK; |
| } |
| |
| #define REG_A2XX_VGT_EVENT_INITIATOR 0x000021f9 |
| |
| #define REG_A2XX_VGT_DRAW_INITIATOR 0x000021fc |
| #define A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE__MASK 0x0000003f |
| #define A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE__SHIFT 0 |
| static inline uint32_t A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE(enum pc_di_primtype val) |
| { |
| return ((val) << A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE__SHIFT) & A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE__MASK; |
| } |
| #define A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__MASK 0x000000c0 |
| #define A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__SHIFT 6 |
| static inline uint32_t A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT(enum pc_di_src_sel val) |
| { |
| return ((val) << A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__SHIFT) & A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__MASK; |
| } |
| #define A2XX_VGT_DRAW_INITIATOR_VIS_CULL__MASK 0x00000600 |
| #define A2XX_VGT_DRAW_INITIATOR_VIS_CULL__SHIFT 9 |
| static inline uint32_t A2XX_VGT_DRAW_INITIATOR_VIS_CULL(enum pc_di_vis_cull_mode val) |
| { |
| return ((val) << A2XX_VGT_DRAW_INITIATOR_VIS_CULL__SHIFT) & A2XX_VGT_DRAW_INITIATOR_VIS_CULL__MASK; |
| } |
| #define A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE__MASK 0x00000800 |
| #define A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE__SHIFT 11 |
| static inline uint32_t A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE(enum pc_di_index_size val) |
| { |
| return ((val) << A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE__SHIFT) & A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE__MASK; |
| } |
| #define A2XX_VGT_DRAW_INITIATOR_NOT_EOP 0x00001000 |
| #define A2XX_VGT_DRAW_INITIATOR_SMALL_INDEX 0x00002000 |
| #define A2XX_VGT_DRAW_INITIATOR_PRE_DRAW_INITIATOR_ENABLE 0x00004000 |
| #define A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__MASK 0xff000000 |
| #define A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__SHIFT 24 |
| static inline uint32_t A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES(uint32_t val) |
| { |
| return ((val) << A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__SHIFT) & A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__MASK; |
| } |
| |
| #define REG_A2XX_VGT_IMMED_DATA 0x000021fd |
| |
| #define REG_A2XX_RB_DEPTHCONTROL 0x00002200 |
| #define A2XX_RB_DEPTHCONTROL_STENCIL_ENABLE 0x00000001 |
| #define A2XX_RB_DEPTHCONTROL_Z_ENABLE 0x00000002 |
| #define A2XX_RB_DEPTHCONTROL_Z_WRITE_ENABLE 0x00000004 |
| #define A2XX_RB_DEPTHCONTROL_EARLY_Z_ENABLE 0x00000008 |
| #define A2XX_RB_DEPTHCONTROL_ZFUNC__MASK 0x00000070 |
| #define A2XX_RB_DEPTHCONTROL_ZFUNC__SHIFT 4 |
| static inline uint32_t A2XX_RB_DEPTHCONTROL_ZFUNC(enum adreno_compare_func val) |
| { |
| return ((val) << A2XX_RB_DEPTHCONTROL_ZFUNC__SHIFT) & A2XX_RB_DEPTHCONTROL_ZFUNC__MASK; |
| } |
| #define A2XX_RB_DEPTHCONTROL_BACKFACE_ENABLE 0x00000080 |
| #define A2XX_RB_DEPTHCONTROL_STENCILFUNC__MASK 0x00000700 |
| #define A2XX_RB_DEPTHCONTROL_STENCILFUNC__SHIFT 8 |
| static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFUNC(enum adreno_compare_func val) |
| { |
| return ((val) << A2XX_RB_DEPTHCONTROL_STENCILFUNC__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILFUNC__MASK; |
| } |
| #define A2XX_RB_DEPTHCONTROL_STENCILFAIL__MASK 0x00003800 |
| #define A2XX_RB_DEPTHCONTROL_STENCILFAIL__SHIFT 11 |
| static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFAIL(enum adreno_stencil_op val) |
| { |
| return ((val) << A2XX_RB_DEPTHCONTROL_STENCILFAIL__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILFAIL__MASK; |
| } |
| #define A2XX_RB_DEPTHCONTROL_STENCILZPASS__MASK 0x0001c000 |
| #define A2XX_RB_DEPTHCONTROL_STENCILZPASS__SHIFT 14 |
| static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZPASS(enum adreno_stencil_op val) |
| { |
| return ((val) << A2XX_RB_DEPTHCONTROL_STENCILZPASS__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILZPASS__MASK; |
| } |
| #define A2XX_RB_DEPTHCONTROL_STENCILZFAIL__MASK 0x000e0000 |
| #define A2XX_RB_DEPTHCONTROL_STENCILZFAIL__SHIFT 17 |
| static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZFAIL(enum adreno_stencil_op val) |
| { |
| return ((val) << A2XX_RB_DEPTHCONTROL_STENCILZFAIL__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILZFAIL__MASK; |
| } |
| #define A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF__MASK 0x00700000 |
| #define A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF__SHIFT 20 |
| static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF(enum adreno_compare_func val) |
| { |
| return ((val) << A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF__MASK; |
| } |
| #define A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF__MASK 0x03800000 |
| #define A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF__SHIFT 23 |
| static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF(enum adreno_stencil_op val) |
| { |
| return ((val) << A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF__MASK; |
| } |
| #define A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF__MASK 0x1c000000 |
| #define A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF__SHIFT 26 |
| static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF(enum adreno_stencil_op val) |
| { |
| return ((val) << A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF__MASK; |
| } |
| #define A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF__MASK 0xe0000000 |
| #define A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF__SHIFT 29 |
| static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF(enum adreno_stencil_op val) |
| { |
| return ((val) << A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF__MASK; |
| } |
| |
| #define REG_A2XX_RB_BLEND_CONTROL 0x00002201 |
| #define A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND__MASK 0x0000001f |
| #define A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND__SHIFT 0 |
| static inline uint32_t A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND(enum adreno_rb_blend_factor val) |
| { |
| return ((val) << A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND__SHIFT) & A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND__MASK; |
| } |
| #define A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__MASK 0x000000e0 |
| #define A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__SHIFT 5 |
| static inline uint32_t A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN(enum a2xx_rb_blend_opcode val) |
| { |
| return ((val) << A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__SHIFT) & A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__MASK; |
| } |
| #define A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND__MASK 0x00001f00 |
| #define A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND__SHIFT 8 |
| static inline uint32_t A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND(enum adreno_rb_blend_factor val) |
| { |
| return ((val) << A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND__SHIFT) & A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND__MASK; |
| } |
| #define A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND__MASK 0x001f0000 |
| #define A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND__SHIFT 16 |
| static inline uint32_t A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND(enum adreno_rb_blend_factor val) |
| { |
| return ((val) << A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND__SHIFT) & A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND__MASK; |
| } |
| #define A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__MASK 0x00e00000 |
| #define A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__SHIFT 21 |
| static inline uint32_t A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN(enum a2xx_rb_blend_opcode val) |
| { |
| return ((val) << A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__SHIFT) & A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__MASK; |
| } |
| #define A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND__MASK 0x1f000000 |
| #define A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND__SHIFT 24 |
| static inline uint32_t A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND(enum adreno_rb_blend_factor val) |
| { |
| return ((val) << A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND__SHIFT) & A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND__MASK; |
| } |
| #define A2XX_RB_BLEND_CONTROL_BLEND_FORCE_ENABLE 0x20000000 |
| #define A2XX_RB_BLEND_CONTROL_BLEND_FORCE 0x40000000 |
| |
| #define REG_A2XX_RB_COLORCONTROL 0x00002202 |
| #define A2XX_RB_COLORCONTROL_ALPHA_FUNC__MASK 0x00000007 |
| #define A2XX_RB_COLORCONTROL_ALPHA_FUNC__SHIFT 0 |
| static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_FUNC(enum adreno_compare_func val) |
| { |
| return ((val) << A2XX_RB_COLORCONTROL_ALPHA_FUNC__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_FUNC__MASK; |
| } |
| #define A2XX_RB_COLORCONTROL_ALPHA_TEST_ENABLE 0x00000008 |
| #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE 0x00000010 |
| #define A2XX_RB_COLORCONTROL_BLEND_DISABLE 0x00000020 |
| #define A2XX_RB_COLORCONTROL_VOB_ENABLE 0x00000040 |
| #define A2XX_RB_COLORCONTROL_VS_EXPORTS_FOG 0x00000080 |
| #define A2XX_RB_COLORCONTROL_ROP_CODE__MASK 0x00000f00 |
| #define A2XX_RB_COLORCONTROL_ROP_CODE__SHIFT 8 |
| static inline uint32_t A2XX_RB_COLORCONTROL_ROP_CODE(uint32_t val) |
| { |
| return ((val) << A2XX_RB_COLORCONTROL_ROP_CODE__SHIFT) & A2XX_RB_COLORCONTROL_ROP_CODE__MASK; |
| } |
| #define A2XX_RB_COLORCONTROL_DITHER_MODE__MASK 0x00003000 |
| #define A2XX_RB_COLORCONTROL_DITHER_MODE__SHIFT 12 |
| static inline uint32_t A2XX_RB_COLORCONTROL_DITHER_MODE(enum adreno_rb_dither_mode val) |
| { |
| return ((val) << A2XX_RB_COLORCONTROL_DITHER_MODE__SHIFT) & A2XX_RB_COLORCONTROL_DITHER_MODE__MASK; |
| } |
| #define A2XX_RB_COLORCONTROL_DITHER_TYPE__MASK 0x0000c000 |
| #define A2XX_RB_COLORCONTROL_DITHER_TYPE__SHIFT 14 |
| static inline uint32_t A2XX_RB_COLORCONTROL_DITHER_TYPE(enum a2xx_rb_dither_type val) |
| { |
| return ((val) << A2XX_RB_COLORCONTROL_DITHER_TYPE__SHIFT) & A2XX_RB_COLORCONTROL_DITHER_TYPE__MASK; |
| } |
| #define A2XX_RB_COLORCONTROL_PIXEL_FOG 0x00010000 |
| #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0__MASK 0x03000000 |
| #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0__SHIFT 24 |
| static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0(uint32_t val) |
| { |
| return ((val) << A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0__MASK; |
| } |
| #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1__MASK 0x0c000000 |
| #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1__SHIFT 26 |
| static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1(uint32_t val) |
| { |
| return ((val) << A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1__MASK; |
| } |
| #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2__MASK 0x30000000 |
| #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2__SHIFT 28 |
| static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2(uint32_t val) |
| { |
| return ((val) << A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2__MASK; |
| } |
| #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3__MASK 0xc0000000 |
| #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3__SHIFT 30 |
| static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3(uint32_t val) |
| { |
| return ((val) << A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3__MASK; |
| } |
| |
| #define REG_A2XX_VGT_CURRENT_BIN_ID_MAX 0x00002203 |
| #define A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN__MASK 0x00000007 |
| #define A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN__SHIFT 0 |
| static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN(uint32_t val) |
| { |
| return ((val) << A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN__MASK; |
| } |
| #define A2XX_VGT_CURRENT_BIN_ID_MAX_ROW__MASK 0x00000038 |
| #define A2XX_VGT_CURRENT_BIN_ID_MAX_ROW__SHIFT 3 |
| static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MAX_ROW(uint32_t val) |
| { |
| return ((val) << A2XX_VGT_CURRENT_BIN_ID_MAX_ROW__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MAX_ROW__MASK; |
| } |
| #define A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK__MASK 0x000001c0 |
| #define A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK__SHIFT 6 |
| static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK(uint32_t val) |
| { |
| return ((val) << A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK__MASK; |
| } |
| |
| #define REG_A2XX_PA_CL_CLIP_CNTL 0x00002204 |
| #define A2XX_PA_CL_CLIP_CNTL_CLIP_DISABLE 0x00010000 |
| #define A2XX_PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA 0x00040000 |
| #define A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF__MASK 0x00080000 |
| #define A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF__SHIFT 19 |
| static inline uint32_t A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF(enum a2xx_dx_clip_space val) |
| { |
| return ((val) << A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF__SHIFT) & A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF__MASK; |
| } |
| #define A2XX_PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT 0x00100000 |
| #define A2XX_PA_CL_CLIP_CNTL_VTX_KILL_OR 0x00200000 |
| #define A2XX_PA_CL_CLIP_CNTL_XY_NAN_RETAIN 0x00400000 |
| #define A2XX_PA_CL_CLIP_CNTL_Z_NAN_RETAIN 0x00800000 |
| #define A2XX_PA_CL_CLIP_CNTL_W_NAN_RETAIN 0x01000000 |
| |
| #define REG_A2XX_PA_SU_SC_MODE_CNTL 0x00002205 |
| #define A2XX_PA_SU_SC_MODE_CNTL_CULL_FRONT 0x00000001 |
| #define A2XX_PA_SU_SC_MODE_CNTL_CULL_BACK 0x00000002 |
| #define A2XX_PA_SU_SC_MODE_CNTL_FACE 0x00000004 |
| #define A2XX_PA_SU_SC_MODE_CNTL_POLYMODE__MASK 0x00000018 |
| #define A2XX_PA_SU_SC_MODE_CNTL_POLYMODE__SHIFT 3 |
| static inline uint32_t A2XX_PA_SU_SC_MODE_CNTL_POLYMODE(enum a2xx_pa_su_sc_polymode val) |
| { |
| return ((val) << A2XX_PA_SU_SC_MODE_CNTL_POLYMODE__SHIFT) & A2XX_PA_SU_SC_MODE_CNTL_POLYMODE__MASK; |
| } |
| #define A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE__MASK 0x000000e0 |
| #define A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE__SHIFT 5 |
| static inline uint32_t A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE(enum adreno_pa_su_sc_draw val) |
| { |
| return ((val) << A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE__SHIFT) & A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE__MASK; |
| } |
| #define A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE__MASK 0x00000700 |
| #define A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE__SHIFT 8 |
| static inline uint32_t A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE(enum adreno_pa_su_sc_draw val) |
| { |
| return ((val) << A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE__SHIFT) & A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE__MASK; |
| } |
| #define A2XX_PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE 0x00000800 |
| #define A2XX_PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE 0x00001000 |
| #define A2XX_PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE 0x00002000 |
| #define A2XX_PA_SU_SC_MODE_CNTL_MSAA_ENABLE 0x00008000 |
| #define A2XX_PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE 0x00010000 |
| #define A2XX_PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE 0x00040000 |
| #define A2XX_PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST 0x00080000 |
| #define A2XX_PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS 0x00100000 |
| #define A2XX_PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA 0x00200000 |
| #define A2XX_PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE 0x00800000 |
| #define A2XX_PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI 0x02000000 |
| #define A2XX_PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE 0x04000000 |
| #define A2XX_PA_SU_SC_MODE_CNTL_CLAMPED_FACENESS 0x10000000 |
| #define A2XX_PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS 0x20000000 |
| #define A2XX_PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE 0x40000000 |
| #define A2XX_PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE 0x80000000 |
| |
| #define REG_A2XX_PA_CL_VTE_CNTL 0x00002206 |
| #define A2XX_PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA 0x00000001 |
| #define A2XX_PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA 0x00000002 |
| #define A2XX_PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA 0x00000004 |
| #define A2XX_PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA 0x00000008 |
| #define A2XX_PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA 0x00000010 |
| #define A2XX_PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA 0x00000020 |
| #define A2XX_PA_CL_VTE_CNTL_VTX_XY_FMT 0x00000100 |
| #define A2XX_PA_CL_VTE_CNTL_VTX_Z_FMT 0x00000200 |
| #define A2XX_PA_CL_VTE_CNTL_VTX_W0_FMT 0x00000400 |
| #define A2XX_PA_CL_VTE_CNTL_PERFCOUNTER_REF 0x00000800 |
| |
| #define REG_A2XX_VGT_CURRENT_BIN_ID_MIN 0x00002207 |
| #define A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN__MASK 0x00000007 |
| #define A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN__SHIFT 0 |
| static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN(uint32_t val) |
| { |
| return ((val) << A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN__MASK; |
| } |
| #define A2XX_VGT_CURRENT_BIN_ID_MIN_ROW__MASK 0x00000038 |
| #define A2XX_VGT_CURRENT_BIN_ID_MIN_ROW__SHIFT 3 |
| static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MIN_ROW(uint32_t val) |
| { |
| return ((val) << A2XX_VGT_CURRENT_BIN_ID_MIN_ROW__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MIN_ROW__MASK; |
| } |
| #define A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK__MASK 0x000001c0 |
| #define A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK__SHIFT 6 |
| static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK(uint32_t val) |
| { |
| return ((val) << A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK__MASK; |
| } |
| |
| #define REG_A2XX_RB_MODECONTROL 0x00002208 |
| #define A2XX_RB_MODECONTROL_EDRAM_MODE__MASK 0x00000007 |
| #define A2XX_RB_MODECONTROL_EDRAM_MODE__SHIFT 0 |
| static inline uint32_t A2XX_RB_MODECONTROL_EDRAM_MODE(enum a2xx_rb_edram_mode val) |
| { |
| return ((val) << A2XX_RB_MODECONTROL_EDRAM_MODE__SHIFT) & A2XX_RB_MODECONTROL_EDRAM_MODE__MASK; |
| } |
| |
| #define REG_A2XX_A220_RB_LRZ_VSC_CONTROL 0x00002209 |
| |
| #define REG_A2XX_RB_SAMPLE_POS 0x0000220a |
| |
| #define REG_A2XX_CLEAR_COLOR 0x0000220b |
| #define A2XX_CLEAR_COLOR_RED__MASK 0x000000ff |
| #define A2XX_CLEAR_COLOR_RED__SHIFT 0 |
| static inline uint32_t A2XX_CLEAR_COLOR_RED(uint32_t val) |
| { |
| return ((val) << A2XX_CLEAR_COLOR_RED__SHIFT) & A2XX_CLEAR_COLOR_RED__MASK; |
| } |
| #define A2XX_CLEAR_COLOR_GREEN__MASK 0x0000ff00 |
| #define A2XX_CLEAR_COLOR_GREEN__SHIFT 8 |
| static inline uint32_t A2XX_CLEAR_COLOR_GREEN(uint32_t val) |
| { |
| return ((val) << A2XX_CLEAR_COLOR_GREEN__SHIFT) & A2XX_CLEAR_COLOR_GREEN__MASK; |
| } |
| #define A2XX_CLEAR_COLOR_BLUE__MASK 0x00ff0000 |
| #define A2XX_CLEAR_COLOR_BLUE__SHIFT 16 |
| static inline uint32_t A2XX_CLEAR_COLOR_BLUE(uint32_t val) |
| { |
| return ((val) << A2XX_CLEAR_COLOR_BLUE__SHIFT) & A2XX_CLEAR_COLOR_BLUE__MASK; |
| } |
| #define A2XX_CLEAR_COLOR_ALPHA__MASK 0xff000000 |
| #define A2XX_CLEAR_COLOR_ALPHA__SHIFT 24 |
| static inline uint32_t A2XX_CLEAR_COLOR_ALPHA(uint32_t val) |
| { |
| return ((val) << A2XX_CLEAR_COLOR_ALPHA__SHIFT) & A2XX_CLEAR_COLOR_ALPHA__MASK; |
| } |
| |
| #define REG_A2XX_A220_GRAS_CONTROL 0x00002210 |
| |
| #define REG_A2XX_PA_SU_POINT_SIZE 0x00002280 |
| #define A2XX_PA_SU_POINT_SIZE_HEIGHT__MASK 0x0000ffff |
| #define A2XX_PA_SU_POINT_SIZE_HEIGHT__SHIFT 0 |
| static inline uint32_t A2XX_PA_SU_POINT_SIZE_HEIGHT(float val) |
| { |
| return ((((uint32_t)(val * 16.0))) << A2XX_PA_SU_POINT_SIZE_HEIGHT__SHIFT) & A2XX_PA_SU_POINT_SIZE_HEIGHT__MASK; |
| } |
| #define A2XX_PA_SU_POINT_SIZE_WIDTH__MASK 0xffff0000 |
| #define A2XX_PA_SU_POINT_SIZE_WIDTH__SHIFT 16 |
| static inline uint32_t A2XX_PA_SU_POINT_SIZE_WIDTH(float val) |
| { |
| return ((((uint32_t)(val * 16.0))) << A2XX_PA_SU_POINT_SIZE_WIDTH__SHIFT) & A2XX_PA_SU_POINT_SIZE_WIDTH__MASK; |
| } |
| |
| #define REG_A2XX_PA_SU_POINT_MINMAX 0x00002281 |
| #define A2XX_PA_SU_POINT_MINMAX_MIN__MASK 0x0000ffff |
| #define A2XX_PA_SU_POINT_MINMAX_MIN__SHIFT 0 |
| static inline uint32_t A2XX_PA_SU_POINT_MINMAX_MIN(float val) |
| { |
| return ((((uint32_t)(val * 16.0))) << A2XX_PA_SU_POINT_MINMAX_MIN__SHIFT) & A2XX_PA_SU_POINT_MINMAX_MIN__MASK; |
| } |
| #define A2XX_PA_SU_POINT_MINMAX_MAX__MASK 0xffff0000 |
| #define A2XX_PA_SU_POINT_MINMAX_MAX__SHIFT 16 |
| static inline uint32_t A2XX_PA_SU_POINT_MINMAX_MAX(float val) |
| { |
| return ((((uint32_t)(val * 16.0))) << A2XX_PA_SU_POINT_MINMAX_MAX__SHIFT) & A2XX_PA_SU_POINT_MINMAX_MAX__MASK; |
| } |
| |
| #define REG_A2XX_PA_SU_LINE_CNTL 0x00002282 |
| #define A2XX_PA_SU_LINE_CNTL_WIDTH__MASK 0x0000ffff |
| #define A2XX_PA_SU_LINE_CNTL_WIDTH__SHIFT 0 |
| static inline uint32_t A2XX_PA_SU_LINE_CNTL_WIDTH(float val) |
| { |
| return ((((uint32_t)(val * 16.0))) << A2XX_PA_SU_LINE_CNTL_WIDTH__SHIFT) & A2XX_PA_SU_LINE_CNTL_WIDTH__MASK; |
| } |
| |
| #define REG_A2XX_PA_SC_LINE_STIPPLE 0x00002283 |
| #define A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN__MASK 0x0000ffff |
| #define A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN__SHIFT 0 |
| static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN(uint32_t val) |
| { |
| return ((val) << A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN__SHIFT) & A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN__MASK; |
| } |
| #define A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT__MASK 0x00ff0000 |
| #define A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT__SHIFT 16 |
| static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT(uint32_t val) |
| { |
| return ((val) << A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT__SHIFT) & A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT__MASK; |
| } |
| #define A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER__MASK 0x10000000 |
| #define A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER__SHIFT 28 |
| static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER(enum a2xx_pa_sc_pattern_bit_order val) |
| { |
| return ((val) << A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER__SHIFT) & A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER__MASK; |
| } |
| #define A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL__MASK 0x60000000 |
| #define A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL__SHIFT 29 |
| static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL(enum a2xx_pa_sc_auto_reset_cntl val) |
| { |
| return ((val) << A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL__SHIFT) & A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL__MASK; |
| } |
| |
| #define REG_A2XX_PA_SC_VIZ_QUERY 0x00002293 |
| #define A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ENA 0x00000001 |
| #define A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ID__MASK 0x0000007e |
| #define A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ID__SHIFT 1 |
| static inline uint32_t A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ID(uint32_t val) |
| { |
| return ((val) << A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ID__SHIFT) & A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ID__MASK; |
| } |
| #define A2XX_PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z 0x00000100 |
| |
| #define REG_A2XX_VGT_ENHANCE 0x00002294 |
| |
| #define REG_A2XX_PA_SC_LINE_CNTL 0x00002300 |
| #define A2XX_PA_SC_LINE_CNTL_BRES_CNTL__MASK 0x0000ffff |
| #define A2XX_PA_SC_LINE_CNTL_BRES_CNTL__SHIFT 0 |
| static inline uint32_t A2XX_PA_SC_LINE_CNTL_BRES_CNTL(uint32_t val) |
| { |
| return ((val) << A2XX_PA_SC_LINE_CNTL_BRES_CNTL__SHIFT) & A2XX_PA_SC_LINE_CNTL_BRES_CNTL__MASK; |
| } |
| #define A2XX_PA_SC_LINE_CNTL_USE_BRES_CNTL 0x00000100 |
| #define A2XX_PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH 0x00000200 |
| #define A2XX_PA_SC_LINE_CNTL_LAST_PIXEL 0x00000400 |
| |
| #define REG_A2XX_PA_SC_AA_CONFIG 0x00002301 |
| #define A2XX_PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES__MASK 0x00000007 |
| #define A2XX_PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES__SHIFT 0 |
| static inline uint32_t A2XX_PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES(uint32_t val) |
| { |
| return ((val) << A2XX_PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES__SHIFT) & A2XX_PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES__MASK; |
| } |
| #define A2XX_PA_SC_AA_CONFIG_MAX_SAMPLE_DIST__MASK 0x0001e000 |
| #define A2XX_PA_SC_AA_CONFIG_MAX_SAMPLE_DIST__SHIFT 13 |
| static inline uint32_t A2XX_PA_SC_AA_CONFIG_MAX_SAMPLE_DIST(uint32_t val) |
| { |
| return ((val) << A2XX_PA_SC_AA_CONFIG_MAX_SAMPLE_DIST__SHIFT) & A2XX_PA_SC_AA_CONFIG_MAX_SAMPLE_DIST__MASK; |
| } |
| |
| #define REG_A2XX_PA_SU_VTX_CNTL 0x00002302 |
| #define A2XX_PA_SU_VTX_CNTL_PIX_CENTER__MASK 0x00000001 |
| #define A2XX_PA_SU_VTX_CNTL_PIX_CENTER__SHIFT 0 |
| static inline uint32_t A2XX_PA_SU_VTX_CNTL_PIX_CENTER(enum a2xx_pa_pixcenter val) |
| { |
| return ((val) << A2XX_PA_SU_VTX_CNTL_PIX_CENTER__SHIFT) & A2XX_PA_SU_VTX_CNTL_PIX_CENTER__MASK; |
| } |
| #define A2XX_PA_SU_VTX_CNTL_ROUND_MODE__MASK 0x00000006 |
| #define A2XX_PA_SU_VTX_CNTL_ROUND_MODE__SHIFT 1 |
| static inline uint32_t A2XX_PA_SU_VTX_CNTL_ROUND_MODE(enum a2xx_pa_roundmode val) |
| { |
| return ((val) << A2XX_PA_SU_VTX_CNTL_ROUND_MODE__SHIFT) & A2XX_PA_SU_VTX_CNTL_ROUND_MODE__MASK; |
| } |
| #define A2XX_PA_SU_VTX_CNTL_QUANT_MODE__MASK 0x00000380 |
| #define A2XX_PA_SU_VTX_CNTL_QUANT_MODE__SHIFT 7 |
| static inline uint32_t A2XX_PA_SU_VTX_CNTL_QUANT_MODE(enum a2xx_pa_quantmode val) |
| { |
| return ((val) << A2XX_PA_SU_VTX_CNTL_QUANT_MODE__SHIFT) & A2XX_PA_SU_VTX_CNTL_QUANT_MODE__MASK; |
| } |
| |
| #define REG_A2XX_PA_CL_GB_VERT_CLIP_ADJ 0x00002303 |
| #define A2XX_PA_CL_GB_VERT_CLIP_ADJ__MASK 0xffffffff |
| #define A2XX_PA_CL_GB_VERT_CLIP_ADJ__SHIFT 0 |
| static inline uint32_t A2XX_PA_CL_GB_VERT_CLIP_ADJ(float val) |
| { |
| return ((fui(val)) << A2XX_PA_CL_GB_VERT_CLIP_ADJ__SHIFT) & A2XX_PA_CL_GB_VERT_CLIP_ADJ__MASK; |
| } |
| |
| #define REG_A2XX_PA_CL_GB_VERT_DISC_ADJ 0x00002304 |
| #define A2XX_PA_CL_GB_VERT_DISC_ADJ__MASK 0xffffffff |
| #define A2XX_PA_CL_GB_VERT_DISC_ADJ__SHIFT 0 |
| static inline uint32_t A2XX_PA_CL_GB_VERT_DISC_ADJ(float val) |
| { |
| return ((fui(val)) << A2XX_PA_CL_GB_VERT_DISC_ADJ__SHIFT) & A2XX_PA_CL_GB_VERT_DISC_ADJ__MASK; |
| } |
| |
| #define REG_A2XX_PA_CL_GB_HORZ_CLIP_ADJ 0x00002305 |
| #define A2XX_PA_CL_GB_HORZ_CLIP_ADJ__MASK 0xffffffff |
| #define A2XX_PA_CL_GB_HORZ_CLIP_ADJ__SHIFT 0 |
| static inline uint32_t A2XX_PA_CL_GB_HORZ_CLIP_ADJ(float val) |
| { |
| return ((fui(val)) << A2XX_PA_CL_GB_HORZ_CLIP_ADJ__SHIFT) & A2XX_PA_CL_GB_HORZ_CLIP_ADJ__MASK; |
| } |
| |
| #define REG_A2XX_PA_CL_GB_HORZ_DISC_ADJ 0x00002306 |
| #define A2XX_PA_CL_GB_HORZ_DISC_ADJ__MASK 0xffffffff |
| #define A2XX_PA_CL_GB_HORZ_DISC_ADJ__SHIFT 0 |
| static inline uint32_t A2XX_PA_CL_GB_HORZ_DISC_ADJ(float val) |
| { |
| return ((fui(val)) << A2XX_PA_CL_GB_HORZ_DISC_ADJ__SHIFT) & A2XX_PA_CL_GB_HORZ_DISC_ADJ__MASK; |
| } |
| |
| #define REG_A2XX_SQ_VS_CONST 0x00002307 |
| #define A2XX_SQ_VS_CONST_BASE__MASK 0x000001ff |
| #define A2XX_SQ_VS_CONST_BASE__SHIFT 0 |
| static inline uint32_t A2XX_SQ_VS_CONST_BASE(uint32_t val) |
| { |
| return ((val) << A2XX_SQ_VS_CONST_BASE__SHIFT) & A2XX_SQ_VS_CONST_BASE__MASK; |
| } |
| #define A2XX_SQ_VS_CONST_SIZE__MASK 0x001ff000 |
| #define A2XX_SQ_VS_CONST_SIZE__SHIFT 12 |
| static inline uint32_t A2XX_SQ_VS_CONST_SIZE(uint32_t val) |
| { |
| return ((val) << A2XX_SQ_VS_CONST_SIZE__SHIFT) & A2XX_SQ_VS_CONST_SIZE__MASK; |
| } |
| |
| #define REG_A2XX_SQ_PS_CONST 0x00002308 |
| #define A2XX_SQ_PS_CONST_BASE__MASK 0x000001ff |
| #define A2XX_SQ_PS_CONST_BASE__SHIFT 0 |
| static inline uint32_t A2XX_SQ_PS_CONST_BASE(uint32_t val) |
| { |
| return ((val) << A2XX_SQ_PS_CONST_BASE__SHIFT) & A2XX_SQ_PS_CONST_BASE__MASK; |
| } |
| #define A2XX_SQ_PS_CONST_SIZE__MASK 0x001ff000 |
| #define A2XX_SQ_PS_CONST_SIZE__SHIFT 12 |
| static inline uint32_t A2XX_SQ_PS_CONST_SIZE(uint32_t val) |
| { |
| return ((val) << A2XX_SQ_PS_CONST_SIZE__SHIFT) & A2XX_SQ_PS_CONST_SIZE__MASK; |
| } |
| |
| #define REG_A2XX_SQ_DEBUG_MISC_0 0x00002309 |
| |
| #define REG_A2XX_SQ_DEBUG_MISC_1 0x0000230a |
| |
| #define REG_A2XX_PA_SC_AA_MASK 0x00002312 |
| |
| #define REG_A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL 0x00002316 |
| #define A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH__MASK 0x00000007 |
| #define A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH__SHIFT 0 |
| static inline uint32_t A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH(uint32_t val) |
| { |
| return ((val) << A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH__SHIFT) & A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH__MASK; |
| } |
| |
| #define REG_A2XX_VGT_OUT_DEALLOC_CNTL 0x00002317 |
| #define A2XX_VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST__MASK 0x00000003 |
| #define A2XX_VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST__SHIFT 0 |
| static inline uint32_t A2XX_VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST(uint32_t val) |
| { |
| return ((val) << A2XX_VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST__SHIFT) & A2XX_VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST__MASK; |
| } |
| |
| #define REG_A2XX_RB_COPY_CONTROL 0x00002318 |
| #define A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT__MASK 0x00000007 |
| #define A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT__SHIFT 0 |
| static inline uint32_t A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT(enum a2xx_rb_copy_sample_select val) |
| { |
| return ((val) << A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT__SHIFT) & A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT__MASK; |
| } |
| #define A2XX_RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE 0x00000008 |
| #define A2XX_RB_COPY_CONTROL_CLEAR_MASK__MASK 0x000000f0 |
| #define A2XX_RB_COPY_CONTROL_CLEAR_MASK__SHIFT 4 |
| static inline uint32_t A2XX_RB_COPY_CONTROL_CLEAR_MASK(uint32_t val) |
| { |
| return ((val) << A2XX_RB_COPY_CONTROL_CLEAR_MASK__SHIFT) & A2XX_RB_COPY_CONTROL_CLEAR_MASK__MASK; |
| } |
| |
| #define REG_A2XX_RB_COPY_DEST_BASE 0x00002319 |
| |
| #define REG_A2XX_RB_COPY_DEST_PITCH 0x0000231a |
| #define A2XX_RB_COPY_DEST_PITCH__MASK 0xffffffff |
| #define A2XX_RB_COPY_DEST_PITCH__SHIFT 0 |
| static inline uint32_t A2XX_RB_COPY_DEST_PITCH(uint32_t val) |
| { |
| return ((val >> 5) << A2XX_RB_COPY_DEST_PITCH__SHIFT) & A2XX_RB_COPY_DEST_PITCH__MASK; |
| } |
| |
| #define REG_A2XX_RB_COPY_DEST_INFO 0x0000231b |
| #define A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN__MASK 0x00000007 |
| #define A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN__SHIFT 0 |
| static inline uint32_t A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN(enum adreno_rb_surface_endian val) |
| { |
| return ((val) << A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN__SHIFT) & A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN__MASK; |
| } |
| #define A2XX_RB_COPY_DEST_INFO_LINEAR 0x00000008 |
| #define A2XX_RB_COPY_DEST_INFO_FORMAT__MASK 0x000000f0 |
| #define A2XX_RB_COPY_DEST_INFO_FORMAT__SHIFT 4 |
| static inline uint32_t A2XX_RB_COPY_DEST_INFO_FORMAT(enum a2xx_colorformatx val) |
| { |
| return ((val) << A2XX_RB_COPY_DEST_INFO_FORMAT__SHIFT) & A2XX_RB_COPY_DEST_INFO_FORMAT__MASK; |
| } |
| #define A2XX_RB_COPY_DEST_INFO_SWAP__MASK 0x00000300 |
| #define A2XX_RB_COPY_DEST_INFO_SWAP__SHIFT 8 |
| static inline uint32_t A2XX_RB_COPY_DEST_INFO_SWAP(uint32_t val) |
| { |
| return ((val) << A2XX_RB_COPY_DEST_INFO_SWAP__SHIFT) & A2XX_RB_COPY_DEST_INFO_SWAP__MASK; |
| } |
| #define A2XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK 0x00000c00 |
| #define A2XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT 10 |
| static inline uint32_t A2XX_RB_COPY_DEST_INFO_DITHER_MODE(enum adreno_rb_dither_mode val) |
| { |
| return ((val) << A2XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT) & A2XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK; |
| } |
| #define A2XX_RB_COPY_DEST_INFO_DITHER_TYPE__MASK 0x00003000 |
| #define A2XX_RB_COPY_DEST_INFO_DITHER_TYPE__SHIFT 12 |
| static inline uint32_t A2XX_RB_COPY_DEST_INFO_DITHER_TYPE(enum a2xx_rb_dither_type val) |
| { |
| return ((val) << A2XX_RB_COPY_DEST_INFO_DITHER_TYPE__SHIFT) & A2XX_RB_COPY_DEST_INFO_DITHER_TYPE__MASK; |
| } |
| #define A2XX_RB_COPY_DEST_INFO_WRITE_RED 0x00004000 |
| #define A2XX_RB_COPY_DEST_INFO_WRITE_GREEN 0x00008000 |
| #define A2XX_RB_COPY_DEST_INFO_WRITE_BLUE 0x00010000 |
| #define A2XX_RB_COPY_DEST_INFO_WRITE_ALPHA 0x00020000 |
| |
| #define REG_A2XX_RB_COPY_DEST_OFFSET 0x0000231c |
| #define A2XX_RB_COPY_DEST_OFFSET_X__MASK 0x00001fff |
| #define A2XX_RB_COPY_DEST_OFFSET_X__SHIFT 0 |
| static inline uint32_t A2XX_RB_COPY_DEST_OFFSET_X(uint32_t val) |
| { |
| return ((val) << A2XX_RB_COPY_DEST_OFFSET_X__SHIFT) & A2XX_RB_COPY_DEST_OFFSET_X__MASK; |
| } |
| #define A2XX_RB_COPY_DEST_OFFSET_Y__MASK 0x03ffe000 |
| #define A2XX_RB_COPY_DEST_OFFSET_Y__SHIFT 13 |
| static inline uint32_t A2XX_RB_COPY_DEST_OFFSET_Y(uint32_t val) |
| { |
| return ((val) << A2XX_RB_COPY_DEST_OFFSET_Y__SHIFT) & A2XX_RB_COPY_DEST_OFFSET_Y__MASK; |
| } |
| |
| #define REG_A2XX_RB_DEPTH_CLEAR 0x0000231d |
| |
| #define REG_A2XX_RB_SAMPLE_COUNT_CTL 0x00002324 |
| |
| #define REG_A2XX_RB_COLOR_DEST_MASK 0x00002326 |
| |
| #define REG_A2XX_A225_GRAS_UCP0X 0x00002340 |
| |
| #define REG_A2XX_A225_GRAS_UCP5W 0x00002357 |
| |
| #define REG_A2XX_A225_GRAS_UCP_ENABLED 0x00002360 |
| |
| #define REG_A2XX_PA_SU_POLY_OFFSET_FRONT_SCALE 0x00002380 |
| |
| #define REG_A2XX_PA_SU_POLY_OFFSET_FRONT_OFFSET 0x00002381 |
| |
| #define REG_A2XX_PA_SU_POLY_OFFSET_BACK_SCALE 0x00002382 |
| |
| #define REG_A2XX_PA_SU_POLY_OFFSET_BACK_OFFSET 0x00002383 |
| |
| #define REG_A2XX_SQ_CONSTANT_0 0x00004000 |
| |
| #define REG_A2XX_SQ_FETCH_0 0x00004800 |
| |
| #define REG_A2XX_SQ_CF_BOOLEANS 0x00004900 |
| |
| #define REG_A2XX_SQ_CF_LOOP 0x00004908 |
| |
| #define REG_A2XX_COHER_SIZE_PM4 0x00000a29 |
| |
| #define REG_A2XX_COHER_BASE_PM4 0x00000a2a |
| |
| #define REG_A2XX_COHER_STATUS_PM4 0x00000a2b |
| |
| #define REG_A2XX_PA_SU_PERFCOUNTER0_SELECT 0x00000c88 |
| |
| #define REG_A2XX_PA_SU_PERFCOUNTER1_SELECT 0x00000c89 |
| |
| #define REG_A2XX_PA_SU_PERFCOUNTER2_SELECT 0x00000c8a |
| |
| #define REG_A2XX_PA_SU_PERFCOUNTER3_SELECT 0x00000c8b |
| |
| #define REG_A2XX_PA_SU_PERFCOUNTER0_LOW 0x00000c8c |
| |
| #define REG_A2XX_PA_SU_PERFCOUNTER0_HI 0x00000c8d |
| |
| #define REG_A2XX_PA_SU_PERFCOUNTER1_LOW 0x00000c8e |
| |
| #define REG_A2XX_PA_SU_PERFCOUNTER1_HI 0x00000c8f |
| |
| #define REG_A2XX_PA_SU_PERFCOUNTER2_LOW 0x00000c90 |
| |
| #define REG_A2XX_PA_SU_PERFCOUNTER2_HI 0x00000c91 |
| |
| #define REG_A2XX_PA_SU_PERFCOUNTER3_LOW 0x00000c92 |
| |
| #define REG_A2XX_PA_SU_PERFCOUNTER3_HI 0x00000c93 |
| |
| #define REG_A2XX_PA_SC_PERFCOUNTER0_SELECT 0x00000c98 |
| |
| #define REG_A2XX_PA_SC_PERFCOUNTER0_LOW 0x00000c99 |
| |
| #define REG_A2XX_PA_SC_PERFCOUNTER0_HI 0x00000c9a |
| |
| #define REG_A2XX_VGT_PERFCOUNTER0_SELECT 0x00000c48 |
| |
| #define REG_A2XX_VGT_PERFCOUNTER1_SELECT 0x00000c49 |
| |
| #define REG_A2XX_VGT_PERFCOUNTER2_SELECT 0x00000c4a |
| |
| #define REG_A2XX_VGT_PERFCOUNTER3_SELECT 0x00000c4b |
| |
| #define REG_A2XX_VGT_PERFCOUNTER0_LOW 0x00000c4c |
| |
| #define REG_A2XX_VGT_PERFCOUNTER1_LOW 0x00000c4e |
| |
| #define REG_A2XX_VGT_PERFCOUNTER2_LOW 0x00000c50 |
| |
| #define REG_A2XX_VGT_PERFCOUNTER3_LOW 0x00000c52 |
| |
| #define REG_A2XX_VGT_PERFCOUNTER0_HI 0x00000c4d |
| |
| #define REG_A2XX_VGT_PERFCOUNTER1_HI 0x00000c4f |
| |
| #define REG_A2XX_VGT_PERFCOUNTER2_HI 0x00000c51 |
| |
| #define REG_A2XX_VGT_PERFCOUNTER3_HI 0x00000c53 |
| |
| #define REG_A2XX_TCR_PERFCOUNTER0_SELECT 0x00000e05 |
| |
| #define REG_A2XX_TCR_PERFCOUNTER1_SELECT 0x00000e08 |
| |
| #define REG_A2XX_TCR_PERFCOUNTER0_HI 0x00000e06 |
| |
| #define REG_A2XX_TCR_PERFCOUNTER1_HI 0x00000e09 |
| |
| #define REG_A2XX_TCR_PERFCOUNTER0_LOW 0x00000e07 |
| |
| #define REG_A2XX_TCR_PERFCOUNTER1_LOW 0x00000e0a |
| |
| #define REG_A2XX_TP0_PERFCOUNTER0_SELECT 0x00000e1f |
| |
| #define REG_A2XX_TP0_PERFCOUNTER0_HI 0x00000e20 |
| |
| #define REG_A2XX_TP0_PERFCOUNTER0_LOW 0x00000e21 |
| |
| #define REG_A2XX_TP0_PERFCOUNTER1_SELECT 0x00000e22 |
| |
| #define REG_A2XX_TP0_PERFCOUNTER1_HI 0x00000e23 |
| |
| #define REG_A2XX_TP0_PERFCOUNTER1_LOW 0x00000e24 |
| |
| #define REG_A2XX_TCM_PERFCOUNTER0_SELECT 0x00000e54 |
| |
| #define REG_A2XX_TCM_PERFCOUNTER1_SELECT 0x00000e57 |
| |
| #define REG_A2XX_TCM_PERFCOUNTER0_HI 0x00000e55 |
| |
| #define REG_A2XX_TCM_PERFCOUNTER1_HI 0x00000e58 |
| |
| #define REG_A2XX_TCM_PERFCOUNTER0_LOW 0x00000e56 |
| |
| #define REG_A2XX_TCM_PERFCOUNTER1_LOW 0x00000e59 |
| |
| #define REG_A2XX_TCF_PERFCOUNTER0_SELECT 0x00000e5a |
| |
| #define REG_A2XX_TCF_PERFCOUNTER1_SELECT 0x00000e5d |
| |
| #define REG_A2XX_TCF_PERFCOUNTER2_SELECT 0x00000e60 |
| |
| #define REG_A2XX_TCF_PERFCOUNTER3_SELECT 0x00000e63 |
| |
| #define REG_A2XX_TCF_PERFCOUNTER4_SELECT 0x00000e66 |
| |
| #define REG_A2XX_TCF_PERFCOUNTER5_SELECT 0x00000e69 |
| |
| #define REG_A2XX_TCF_PERFCOUNTER6_SELECT 0x00000e6c |
| |
| #define REG_A2XX_TCF_PERFCOUNTER7_SELECT 0x00000e6f |
| |
| #define REG_A2XX_TCF_PERFCOUNTER8_SELECT 0x00000e72 |
| |
| #define REG_A2XX_TCF_PERFCOUNTER9_SELECT 0x00000e75 |
| |
| #define REG_A2XX_TCF_PERFCOUNTER10_SELECT 0x00000e78 |
| |
| #define REG_A2XX_TCF_PERFCOUNTER11_SELECT 0x00000e7b |
| |
| #define REG_A2XX_TCF_PERFCOUNTER0_HI 0x00000e5b |
| |
| #define REG_A2XX_TCF_PERFCOUNTER1_HI 0x00000e5e |
| |
| #define REG_A2XX_TCF_PERFCOUNTER2_HI 0x00000e61 |
| |
| #define REG_A2XX_TCF_PERFCOUNTER3_HI 0x00000e64 |
| |
| #define REG_A2XX_TCF_PERFCOUNTER4_HI 0x00000e67 |
| |
| #define REG_A2XX_TCF_PERFCOUNTER5_HI 0x00000e6a |
| |
| #define REG_A2XX_TCF_PERFCOUNTER6_HI 0x00000e6d |
| |
| #define REG_A2XX_TCF_PERFCOUNTER7_HI 0x00000e70 |
| |
| #define REG_A2XX_TCF_PERFCOUNTER8_HI 0x00000e73 |
| |
| #define REG_A2XX_TCF_PERFCOUNTER9_HI 0x00000e76 |
| |
| #define REG_A2XX_TCF_PERFCOUNTER10_HI 0x00000e79 |
| |
| #define REG_A2XX_TCF_PERFCOUNTER11_HI 0x00000e7c |
| |
| #define REG_A2XX_TCF_PERFCOUNTER0_LOW 0x00000e5c |
| |
| #define REG_A2XX_TCF_PERFCOUNTER1_LOW 0x00000e5f |
| |
| #define REG_A2XX_TCF_PERFCOUNTER2_LOW 0x00000e62 |
| |
| #define REG_A2XX_TCF_PERFCOUNTER3_LOW 0x00000e65 |
| |
| #define REG_A2XX_TCF_PERFCOUNTER4_LOW 0x00000e68 |
| |
| #define REG_A2XX_TCF_PERFCOUNTER5_LOW 0x00000e6b |
| |
| #define REG_A2XX_TCF_PERFCOUNTER6_LOW 0x00000e6e |
| |
| #define REG_A2XX_TCF_PERFCOUNTER7_LOW 0x00000e71 |
| |
| #define REG_A2XX_TCF_PERFCOUNTER8_LOW 0x00000e74 |
| |
| #define REG_A2XX_TCF_PERFCOUNTER9_LOW 0x00000e77 |
| |
| #define REG_A2XX_TCF_PERFCOUNTER10_LOW 0x00000e7a |
| |
| #define REG_A2XX_TCF_PERFCOUNTER11_LOW 0x00000e7d |
| |
| #define REG_A2XX_SQ_PERFCOUNTER0_SELECT 0x00000dc8 |
| |
| #define REG_A2XX_SQ_PERFCOUNTER1_SELECT 0x00000dc9 |
| |
| #define REG_A2XX_SQ_PERFCOUNTER2_SELECT 0x00000dca |
| |
| #define REG_A2XX_SQ_PERFCOUNTER3_SELECT 0x00000dcb |
| |
| #define REG_A2XX_SQ_PERFCOUNTER0_LOW 0x00000dcc |
| |
| #define REG_A2XX_SQ_PERFCOUNTER0_HI 0x00000dcd |
| |
| #define REG_A2XX_SQ_PERFCOUNTER1_LOW 0x00000dce |
| |
| #define REG_A2XX_SQ_PERFCOUNTER1_HI 0x00000dcf |
| |
| #define REG_A2XX_SQ_PERFCOUNTER2_LOW 0x00000dd0 |
| |
| #define REG_A2XX_SQ_PERFCOUNTER2_HI 0x00000dd1 |
| |
| #define REG_A2XX_SQ_PERFCOUNTER3_LOW 0x00000dd2 |
| |
| #define REG_A2XX_SQ_PERFCOUNTER3_HI 0x00000dd3 |
| |
| #define REG_A2XX_SX_PERFCOUNTER0_SELECT 0x00000dd4 |
| |
| #define REG_A2XX_SX_PERFCOUNTER0_LOW 0x00000dd8 |
| |
| #define REG_A2XX_SX_PERFCOUNTER0_HI 0x00000dd9 |
| |
| #define REG_A2XX_MH_PERFCOUNTER0_SELECT 0x00000a46 |
| |
| #define REG_A2XX_MH_PERFCOUNTER1_SELECT 0x00000a4a |
| |
| #define REG_A2XX_MH_PERFCOUNTER0_CONFIG 0x00000a47 |
| |
| #define REG_A2XX_MH_PERFCOUNTER1_CONFIG 0x00000a4b |
| |
| #define REG_A2XX_MH_PERFCOUNTER0_LOW 0x00000a48 |
| |
| #define REG_A2XX_MH_PERFCOUNTER1_LOW 0x00000a4c |
| |
| #define REG_A2XX_MH_PERFCOUNTER0_HI 0x00000a49 |
| |
| #define REG_A2XX_MH_PERFCOUNTER1_HI 0x00000a4d |
| |
| #define REG_A2XX_RB_PERFCOUNTER0_SELECT 0x00000f04 |
| |
| #define REG_A2XX_RB_PERFCOUNTER0_LOW 0x00000f08 |
| |
| #define REG_A2XX_RB_PERFCOUNTER0_HI 0x00000f09 |
| |
| #define REG_A2XX_SQ_TEX_0 0x00000000 |
| #define A2XX_SQ_TEX_0_TYPE__MASK 0x00000003 |
| #define A2XX_SQ_TEX_0_TYPE__SHIFT 0 |
| static inline uint32_t A2XX_SQ_TEX_0_TYPE(enum sq_tex_type val) |
| { |
| return ((val) << A2XX_SQ_TEX_0_TYPE__SHIFT) & A2XX_SQ_TEX_0_TYPE__MASK; |
| } |
| #define A2XX_SQ_TEX_0_SIGN_X__MASK 0x0000000c |
| #define A2XX_SQ_TEX_0_SIGN_X__SHIFT 2 |
| static inline uint32_t A2XX_SQ_TEX_0_SIGN_X(enum sq_tex_sign val) |
| { |
| return ((val) << A2XX_SQ_TEX_0_SIGN_X__SHIFT) & A2XX_SQ_TEX_0_SIGN_X__MASK; |
| } |
| #define A2XX_SQ_TEX_0_SIGN_Y__MASK 0x00000030 |
| #define A2XX_SQ_TEX_0_SIGN_Y__SHIFT 4 |
| static inline uint32_t A2XX_SQ_TEX_0_SIGN_Y(enum sq_tex_sign val) |
| { |
| return ((val) << A2XX_SQ_TEX_0_SIGN_Y__SHIFT) & A2XX_SQ_TEX_0_SIGN_Y__MASK; |
| } |
| #define A2XX_SQ_TEX_0_SIGN_Z__MASK 0x000000c0 |
| #define A2XX_SQ_TEX_0_SIGN_Z__SHIFT 6 |
| static inline uint32_t A2XX_SQ_TEX_0_SIGN_Z(enum sq_tex_sign val) |
| { |
| return ((val) << A2XX_SQ_TEX_0_SIGN_Z__SHIFT) & A2XX_SQ_TEX_0_SIGN_Z__MASK; |
| } |
| #define A2XX_SQ_TEX_0_SIGN_W__MASK 0x00000300 |
| #define A2XX_SQ_TEX_0_SIGN_W__SHIFT 8 |
| static inline uint32_t A2XX_SQ_TEX_0_SIGN_W(enum sq_tex_sign val) |
| { |
| return ((val) << A2XX_SQ_TEX_0_SIGN_W__SHIFT) & A2XX_SQ_TEX_0_SIGN_W__MASK; |
| } |
| #define A2XX_SQ_TEX_0_CLAMP_X__MASK 0x00001c00 |
| #define A2XX_SQ_TEX_0_CLAMP_X__SHIFT 10 |
| static inline uint32_t A2XX_SQ_TEX_0_CLAMP_X(enum sq_tex_clamp val) |
| { |
| return ((val) << A2XX_SQ_TEX_0_CLAMP_X__SHIFT) & A2XX_SQ_TEX_0_CLAMP_X__MASK; |
| } |
| #define A2XX_SQ_TEX_0_CLAMP_Y__MASK 0x0000e000 |
| #define A2XX_SQ_TEX_0_CLAMP_Y__SHIFT 13 |
| static inline uint32_t A2XX_SQ_TEX_0_CLAMP_Y(enum sq_tex_clamp val) |
| { |
| return ((val) << A2XX_SQ_TEX_0_CLAMP_Y__SHIFT) & A2XX_SQ_TEX_0_CLAMP_Y__MASK; |
| } |
| #define A2XX_SQ_TEX_0_CLAMP_Z__MASK 0x00070000 |
| #define A2XX_SQ_TEX_0_CLAMP_Z__SHIFT 16 |
| static inline uint32_t A2XX_SQ_TEX_0_CLAMP_Z(enum sq_tex_clamp val) |
| { |
| return ((val) << A2XX_SQ_TEX_0_CLAMP_Z__SHIFT) & A2XX_SQ_TEX_0_CLAMP_Z__MASK; |
| } |
| #define A2XX_SQ_TEX_0_PITCH__MASK 0x7fc00000 |
| #define A2XX_SQ_TEX_0_PITCH__SHIFT 22 |
| static inline uint32_t A2XX_SQ_TEX_0_PITCH(uint32_t val) |
| { |
| return ((val >> 5) << A2XX_SQ_TEX_0_PITCH__SHIFT) & A2XX_SQ_TEX_0_PITCH__MASK; |
| } |
| #define A2XX_SQ_TEX_0_TILED 0x80000000 |
| |
| #define REG_A2XX_SQ_TEX_1 0x00000001 |
| #define A2XX_SQ_TEX_1_FORMAT__MASK 0x0000003f |
| #define A2XX_SQ_TEX_1_FORMAT__SHIFT 0 |
| static inline uint32_t A2XX_SQ_TEX_1_FORMAT(enum a2xx_sq_surfaceformat val) |
| { |
| return ((val) << A2XX_SQ_TEX_1_FORMAT__SHIFT) & A2XX_SQ_TEX_1_FORMAT__MASK; |
| } |
| #define A2XX_SQ_TEX_1_ENDIANNESS__MASK 0x000000c0 |
| #define A2XX_SQ_TEX_1_ENDIANNESS__SHIFT 6 |
| static inline uint32_t A2XX_SQ_TEX_1_ENDIANNESS(enum sq_tex_endian val) |
| { |
| return ((val) << A2XX_SQ_TEX_1_ENDIANNESS__SHIFT) & A2XX_SQ_TEX_1_ENDIANNESS__MASK; |
| } |
| #define A2XX_SQ_TEX_1_REQUEST_SIZE__MASK 0x00000300 |
| #define A2XX_SQ_TEX_1_REQUEST_SIZE__SHIFT 8 |
| static inline uint32_t A2XX_SQ_TEX_1_REQUEST_SIZE(uint32_t val) |
| { |
| return ((val) << A2XX_SQ_TEX_1_REQUEST_SIZE__SHIFT) & A2XX_SQ_TEX_1_REQUEST_SIZE__MASK; |
| } |
| #define A2XX_SQ_TEX_1_STACKED 0x00000400 |
| #define A2XX_SQ_TEX_1_CLAMP_POLICY__MASK 0x00000800 |
| #define A2XX_SQ_TEX_1_CLAMP_POLICY__SHIFT 11 |
| static inline uint32_t A2XX_SQ_TEX_1_CLAMP_POLICY(enum sq_tex_clamp_policy val) |
| { |
| return ((val) << A2XX_SQ_TEX_1_CLAMP_POLICY__SHIFT) & A2XX_SQ_TEX_1_CLAMP_POLICY__MASK; |
| } |
| #define A2XX_SQ_TEX_1_BASE_ADDRESS__MASK 0xfffff000 |
| #define A2XX_SQ_TEX_1_BASE_ADDRESS__SHIFT 12 |
| static inline uint32_t A2XX_SQ_TEX_1_BASE_ADDRESS(uint32_t val) |
| { |
| return ((val >> 12) << A2XX_SQ_TEX_1_BASE_ADDRESS__SHIFT) & A2XX_SQ_TEX_1_BASE_ADDRESS__MASK; |
| } |
| |
| #define REG_A2XX_SQ_TEX_2 0x00000002 |
| #define A2XX_SQ_TEX_2_WIDTH__MASK 0x00001fff |
| #define A2XX_SQ_TEX_2_WIDTH__SHIFT 0 |
| static inline uint32_t A2XX_SQ_TEX_2_WIDTH(uint32_t val) |
| { |
| return ((val) << A2XX_SQ_TEX_2_WIDTH__SHIFT) & A2XX_SQ_TEX_2_WIDTH__MASK; |
| } |
| #define A2XX_SQ_TEX_2_HEIGHT__MASK 0x03ffe000 |
| #define A2XX_SQ_TEX_2_HEIGHT__SHIFT 13 |
| static inline uint32_t A2XX_SQ_TEX_2_HEIGHT(uint32_t val) |
| { |
| return ((val) << A2XX_SQ_TEX_2_HEIGHT__SHIFT) & A2XX_SQ_TEX_2_HEIGHT__MASK; |
| } |
| #define A2XX_SQ_TEX_2_DEPTH__MASK 0xfc000000 |
| #define A2XX_SQ_TEX_2_DEPTH__SHIFT 26 |
| static inline uint32_t A2XX_SQ_TEX_2_DEPTH(uint32_t val) |
| { |
| return ((val) << A2XX_SQ_TEX_2_DEPTH__SHIFT) & A2XX_SQ_TEX_2_DEPTH__MASK; |
| } |
| |
| #define REG_A2XX_SQ_TEX_3 0x00000003 |
| #define A2XX_SQ_TEX_3_NUM_FORMAT__MASK 0x00000001 |
| #define A2XX_SQ_TEX_3_NUM_FORMAT__SHIFT 0 |
| static inline uint32_t A2XX_SQ_TEX_3_NUM_FORMAT(enum sq_tex_num_format val) |
| { |
| return ((val) << A2XX_SQ_TEX_3_NUM_FORMAT__SHIFT) & A2XX_SQ_TEX_3_NUM_FORMAT__MASK; |
| } |
| #define A2XX_SQ_TEX_3_SWIZ_X__MASK 0x0000000e |
| #define A2XX_SQ_TEX_3_SWIZ_X__SHIFT 1 |
| static inline uint32_t A2XX_SQ_TEX_3_SWIZ_X(enum sq_tex_swiz val) |
| { |
| return ((val) << A2XX_SQ_TEX_3_SWIZ_X__SHIFT) & A2XX_SQ_TEX_3_SWIZ_X__MASK; |
| } |
| #define A2XX_SQ_TEX_3_SWIZ_Y__MASK 0x00000070 |
| #define A2XX_SQ_TEX_3_SWIZ_Y__SHIFT 4 |
| static inline uint32_t A2XX_SQ_TEX_3_SWIZ_Y(enum sq_tex_swiz val) |
| { |
| return ((val) << A2XX_SQ_TEX_3_SWIZ_Y__SHIFT) & A2XX_SQ_TEX_3_SWIZ_Y__MASK; |
| } |
| #define A2XX_SQ_TEX_3_SWIZ_Z__MASK 0x00000380 |
| #define A2XX_SQ_TEX_3_SWIZ_Z__SHIFT 7 |
| static inline uint32_t A2XX_SQ_TEX_3_SWIZ_Z(enum sq_tex_swiz val) |
| { |
| return ((val) << A2XX_SQ_TEX_3_SWIZ_Z__SHIFT) & A2XX_SQ_TEX_3_SWIZ_Z__MASK; |
| } |
| #define A2XX_SQ_TEX_3_SWIZ_W__MASK 0x00001c00 |
| #define A2XX_SQ_TEX_3_SWIZ_W__SHIFT 10 |
| static inline uint32_t A2XX_SQ_TEX_3_SWIZ_W(enum sq_tex_swiz val) |
| { |
| return ((val) << A2XX_SQ_TEX_3_SWIZ_W__SHIFT) & A2XX_SQ_TEX_3_SWIZ_W__MASK; |
| } |
| #define A2XX_SQ_TEX_3_EXP_ADJUST__MASK 0x0007e000 |
| #define A2XX_SQ_TEX_3_EXP_ADJUST__SHIFT 13 |
| static inline uint32_t A2XX_SQ_TEX_3_EXP_ADJUST(int32_t val) |
| { |
| return ((val) << A2XX_SQ_TEX_3_EXP_ADJUST__SHIFT) & A2XX_SQ_TEX_3_EXP_ADJUST__MASK; |
| } |
| #define A2XX_SQ_TEX_3_XY_MAG_FILTER__MASK 0x00180000 |
| #define A2XX_SQ_TEX_3_XY_MAG_FILTER__SHIFT 19 |
| static inline uint32_t A2XX_SQ_TEX_3_XY_MAG_FILTER(enum sq_tex_filter val) |
| { |
| return ((val) << A2XX_SQ_TEX_3_XY_MAG_FILTER__SHIFT) & A2XX_SQ_TEX_3_XY_MAG_FILTER__MASK; |
| } |
| #define A2XX_SQ_TEX_3_XY_MIN_FILTER__MASK 0x00600000 |
| #define A2XX_SQ_TEX_3_XY_MIN_FILTER__SHIFT 21 |
| static inline uint32_t A2XX_SQ_TEX_3_XY_MIN_FILTER(enum sq_tex_filter val) |
| { |
| return ((val) << A2XX_SQ_TEX_3_XY_MIN_FILTER__SHIFT) & A2XX_SQ_TEX_3_XY_MIN_FILTER__MASK; |
| } |
| #define A2XX_SQ_TEX_3_MIP_FILTER__MASK 0x01800000 |
| #define A2XX_SQ_TEX_3_MIP_FILTER__SHIFT 23 |
| static inline uint32_t A2XX_SQ_TEX_3_MIP_FILTER(enum sq_tex_filter val) |
| { |
| return ((val) << A2XX_SQ_TEX_3_MIP_FILTER__SHIFT) & A2XX_SQ_TEX_3_MIP_FILTER__MASK; |
| } |
| #define A2XX_SQ_TEX_3_ANISO_FILTER__MASK 0x0e000000 |
| #define A2XX_SQ_TEX_3_ANISO_FILTER__SHIFT 25 |
| static inline uint32_t A2XX_SQ_TEX_3_ANISO_FILTER(enum sq_tex_aniso_filter val) |
| { |
| return ((val) << A2XX_SQ_TEX_3_ANISO_FILTER__SHIFT) & A2XX_SQ_TEX_3_ANISO_FILTER__MASK; |
| } |
| #define A2XX_SQ_TEX_3_BORDER_SIZE__MASK 0x80000000 |
| #define A2XX_SQ_TEX_3_BORDER_SIZE__SHIFT 31 |
| static inline uint32_t A2XX_SQ_TEX_3_BORDER_SIZE(uint32_t val) |
| { |
| return ((val) << A2XX_SQ_TEX_3_BORDER_SIZE__SHIFT) & A2XX_SQ_TEX_3_BORDER_SIZE__MASK; |
| } |
| |
| #define REG_A2XX_SQ_TEX_4 0x00000004 |
| #define A2XX_SQ_TEX_4_VOL_MAG_FILTER__MASK 0x00000001 |
| #define A2XX_SQ_TEX_4_VOL_MAG_FILTER__SHIFT 0 |
| static inline uint32_t A2XX_SQ_TEX_4_VOL_MAG_FILTER(enum sq_tex_filter val) |
| { |
| return ((val) << A2XX_SQ_TEX_4_VOL_MAG_FILTER__SHIFT) & A2XX_SQ_TEX_4_VOL_MAG_FILTER__MASK; |
| } |
| #define A2XX_SQ_TEX_4_VOL_MIN_FILTER__MASK 0x00000002 |
| #define A2XX_SQ_TEX_4_VOL_MIN_FILTER__SHIFT 1 |
| static inline uint32_t A2XX_SQ_TEX_4_VOL_MIN_FILTER(enum sq_tex_filter val) |
| { |
| return ((val) << A2XX_SQ_TEX_4_VOL_MIN_FILTER__SHIFT) & A2XX_SQ_TEX_4_VOL_MIN_FILTER__MASK; |
| } |
| #define A2XX_SQ_TEX_4_MIP_MIN_LEVEL__MASK 0x0000003c |
| #define A2XX_SQ_TEX_4_MIP_MIN_LEVEL__SHIFT 2 |
| static inline uint32_t A2XX_SQ_TEX_4_MIP_MIN_LEVEL(uint32_t val) |
| { |
| return ((val) << A2XX_SQ_TEX_4_MIP_MIN_LEVEL__SHIFT) & A2XX_SQ_TEX_4_MIP_MIN_LEVEL__MASK; |
| } |
| #define A2XX_SQ_TEX_4_MIP_MAX_LEVEL__MASK 0x000003c0 |
| #define A2XX_SQ_TEX_4_MIP_MAX_LEVEL__SHIFT 6 |
| static inline uint32_t A2XX_SQ_TEX_4_MIP_MAX_LEVEL(uint32_t val) |
| { |
| return ((val) << A2XX_SQ_TEX_4_MIP_MAX_LEVEL__SHIFT) & A2XX_SQ_TEX_4_MIP_MAX_LEVEL__MASK; |
| } |
| #define A2XX_SQ_TEX_4_MAX_ANISO_WALK 0x00000400 |
| #define A2XX_SQ_TEX_4_MIN_ANISO_WALK 0x00000800 |
| #define A2XX_SQ_TEX_4_LOD_BIAS__MASK 0x003ff000 |
| #define A2XX_SQ_TEX_4_LOD_BIAS__SHIFT 12 |
| static inline uint32_t A2XX_SQ_TEX_4_LOD_BIAS(float val) |
| { |
| return ((((int32_t)(val * 32.0))) << A2XX_SQ_TEX_4_LOD_BIAS__SHIFT) & A2XX_SQ_TEX_4_LOD_BIAS__MASK; |
| } |
| #define A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_H__MASK 0x07c00000 |
| #define A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_H__SHIFT 22 |
| static inline uint32_t A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_H(uint32_t val) |
| { |
| return ((val) << A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_H__SHIFT) & A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_H__MASK; |
| } |
| #define A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_V__MASK 0xf8000000 |
| #define A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_V__SHIFT 27 |
| static inline uint32_t A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_V(uint32_t val) |
| { |
| return ((val) << A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_V__SHIFT) & A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_V__MASK; |
| } |
| |
| #define REG_A2XX_SQ_TEX_5 0x00000005 |
| #define A2XX_SQ_TEX_5_BORDER_COLOR__MASK 0x00000003 |
| #define A2XX_SQ_TEX_5_BORDER_COLOR__SHIFT 0 |
| static inline uint32_t A2XX_SQ_TEX_5_BORDER_COLOR(enum sq_tex_border_color val) |
| { |
| return ((val) << A2XX_SQ_TEX_5_BORDER_COLOR__SHIFT) & A2XX_SQ_TEX_5_BORDER_COLOR__MASK; |
| } |
| #define A2XX_SQ_TEX_5_FORCE_BCW_MAX 0x00000004 |
| #define A2XX_SQ_TEX_5_TRI_CLAMP__MASK 0x00000018 |
| #define A2XX_SQ_TEX_5_TRI_CLAMP__SHIFT 3 |
| static inline uint32_t A2XX_SQ_TEX_5_TRI_CLAMP(uint32_t val) |
| { |
| return ((val) << A2XX_SQ_TEX_5_TRI_CLAMP__SHIFT) & A2XX_SQ_TEX_5_TRI_CLAMP__MASK; |
| } |
| #define A2XX_SQ_TEX_5_ANISO_BIAS__MASK 0x000001e0 |
| #define A2XX_SQ_TEX_5_ANISO_BIAS__SHIFT 5 |
| static inline uint32_t A2XX_SQ_TEX_5_ANISO_BIAS(float val) |
| { |
| return ((((int32_t)(val * 1.0))) << A2XX_SQ_TEX_5_ANISO_BIAS__SHIFT) & A2XX_SQ_TEX_5_ANISO_BIAS__MASK; |
| } |
| #define A2XX_SQ_TEX_5_DIMENSION__MASK 0x00000600 |
| #define A2XX_SQ_TEX_5_DIMENSION__SHIFT 9 |
| static inline uint32_t A2XX_SQ_TEX_5_DIMENSION(enum sq_tex_dimension val) |
| { |
| return ((val) << A2XX_SQ_TEX_5_DIMENSION__SHIFT) & A2XX_SQ_TEX_5_DIMENSION__MASK; |
| } |
| #define A2XX_SQ_TEX_5_PACKED_MIPS 0x00000800 |
| #define A2XX_SQ_TEX_5_MIP_ADDRESS__MASK 0xfffff000 |
| #define A2XX_SQ_TEX_5_MIP_ADDRESS__SHIFT 12 |
| static inline uint32_t A2XX_SQ_TEX_5_MIP_ADDRESS(uint32_t val) |
| { |
| return ((val >> 12) << A2XX_SQ_TEX_5_MIP_ADDRESS__SHIFT) & A2XX_SQ_TEX_5_MIP_ADDRESS__MASK; |
| } |
| |
| |
| #endif /* A2XX_XML */ |
