| # SPDX-License-Identifier: GPL-2.0 |
| %YAML 1.2 |
| --- |
| $id: http://devicetree.org/schemas/display/allwinner,sun9i-a80-deu.yaml# |
| $schema: http://devicetree.org/meta-schemas/core.yaml# |
| |
| title: Allwinner A80 Detail Enhancement Unit Device Tree Bindings |
| |
| maintainers: |
| - Chen-Yu Tsai <wens@csie.org> |
| - Maxime Ripard <mripard@kernel.org> |
| |
| description: | |
| The DEU (Detail Enhancement Unit), found in the Allwinner A80 SoC, |
| can sharpen the display content in both luma and chroma channels. |
| |
| properties: |
| compatible: |
| const: allwinner,sun9i-a80-deu |
| |
| reg: |
| maxItems: 1 |
| |
| interrupts: |
| maxItems: 1 |
| |
| clocks: |
| items: |
| - description: The DEU interface clock |
| - description: The DEU module clock |
| - description: The DEU DRAM clock |
| |
| clock-names: |
| items: |
| - const: ahb |
| - const: mod |
| - const: ram |
| |
| resets: |
| maxItems: 1 |
| |
| ports: |
| type: object |
| description: | |
| A ports node with endpoint definitions as defined in |
| Documentation/devicetree/bindings/media/video-interfaces.txt. |
| |
| properties: |
| "#address-cells": |
| const: 1 |
| |
| "#size-cells": |
| const: 0 |
| |
| port@0: |
| type: object |
| description: | |
| Input endpoints of the controller. |
| |
| port@1: |
| type: object |
| description: | |
| Output endpoints of the controller. |
| |
| required: |
| - "#address-cells" |
| - "#size-cells" |
| - port@0 |
| - port@1 |
| |
| additionalProperties: false |
| |
| required: |
| - compatible |
| - reg |
| - interrupts |
| - clocks |
| - clock-names |
| - resets |
| - ports |
| |
| additionalProperties: false |
| |
| examples: |
| - | |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| |
| #include <dt-bindings/clock/sun9i-a80-de.h> |
| #include <dt-bindings/reset/sun9i-a80-de.h> |
| |
| deu0: deu@3300000 { |
| compatible = "allwinner,sun9i-a80-deu"; |
| reg = <0x03300000 0x40000>; |
| interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&de_clocks CLK_BUS_DEU0>, |
| <&de_clocks CLK_IEP_DEU0>, |
| <&de_clocks CLK_DRAM_DEU0>; |
| clock-names = "ahb", |
| "mod", |
| "ram"; |
| resets = <&de_clocks RST_DEU0>; |
| |
| ports { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| deu0_in: port@0 { |
| reg = <0>; |
| |
| deu0_in_fe0: endpoint { |
| remote-endpoint = <&fe0_out_deu0>; |
| }; |
| }; |
| |
| deu0_out: port@1 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <1>; |
| |
| deu0_out_be0: endpoint@0 { |
| reg = <0>; |
| remote-endpoint = <&be0_in_deu0>; |
| }; |
| |
| deu0_out_be1: endpoint@1 { |
| reg = <1>; |
| remote-endpoint = <&be1_in_deu0>; |
| }; |
| }; |
| }; |
| }; |
| |
| ... |
