| /* SPDX-License-Identifier: GPL-2.0 |
| * |
| * Copyright 2016-2018 HabanaLabs, Ltd. |
| * All Rights Reserved. |
| * |
| */ |
| |
| /************************************ |
| ** This is an auto-generated file ** |
| ** DO NOT EDIT BELOW ** |
| ************************************/ |
| |
| #ifndef ASIC_REG_NIF_RTR_CTRL_2_REGS_H_ |
| #define ASIC_REG_NIF_RTR_CTRL_2_REGS_H_ |
| |
| /* |
| ***************************************** |
| * NIF_RTR_CTRL_2 (Prototype: RTR_CTRL) |
| ***************************************** |
| */ |
| |
| #define mmNIF_RTR_CTRL_2_PERM_SEL 0x3A6108 |
| |
| #define mmNIF_RTR_CTRL_2_HBM_POLY_H3_0 0x3A6114 |
| |
| #define mmNIF_RTR_CTRL_2_HBM_POLY_H3_1 0x3A6118 |
| |
| #define mmNIF_RTR_CTRL_2_HBM_POLY_H3_2 0x3A611C |
| |
| #define mmNIF_RTR_CTRL_2_HBM_POLY_H3_3 0x3A6120 |
| |
| #define mmNIF_RTR_CTRL_2_HBM_POLY_H3_4 0x3A6124 |
| |
| #define mmNIF_RTR_CTRL_2_HBM_POLY_H3_5 0x3A6128 |
| |
| #define mmNIF_RTR_CTRL_2_HBM_POLY_H3_6 0x3A612C |
| |
| #define mmNIF_RTR_CTRL_2_HBM_POLY_H3_7 0x3A6130 |
| |
| #define mmNIF_RTR_CTRL_2_HBM_POLY_H3_8 0x3A6134 |
| |
| #define mmNIF_RTR_CTRL_2_HBM_POLY_H3_9 0x3A6138 |
| |
| #define mmNIF_RTR_CTRL_2_HBM_POLY_H3_10 0x3A613C |
| |
| #define mmNIF_RTR_CTRL_2_HBM_POLY_H3_11 0x3A6140 |
| |
| #define mmNIF_RTR_CTRL_2_HBM_POLY_H3_12 0x3A6144 |
| |
| #define mmNIF_RTR_CTRL_2_HBM_POLY_H3_13 0x3A6148 |
| |
| #define mmNIF_RTR_CTRL_2_HBM_POLY_H3_14 0x3A614C |
| |
| #define mmNIF_RTR_CTRL_2_HBM_POLY_H3_15 0x3A6150 |
| |
| #define mmNIF_RTR_CTRL_2_HBM_POLY_H3_16 0x3A6154 |
| |
| #define mmNIF_RTR_CTRL_2_HBM_POLY_H3_17 0x3A6158 |
| |
| #define mmNIF_RTR_CTRL_2_HBM_POLY_H3_18 0x3A615C |
| |
| #define mmNIF_RTR_CTRL_2_HBM_POLY_H3_19 0x3A6160 |
| |
| #define mmNIF_RTR_CTRL_2_HBM_POLY_H3_20 0x3A6164 |
| |
| #define mmNIF_RTR_CTRL_2_HBM_POLY_H3_21 0x3A6168 |
| |
| #define mmNIF_RTR_CTRL_2_HBM_POLY_H3_22 0x3A616C |
| |
| #define mmNIF_RTR_CTRL_2_HBM_POLY_H3_23 0x3A6170 |
| |
| #define mmNIF_RTR_CTRL_2_HBM_POLY_H3_24 0x3A6174 |
| |
| #define mmNIF_RTR_CTRL_2_HBM_POLY_H3_25 0x3A6178 |
| |
| #define mmNIF_RTR_CTRL_2_HBM_POLY_H3_26 0x3A617C |
| |
| #define mmNIF_RTR_CTRL_2_HBM_POLY_H3_27 0x3A6180 |
| |
| #define mmNIF_RTR_CTRL_2_SRAM_POLY_H3_0 0x3A6184 |
| |
| #define mmNIF_RTR_CTRL_2_SRAM_POLY_H3_1 0x3A6188 |
| |
| #define mmNIF_RTR_CTRL_2_SRAM_POLY_H3_2 0x3A618C |
| |
| #define mmNIF_RTR_CTRL_2_SRAM_POLY_H3_3 0x3A6190 |
| |
| #define mmNIF_RTR_CTRL_2_SRAM_POLY_H3_4 0x3A6194 |
| |
| #define mmNIF_RTR_CTRL_2_SRAM_POLY_H3_5 0x3A6198 |
| |
| #define mmNIF_RTR_CTRL_2_SRAM_POLY_H3_6 0x3A619C |
| |
| #define mmNIF_RTR_CTRL_2_SRAM_POLY_H3_7 0x3A61A0 |
| |
| #define mmNIF_RTR_CTRL_2_SRAM_POLY_H3_8 0x3A61A4 |
| |
| #define mmNIF_RTR_CTRL_2_SRAM_POLY_H3_9 0x3A61A8 |
| |
| #define mmNIF_RTR_CTRL_2_SRAM_POLY_H3_10 0x3A61AC |
| |
| #define mmNIF_RTR_CTRL_2_SRAM_POLY_H3_11 0x3A61B0 |
| |
| #define mmNIF_RTR_CTRL_2_SRAM_POLY_H3_12 0x3A61B4 |
| |
| #define mmNIF_RTR_CTRL_2_SRAM_POLY_H3_13 0x3A61B8 |
| |
| #define mmNIF_RTR_CTRL_2_SRAM_POLY_H3_14 0x3A61BC |
| |
| #define mmNIF_RTR_CTRL_2_SCRAM_SRAM_EN 0x3A626C |
| |
| #define mmNIF_RTR_CTRL_2_RL_HBM_EN 0x3A6274 |
| |
| #define mmNIF_RTR_CTRL_2_RL_HBM_SAT 0x3A6278 |
| |
| #define mmNIF_RTR_CTRL_2_RL_HBM_RST 0x3A627C |
| |
| #define mmNIF_RTR_CTRL_2_RL_HBM_TIMEOUT 0x3A6280 |
| |
| #define mmNIF_RTR_CTRL_2_SCRAM_HBM_EN 0x3A6284 |
| |
| #define mmNIF_RTR_CTRL_2_RL_PCI_EN 0x3A6288 |
| |
| #define mmNIF_RTR_CTRL_2_RL_PCI_SAT 0x3A628C |
| |
| #define mmNIF_RTR_CTRL_2_RL_PCI_RST 0x3A6290 |
| |
| #define mmNIF_RTR_CTRL_2_RL_PCI_TIMEOUT 0x3A6294 |
| |
| #define mmNIF_RTR_CTRL_2_RL_SRAM_EN 0x3A629C |
| |
| #define mmNIF_RTR_CTRL_2_RL_SRAM_SAT 0x3A62A0 |
| |
| #define mmNIF_RTR_CTRL_2_RL_SRAM_RST 0x3A62A4 |
| |
| #define mmNIF_RTR_CTRL_2_RL_SRAM_TIMEOUT 0x3A62AC |
| |
| #define mmNIF_RTR_CTRL_2_RL_SRAM_RED 0x3A62B4 |
| |
| #define mmNIF_RTR_CTRL_2_E2E_HBM_EN 0x3A62EC |
| |
| #define mmNIF_RTR_CTRL_2_E2E_PCI_EN 0x3A62F0 |
| |
| #define mmNIF_RTR_CTRL_2_E2E_HBM_WR_SIZE 0x3A62F4 |
| |
| #define mmNIF_RTR_CTRL_2_E2E_PCI_WR_SIZE 0x3A62F8 |
| |
| #define mmNIF_RTR_CTRL_2_E2E_AW_PCI_CTR_SET_EN 0x3A6404 |
| |
| #define mmNIF_RTR_CTRL_2_E2E_AW_PCI_CTR_SET 0x3A6408 |
| |
| #define mmNIF_RTR_CTRL_2_E2E_AW_PCI_CTR_WRAP 0x3A640C |
| |
| #define mmNIF_RTR_CTRL_2_E2E_AW_PCI_CTR_CNT 0x3A6410 |
| |
| #define mmNIF_RTR_CTRL_2_E2E_AW_HBM_CTR_SET_EN 0x3A6414 |
| |
| #define mmNIF_RTR_CTRL_2_E2E_AW_HBM_CTR_SET 0x3A6418 |
| |
| #define mmNIF_RTR_CTRL_2_E2E_HBM_RD_SIZE 0x3A641C |
| |
| #define mmNIF_RTR_CTRL_2_E2E_PCI_RD_SIZE 0x3A6420 |
| |
| #define mmNIF_RTR_CTRL_2_E2E_AR_PCI_CTR_SET_EN 0x3A6424 |
| |
| #define mmNIF_RTR_CTRL_2_E2E_AR_PCI_CTR_SET 0x3A6428 |
| |
| #define mmNIF_RTR_CTRL_2_E2E_AR_PCI_CTR_WRAP 0x3A642C |
| |
| #define mmNIF_RTR_CTRL_2_E2E_AR_PCI_CTR_CNT 0x3A6430 |
| |
| #define mmNIF_RTR_CTRL_2_E2E_AR_HBM_CTR_SET_EN 0x3A6434 |
| |
| #define mmNIF_RTR_CTRL_2_E2E_AR_HBM_CTR_SET 0x3A6438 |
| |
| #define mmNIF_RTR_CTRL_2_NL_HBM_SEL_0 0x3A6450 |
| |
| #define mmNIF_RTR_CTRL_2_NL_HBM_SEL_1 0x3A6454 |
| |
| #define mmNIF_RTR_CTRL_2_NON_LIN_EN 0x3A6480 |
| |
| #define mmNIF_RTR_CTRL_2_NL_SRAM_BANK_0 0x3A6500 |
| |
| #define mmNIF_RTR_CTRL_2_NL_SRAM_BANK_1 0x3A6504 |
| |
| #define mmNIF_RTR_CTRL_2_NL_SRAM_BANK_2 0x3A6508 |
| |
| #define mmNIF_RTR_CTRL_2_NL_SRAM_BANK_3 0x3A650C |
| |
| #define mmNIF_RTR_CTRL_2_NL_SRAM_BANK_4 0x3A6510 |
| |
| #define mmNIF_RTR_CTRL_2_NL_SRAM_OFFSET_0 0x3A6514 |
| |
| #define mmNIF_RTR_CTRL_2_NL_SRAM_OFFSET_1 0x3A6520 |
| |
| #define mmNIF_RTR_CTRL_2_NL_SRAM_OFFSET_2 0x3A6524 |
| |
| #define mmNIF_RTR_CTRL_2_NL_SRAM_OFFSET_3 0x3A6528 |
| |
| #define mmNIF_RTR_CTRL_2_NL_SRAM_OFFSET_4 0x3A652C |
| |
| #define mmNIF_RTR_CTRL_2_NL_SRAM_OFFSET_5 0x3A6530 |
| |
| #define mmNIF_RTR_CTRL_2_NL_SRAM_OFFSET_6 0x3A6534 |
| |
| #define mmNIF_RTR_CTRL_2_NL_SRAM_OFFSET_7 0x3A6538 |
| |
| #define mmNIF_RTR_CTRL_2_NL_SRAM_OFFSET_8 0x3A653C |
| |
| #define mmNIF_RTR_CTRL_2_NL_SRAM_OFFSET_9 0x3A6540 |
| |
| #define mmNIF_RTR_CTRL_2_NL_HBM_OFFSET_0 0x3A6550 |
| |
| #define mmNIF_RTR_CTRL_2_NL_HBM_OFFSET_1 0x3A6554 |
| |
| #define mmNIF_RTR_CTRL_2_NL_HBM_OFFSET_2 0x3A6558 |
| |
| #define mmNIF_RTR_CTRL_2_NL_HBM_OFFSET_3 0x3A655C |
| |
| #define mmNIF_RTR_CTRL_2_NL_HBM_OFFSET_4 0x3A6560 |
| |
| #define mmNIF_RTR_CTRL_2_NL_HBM_OFFSET_5 0x3A6564 |
| |
| #define mmNIF_RTR_CTRL_2_NL_HBM_OFFSET_6 0x3A6568 |
| |
| #define mmNIF_RTR_CTRL_2_NL_HBM_OFFSET_7 0x3A656C |
| |
| #define mmNIF_RTR_CTRL_2_NL_HBM_OFFSET_8 0x3A6570 |
| |
| #define mmNIF_RTR_CTRL_2_NL_HBM_OFFSET_9 0x3A6574 |
| |
| #define mmNIF_RTR_CTRL_2_NL_HBM_OFFSET_10 0x3A6578 |
| |
| #define mmNIF_RTR_CTRL_2_NL_HBM_OFFSET_11 0x3A657C |
| |
| #define mmNIF_RTR_CTRL_2_NL_HBM_OFFSET_12 0x3A6580 |
| |
| #define mmNIF_RTR_CTRL_2_NL_HBM_OFFSET_13 0x3A6584 |
| |
| #define mmNIF_RTR_CTRL_2_NL_HBM_OFFSET_14 0x3A6588 |
| |
| #define mmNIF_RTR_CTRL_2_NL_HBM_OFFSET_15 0x3A658C |
| |
| #define mmNIF_RTR_CTRL_2_NL_HBM_OFFSET_16 0x3A6590 |
| |
| #define mmNIF_RTR_CTRL_2_NL_HBM_OFFSET_17 0x3A6594 |
| |
| #define mmNIF_RTR_CTRL_2_NL_HBM_OFFSET_18 0x3A6598 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_0 0x3A65E4 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_1 0x3A65E8 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_2 0x3A65EC |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_3 0x3A65F0 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_4 0x3A65F4 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_5 0x3A65F8 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_6 0x3A65FC |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_7 0x3A6600 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_8 0x3A6604 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_9 0x3A6608 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_10 0x3A660C |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_11 0x3A6610 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_12 0x3A6614 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_13 0x3A6618 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_14 0x3A661C |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_15 0x3A6620 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_0 0x3A6624 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_1 0x3A6628 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_2 0x3A662C |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_3 0x3A6630 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_4 0x3A6634 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_5 0x3A6638 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_6 0x3A663C |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_7 0x3A6640 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_8 0x3A6644 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_9 0x3A6648 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_10 0x3A664C |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_11 0x3A6650 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_12 0x3A6654 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_13 0x3A6658 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_14 0x3A665C |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_15 0x3A6660 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_0 0x3A6664 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_1 0x3A6668 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_2 0x3A666C |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_3 0x3A6670 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_4 0x3A6674 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_5 0x3A6678 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_6 0x3A667C |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_7 0x3A6680 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_8 0x3A6684 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_9 0x3A6688 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_10 0x3A668C |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_11 0x3A6690 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_12 0x3A6694 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_13 0x3A6698 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_14 0x3A669C |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_15 0x3A66A0 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_0 0x3A66A4 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_1 0x3A66A8 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_2 0x3A66AC |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_3 0x3A66B0 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_4 0x3A66B4 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_5 0x3A66B8 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_6 0x3A66BC |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_7 0x3A66C0 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_8 0x3A66C4 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_9 0x3A66C8 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_10 0x3A66CC |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_11 0x3A66D0 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_12 0x3A66D4 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_13 0x3A66D8 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_14 0x3A66DC |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_15 0x3A66E0 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_0 0x3A66E4 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_1 0x3A66E8 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_2 0x3A66EC |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_3 0x3A66F0 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_4 0x3A66F4 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_5 0x3A66F8 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_6 0x3A66FC |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_7 0x3A6700 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_8 0x3A6704 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_9 0x3A6708 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_10 0x3A670C |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_11 0x3A6710 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_12 0x3A6714 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_13 0x3A6718 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_14 0x3A671C |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_15 0x3A6720 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_0 0x3A6724 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_1 0x3A6728 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_2 0x3A672C |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_3 0x3A6730 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_4 0x3A6734 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_5 0x3A6738 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_6 0x3A673C |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_7 0x3A6740 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_8 0x3A6744 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_9 0x3A6748 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_10 0x3A674C |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_11 0x3A6750 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_12 0x3A6754 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_13 0x3A6758 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_14 0x3A675C |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_15 0x3A6760 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_0 0x3A6764 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_1 0x3A6768 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_2 0x3A676C |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_3 0x3A6770 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_4 0x3A6774 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_5 0x3A6778 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_6 0x3A677C |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_7 0x3A6780 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_8 0x3A6784 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_9 0x3A6788 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_10 0x3A678C |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_11 0x3A6790 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_12 0x3A6794 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_13 0x3A6798 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_14 0x3A679C |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_15 0x3A67A0 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_0 0x3A67A4 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_1 0x3A67A8 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_2 0x3A67AC |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_3 0x3A67B0 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_4 0x3A67B4 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_5 0x3A67B8 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_6 0x3A67BC |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_7 0x3A67C0 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_8 0x3A67C4 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_9 0x3A67C8 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_10 0x3A67CC |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_11 0x3A67D0 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_12 0x3A67D4 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_13 0x3A67D8 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_14 0x3A67DC |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_15 0x3A67E0 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_0 0x3A6824 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_1 0x3A6828 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_2 0x3A682C |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_3 0x3A6830 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_4 0x3A6834 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_5 0x3A6838 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_6 0x3A683C |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_7 0x3A6840 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_8 0x3A6844 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_9 0x3A6848 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_10 0x3A684C |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_11 0x3A6850 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_12 0x3A6854 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_13 0x3A6858 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_14 0x3A685C |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_15 0x3A6860 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_0 0x3A6864 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_1 0x3A6868 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_2 0x3A686C |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_3 0x3A6870 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_4 0x3A6874 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_5 0x3A6878 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_6 0x3A687C |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_7 0x3A6880 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_8 0x3A6884 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_9 0x3A6888 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_10 0x3A688C |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_11 0x3A6890 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_12 0x3A6894 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_13 0x3A6898 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_14 0x3A689C |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_15 0x3A68A0 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_0 0x3A68A4 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_1 0x3A68A8 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_2 0x3A68AC |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_3 0x3A68B0 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_4 0x3A68B4 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_5 0x3A68B8 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_6 0x3A68BC |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_7 0x3A68C0 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_8 0x3A68C4 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_9 0x3A68C8 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_10 0x3A68CC |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_11 0x3A68D0 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_12 0x3A68D4 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_13 0x3A68D8 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_14 0x3A68DC |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_15 0x3A68E0 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_0 0x3A68E4 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_1 0x3A68E8 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_2 0x3A68EC |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_3 0x3A68F0 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_4 0x3A68F4 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_5 0x3A68F8 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_6 0x3A68FC |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_7 0x3A6900 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_8 0x3A6904 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_9 0x3A6908 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_10 0x3A690C |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_11 0x3A6910 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_12 0x3A6914 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_13 0x3A6918 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_14 0x3A691C |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_15 0x3A6920 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_0 0x3A6924 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_1 0x3A6928 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_2 0x3A692C |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_3 0x3A6930 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_4 0x3A6934 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_5 0x3A6938 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_6 0x3A693C |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_7 0x3A6940 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_8 0x3A6944 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_9 0x3A6948 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_10 0x3A694C |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_11 0x3A6950 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_12 0x3A6954 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_13 0x3A6958 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_14 0x3A695C |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_15 0x3A6960 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_0 0x3A6964 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_1 0x3A6968 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_2 0x3A696C |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_3 0x3A6970 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_4 0x3A6974 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_5 0x3A6978 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_6 0x3A697C |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_7 0x3A6980 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_8 0x3A6984 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_9 0x3A6988 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_10 0x3A698C |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_11 0x3A6990 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_12 0x3A6994 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_13 0x3A6998 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_14 0x3A699C |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_15 0x3A69A0 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_0 0x3A69A4 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_1 0x3A69A8 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_2 0x3A69AC |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_3 0x3A69B0 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_4 0x3A69B4 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_5 0x3A69B8 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_6 0x3A69BC |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_7 0x3A69C0 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_8 0x3A69C4 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_9 0x3A69C8 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_10 0x3A69CC |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_11 0x3A69D0 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_12 0x3A69D4 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_13 0x3A69D8 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_14 0x3A69DC |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_15 0x3A69E0 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_0 0x3A69E4 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_1 0x3A69E8 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_2 0x3A69EC |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_3 0x3A69F0 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_4 0x3A69F4 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_5 0x3A69F8 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_6 0x3A69FC |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_7 0x3A6A00 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_8 0x3A6A04 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_9 0x3A6A08 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_10 0x3A6A0C |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_11 0x3A6A10 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_12 0x3A6A14 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_13 0x3A6A18 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_14 0x3A6A1C |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_15 0x3A6A20 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_HIT_AW 0x3A6A64 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_SEC_HIT_AR 0x3A6A68 |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_HIT_AW 0x3A6A6C |
| |
| #define mmNIF_RTR_CTRL_2_RANGE_PRIV_HIT_AR 0x3A6A70 |
| |
| #define mmNIF_RTR_CTRL_2_RGL_CFG 0x3A6B64 |
| |
| #define mmNIF_RTR_CTRL_2_RGL_SHIFT 0x3A6B68 |
| |
| #define mmNIF_RTR_CTRL_2_RGL_EXPECTED_LAT_0 0x3A6B6C |
| |
| #define mmNIF_RTR_CTRL_2_RGL_EXPECTED_LAT_1 0x3A6B70 |
| |
| #define mmNIF_RTR_CTRL_2_RGL_EXPECTED_LAT_2 0x3A6B74 |
| |
| #define mmNIF_RTR_CTRL_2_RGL_EXPECTED_LAT_3 0x3A6B78 |
| |
| #define mmNIF_RTR_CTRL_2_RGL_EXPECTED_LAT_4 0x3A6B7C |
| |
| #define mmNIF_RTR_CTRL_2_RGL_EXPECTED_LAT_5 0x3A6B80 |
| |
| #define mmNIF_RTR_CTRL_2_RGL_EXPECTED_LAT_6 0x3A6B84 |
| |
| #define mmNIF_RTR_CTRL_2_RGL_EXPECTED_LAT_7 0x3A6B88 |
| |
| #define mmNIF_RTR_CTRL_2_RGL_TOKEN_0 0x3A6BAC |
| |
| #define mmNIF_RTR_CTRL_2_RGL_TOKEN_1 0x3A6BB0 |
| |
| #define mmNIF_RTR_CTRL_2_RGL_TOKEN_2 0x3A6BB4 |
| |
| #define mmNIF_RTR_CTRL_2_RGL_TOKEN_3 0x3A6BB8 |
| |
| #define mmNIF_RTR_CTRL_2_RGL_TOKEN_4 0x3A6BBC |
| |
| #define mmNIF_RTR_CTRL_2_RGL_TOKEN_5 0x3A6BC0 |
| |
| #define mmNIF_RTR_CTRL_2_RGL_TOKEN_6 0x3A6BC4 |
| |
| #define mmNIF_RTR_CTRL_2_RGL_TOKEN_7 0x3A6BC8 |
| |
| #define mmNIF_RTR_CTRL_2_RGL_BANK_ID_0 0x3A6BEC |
| |
| #define mmNIF_RTR_CTRL_2_RGL_BANK_ID_1 0x3A6BF0 |
| |
| #define mmNIF_RTR_CTRL_2_RGL_BANK_ID_2 0x3A6BF4 |
| |
| #define mmNIF_RTR_CTRL_2_RGL_BANK_ID_3 0x3A6BF8 |
| |
| #define mmNIF_RTR_CTRL_2_RGL_BANK_ID_4 0x3A6BFC |
| |
| #define mmNIF_RTR_CTRL_2_RGL_BANK_ID_5 0x3A6C00 |
| |
| #define mmNIF_RTR_CTRL_2_RGL_BANK_ID_6 0x3A6C04 |
| |
| #define mmNIF_RTR_CTRL_2_RGL_BANK_ID_7 0x3A6C08 |
| |
| #define mmNIF_RTR_CTRL_2_RGL_WDT 0x3A6C2C |
| |
| #define mmNIF_RTR_CTRL_2_E2E_AR_HBM0_CH0_CTR_WRAP 0x3A6C30 |
| |
| #define mmNIF_RTR_CTRL_2_E2E_AR_HBM0_CH1_CTR_WRAP 0x3A6C34 |
| |
| #define mmNIF_RTR_CTRL_2_E2E_AR_HBM1_CH0_CTR_WRAP 0x3A6C38 |
| |
| #define mmNIF_RTR_CTRL_2_E2E_AR_HBM1_CH1_CTR_WRAP 0x3A6C3C |
| |
| #define mmNIF_RTR_CTRL_2_E2E_AR_HBM2_CH0_CTR_WRAP 0x3A6C40 |
| |
| #define mmNIF_RTR_CTRL_2_E2E_AR_HBM2_CH1_CTR_WRAP 0x3A6C44 |
| |
| #define mmNIF_RTR_CTRL_2_E2E_AR_HBM3_CH0_CTR_WRAP 0x3A6C48 |
| |
| #define mmNIF_RTR_CTRL_2_E2E_AR_HBM3_CH1_CTR_WRAP 0x3A6C4C |
| |
| #define mmNIF_RTR_CTRL_2_E2E_AR_HBM0_CH0_CTR_CNT 0x3A6C50 |
| |
| #define mmNIF_RTR_CTRL_2_E2E_AR_HBM0_CH1_CTR_CNT 0x3A6C54 |
| |
| #define mmNIF_RTR_CTRL_2_E2E_AR_HBM1_CH0_CTR_CNT 0x3A6C58 |
| |
| #define mmNIF_RTR_CTRL_2_E2E_AR_HBM1_CH1_CTR_CNT 0x3A6C5C |
| |
| #define mmNIF_RTR_CTRL_2_E2E_AR_HBM2_CH0_CTR_CNT 0x3A6C60 |
| |
| #define mmNIF_RTR_CTRL_2_E2E_AR_HBM2_CH1_CTR_CNT 0x3A6C64 |
| |
| #define mmNIF_RTR_CTRL_2_E2E_AR_HBM3_CH0_CTR_CNT 0x3A6C68 |
| |
| #define mmNIF_RTR_CTRL_2_E2E_AR_HBM3_CH1_CTR_CNT 0x3A6C6C |
| |
| #define mmNIF_RTR_CTRL_2_E2E_AW_HBM0_CH0_CTR_WRAP 0x3A6C70 |
| |
| #define mmNIF_RTR_CTRL_2_E2E_AW_HBM0_CH1_CTR_WRAP 0x3A6C74 |
| |
| #define mmNIF_RTR_CTRL_2_E2E_AW_HBM1_CH0_CTR_WRAP 0x3A6C78 |
| |
| #define mmNIF_RTR_CTRL_2_E2E_AW_HBM1_CH1_CTR_WRAP 0x3A6C7C |
| |
| #define mmNIF_RTR_CTRL_2_E2E_AW_HBM2_CH0_CTR_WRAP 0x3A6C80 |
| |
| #define mmNIF_RTR_CTRL_2_E2E_AW_HBM2_CH1_CTR_WRAP 0x3A6C84 |
| |
| #define mmNIF_RTR_CTRL_2_E2E_AW_HBM3_CH0_CTR_WRAP 0x3A6C88 |
| |
| #define mmNIF_RTR_CTRL_2_E2E_AW_HBM3_CH1_CTR_WRAP 0x3A6C8C |
| |
| #define mmNIF_RTR_CTRL_2_E2E_AW_HBM0_CH0_CTR_CNT 0x3A6C90 |
| |
| #define mmNIF_RTR_CTRL_2_E2E_AW_HBM0_CH1_CTR_CNT 0x3A6C94 |
| |
| #define mmNIF_RTR_CTRL_2_E2E_AW_HBM1_CH0_CTR_CNT 0x3A6C98 |
| |
| #define mmNIF_RTR_CTRL_2_E2E_AW_HBM1_CH1_CTR_CNT 0x3A6C9C |
| |
| #define mmNIF_RTR_CTRL_2_E2E_AW_HBM2_CH0_CTR_CNT 0x3A6CA0 |
| |
| #define mmNIF_RTR_CTRL_2_E2E_AW_HBM2_CH1_CTR_CNT 0x3A6CA4 |
| |
| #define mmNIF_RTR_CTRL_2_E2E_AW_HBM3_CH0_CTR_CNT 0x3A6CA8 |
| |
| #define mmNIF_RTR_CTRL_2_E2E_AW_HBM3_CH1_CTR_CNT 0x3A6CAC |
| |
| #define mmNIF_RTR_CTRL_2_NL_HBM_PC_SEL_0 0x3A6CB0 |
| |
| #define mmNIF_RTR_CTRL_2_NL_HBM_PC_SEL_1 0x3A6CB4 |
| |
| #define mmNIF_RTR_CTRL_2_NL_HBM_PC_SEL_2 0x3A6CB8 |
| |
| #define mmNIF_RTR_CTRL_2_NL_HBM_PC_SEL_3 0x3A6CBC |
| |
| #endif /* ASIC_REG_NIF_RTR_CTRL_2_REGS_H_ */ |
