Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt

Rockchip DWC HDMI TX Encoder
============================

The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
with a companion PHY IP.

These DT bindings follow the Synopsys DWC HDMI TX bindings defined in
Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt with the
following device-specific properties.


Required properties:

- compatible: Shall contain "rockchip,rk3288-dw-hdmi".
- reg: See dw_hdmi.txt.
- reg-io-width: See dw_hdmi.txt. Shall be 4.
- interrupts: HDMI interrupt number
- clocks: See dw_hdmi.txt.
- clock-names: Shall contain "iahb" and "isfr" as defined in dw_hdmi.txt.
- ports: See dw_hdmi.txt. The DWC HDMI shall have a single port numbered 0
  corresponding to the video input of the controller. The port shall have two
  endpoints, numbered 0 and 1, connected respectively to the vopb and vopl.
- rockchip,grf: Shall reference the GRF to mux vopl/vopb.

Optional properties

- ddc-i2c-bus: The HDMI DDC bus can be connected to either a system I2C master
  or the functionally-reduced I2C master contained in the DWC HDMI. When
  connected to a system I2C master this property contains a phandle to that
  I2C master controller.
- clock-names: See dw_hdmi.txt. The "cec" clock is optional.
- clock-names: May contain "cec" as defined in dw_hdmi.txt.


Example:

hdmi: hdmi@ff980000 {
	compatible = "rockchip,rk3288-dw-hdmi";
	reg = <0xff980000 0x20000>;
	reg-io-width = <4>;
	ddc-i2c-bus = <&i2c5>;
	rockchip,grf = <&grf>;
	interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cru  PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
	clock-names = "iahb", "isfr";
	status = "disabled";
	ports {
		hdmi_in: port {
			#address-cells = <1>;
			#size-cells = <0>;
			hdmi_in_vopb: endpoint@0 {
				reg = <0>;
				remote-endpoint = <&vopb_out_hdmi>;
			};
			hdmi_in_vopl: endpoint@1 {
				reg = <1>;
				remote-endpoint = <&vopl_out_hdmi>;
			};
		};
	};
};