| # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) |
| %YAML 1.2 |
| --- |
| $id: "http://devicetree.org/schemas/mailbox/st,stm32-ipcc.yaml#" |
| $schema: "http://devicetree.org/meta-schemas/core.yaml#" |
| |
| title: STMicroelectronics STM32 IPC controller bindings |
| |
| description: |
| The IPCC block provides a non blocking signaling mechanism to post and |
| retrieve messages in an atomic way between two processors. |
| It provides the signaling for N bidirectionnal channels. The number of |
| channels (N) can be read from a dedicated register. |
| |
| maintainers: |
| - Fabien Dessenne <fabien.dessenne@foss.st.com> |
| - Arnaud Pouliquen <arnaud.pouliquen@foss.st.com> |
| |
| properties: |
| compatible: |
| const: st,stm32mp1-ipcc |
| |
| reg: |
| maxItems: 1 |
| |
| clocks: |
| maxItems: 1 |
| |
| interrupts: |
| items: |
| - description: rx channel occupied |
| - description: tx channel free |
| - description: wakeup source |
| minItems: 2 |
| |
| interrupt-names: |
| items: |
| - const: rx |
| - const: tx |
| - const: wakeup |
| minItems: 2 |
| |
| wakeup-source: true |
| |
| "#mbox-cells": |
| const: 1 |
| |
| st,proc-id: |
| description: Processor id using the mailbox (0 or 1) |
| $ref: /schemas/types.yaml#/definitions/uint32 |
| enum: [0, 1] |
| |
| required: |
| - compatible |
| - reg |
| - st,proc-id |
| - clocks |
| - interrupt-names |
| - "#mbox-cells" |
| - interrupts |
| |
| additionalProperties: false |
| |
| examples: |
| - | |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| #include <dt-bindings/clock/stm32mp1-clks.h> |
| ipcc: mailbox@4c001000 { |
| compatible = "st,stm32mp1-ipcc"; |
| #mbox-cells = <1>; |
| reg = <0x4c001000 0x400>; |
| st,proc-id = <0>; |
| interrupts-extended = <&intc GIC_SPI 100 IRQ_TYPE_NONE>, |
| <&intc GIC_SPI 101 IRQ_TYPE_NONE>, |
| <&aiec 62 1>; |
| interrupt-names = "rx", "tx", "wakeup"; |
| clocks = <&rcc_clk IPCC>; |
| wakeup-source; |
| }; |
| |
| ... |
