| /* SPDX-License-Identifier: GPL-2.0 */ |
| /* |
| * Copyright (c) 2017, The Linux Foundation. All rights reserved. |
| */ |
| |
| #ifndef QCOM_PHY_QMP_QSERDES_TXRX_V4_20_H_ |
| #define QCOM_PHY_QMP_QSERDES_TXRX_V4_20_H_ |
| |
| /* Only for QMP V4_20 PHY - TX registers */ |
| #define QSERDES_V4_20_TX_LANE_MODE_1 0x88 |
| #define QSERDES_V4_20_TX_LANE_MODE_2 0x8c |
| #define QSERDES_V4_20_TX_LANE_MODE_3 0x90 |
| #define QSERDES_V4_20_TX_VMODE_CTRL1 0xc4 |
| #define QSERDES_V4_20_TX_PI_QEC_CTRL 0xe0 |
| |
| /* Only for QMP V4_20 PHY - RX registers */ |
| #define QSERDES_V4_20_RX_FO_GAIN_RATE2 0x008 |
| #define QSERDES_V4_20_RX_UCDR_PI_CONTROLS 0x058 |
| #define QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE 0x0ac |
| #define QSERDES_V4_20_RX_DFE_3 0x110 |
| #define QSERDES_V4_20_RX_DFE_DAC_ENABLE1 0x134 |
| #define QSERDES_V4_20_RX_DFE_DAC_ENABLE2 0x138 |
| #define QSERDES_V4_20_RX_VGA_CAL_CNTRL2 0x150 |
| #define QSERDES_V4_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x178 |
| #define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B1 0x1c8 |
| #define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B2 0x1cc |
| #define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B3 0x1d0 |
| #define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B4 0x1d4 |
| #define QSERDES_V4_20_RX_RX_MODE_RATE2_B0 0x1d8 |
| #define QSERDES_V4_20_RX_RX_MODE_RATE2_B1 0x1dc |
| #define QSERDES_V4_20_RX_RX_MODE_RATE2_B2 0x1e0 |
| #define QSERDES_V4_20_RX_RX_MODE_RATE2_B3 0x1e4 |
| #define QSERDES_V4_20_RX_RX_MODE_RATE2_B4 0x1e8 |
| #define QSERDES_V4_20_RX_RX_MODE_RATE3_B0 0x1ec |
| #define QSERDES_V4_20_RX_RX_MODE_RATE3_B1 0x1f0 |
| #define QSERDES_V4_20_RX_RX_MODE_RATE3_B2 0x1f4 |
| #define QSERDES_V4_20_RX_RX_MODE_RATE3_B3 0x1f8 |
| #define QSERDES_V4_20_RX_RX_MODE_RATE3_B4 0x1fc |
| #define QSERDES_V4_20_RX_PHPRE_CTRL 0x200 |
| #define QSERDES_V4_20_RX_DFE_CTLE_POST_CAL_OFFSET 0x20c |
| #define QSERDES_V4_20_RX_MARG_COARSE_CTRL2 0x23c |
| |
| #endif |
