| # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| %YAML 1.2 |
| --- |
| $id: http://devicetree.org/schemas/display/st,stm32-dsi.yaml# |
| $schema: http://devicetree.org/meta-schemas/core.yaml# |
| |
| title: STMicroelectronics STM32 DSI host controller |
| |
| maintainers: |
| - Philippe Cornu <philippe.cornu@foss.st.com> |
| - Yannick Fertre <yannick.fertre@foss.st.com> |
| |
| description: |
| The STMicroelectronics STM32 DSI controller uses the Synopsys DesignWare MIPI-DSI host controller. |
| |
| allOf: |
| - $ref: dsi-controller.yaml# |
| |
| properties: |
| compatible: |
| const: st,stm32-dsi |
| |
| reg: |
| maxItems: 1 |
| |
| clocks: |
| items: |
| - description: Module Clock |
| - description: DSI bus clock |
| - description: Pixel clock |
| minItems: 2 |
| |
| clock-names: |
| items: |
| - const: pclk |
| - const: ref |
| - const: px_clk |
| minItems: 2 |
| |
| resets: |
| maxItems: 1 |
| |
| reset-names: |
| items: |
| - const: apb |
| |
| phy-dsi-supply: |
| description: |
| Phandle of the regulator that provides the supply voltage. |
| |
| ports: |
| $ref: /schemas/graph.yaml#/properties/ports |
| |
| properties: |
| port@0: |
| $ref: /schemas/graph.yaml#/properties/port |
| description: |
| DSI input port node, connected to the ltdc rgb output port. |
| |
| port@1: |
| $ref: /schemas/graph.yaml#/$defs/port-base |
| unevaluatedProperties: false |
| description: | |
| DSI output port node, connected to a panel or a bridge input port. |
| properties: |
| endpoint: |
| $ref: /schemas/media/video-interfaces.yaml# |
| unevaluatedProperties: false |
| properties: |
| data-lanes: |
| minItems: 1 |
| items: |
| - const: 1 |
| - const: 2 |
| |
| required: |
| - compatible |
| - reg |
| - clocks |
| - clock-names |
| - ports |
| |
| unevaluatedProperties: false |
| |
| examples: |
| - | |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| #include <dt-bindings/clock/stm32mp1-clks.h> |
| #include <dt-bindings/reset/stm32mp1-resets.h> |
| #include <dt-bindings/gpio/gpio.h> |
| dsi: dsi@5a000000 { |
| compatible = "st,stm32-dsi"; |
| reg = <0x5a000000 0x800>; |
| clocks = <&rcc DSI_K>, <&clk_hse>, <&rcc DSI_PX>; |
| clock-names = "pclk", "ref", "px_clk"; |
| resets = <&rcc DSI_R>; |
| reset-names = "apb"; |
| phy-dsi-supply = <®18>; |
| |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| ports { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| port@0 { |
| reg = <0>; |
| dsi_in: endpoint { |
| remote-endpoint = <<dc_ep1_out>; |
| }; |
| }; |
| |
| port@1 { |
| reg = <1>; |
| dsi_out: endpoint { |
| remote-endpoint = <&panel_in>; |
| }; |
| }; |
| }; |
| |
| panel@0 { |
| compatible = "orisetech,otm8009a"; |
| reg = <0>; |
| reset-gpios = <&gpioe 4 GPIO_ACTIVE_LOW>; |
| power-supply = <&v3v3>; |
| |
| port { |
| panel_in: endpoint { |
| remote-endpoint = <&dsi_out>; |
| }; |
| }; |
| }; |
| }; |
| |
| ... |