Documentation/devicetree/bindings/memory-controllers/intel,ixp4xx-expansion-peripheral-props.yaml

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/intel,ixp4xx-expansion-peripheral-props.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Peripheral properties for Intel IXP4xx Expansion Bus

description:
  The IXP4xx expansion bus controller handles access to devices on the
  memory-mapped expansion bus on the Intel IXP4xx family of system on chips,
  including IXP42x, IXP43x, IXP45x and IXP46x.

maintainers:
  - Linus Walleij <linus.walleij@linaro.org>

properties:
  intel,ixp4xx-eb-t1:
    description: Address timing, extend address phase with n cycles.
    $ref: /schemas/types.yaml#/definitions/uint32
    maximum: 3

  intel,ixp4xx-eb-t2:
    description: Setup chip select timing, extend setup phase with n cycles.
    $ref: /schemas/types.yaml#/definitions/uint32
    maximum: 3

  intel,ixp4xx-eb-t3:
    description: Strobe timing, extend strobe phase with n cycles.
    $ref: /schemas/types.yaml#/definitions/uint32
    maximum: 15

  intel,ixp4xx-eb-t4:
    description: Hold timing, extend hold phase with n cycles.
    $ref: /schemas/types.yaml#/definitions/uint32
    maximum: 3

  intel,ixp4xx-eb-t5:
    description: Recovery timing, extend recovery phase with n cycles.
    $ref: /schemas/types.yaml#/definitions/uint32
    maximum: 15

  intel,ixp4xx-eb-cycle-type:
    description: The type of cycles to use on the expansion bus for this
      chip select. 0 = Intel cycles, 1 = Motorola cycles, 2 = HPI cycles.
    $ref: /schemas/types.yaml#/definitions/uint32
    enum: [0, 1, 2]

  intel,ixp4xx-eb-byte-access-on-halfword:
    description: Allow byte read access on half word devices.
    $ref: /schemas/types.yaml#/definitions/uint32
    enum: [0, 1]

  intel,ixp4xx-eb-hpi-hrdy-pol-high:
    description: Set HPI HRDY polarity to active high when using HPI.
    $ref: /schemas/types.yaml#/definitions/uint32
    enum: [0, 1]

  intel,ixp4xx-eb-mux-address-and-data:
    description: Multiplex address and data on the data bus.
    $ref: /schemas/types.yaml#/definitions/uint32
    enum: [0, 1]

  intel,ixp4xx-eb-ahb-split-transfers:
    description: Enable AHB split transfers.
    $ref: /schemas/types.yaml#/definitions/uint32
    enum: [0, 1]

  intel,ixp4xx-eb-write-enable:
    description: Enable write cycles.
    $ref: /schemas/types.yaml#/definitions/uint32
    enum: [0, 1]

  intel,ixp4xx-eb-byte-access:
    description: Expansion bus uses only 8 bits. The default is to use
      16 bits.
    $ref: /schemas/types.yaml#/definitions/uint32
    enum: [0, 1]

additionalProperties: true