Documentation/devicetree/bindings/pinctrl/qcom,sc7280-pinctrl.yaml

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/qcom,sc7280-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Technologies, Inc. SC7280 TLMM block

maintainers:
  - Bjorn Andersson <andersson@kernel.org>

description:
  Top Level Mode Multiplexer pin controller in Qualcomm SC7280 SoC.

properties:
  compatible:
    const: qcom,sc7280-pinctrl

  reg:
    maxItems: 1

  interrupts:
    description: Specifies the TLMM summary IRQ
    maxItems: 1

  gpio-reserved-ranges:
    minItems: 1
    maxItems: 88

  gpio-line-names:
    maxItems: 175

patternProperties:
  "-state$":
    oneOf:
      - $ref: "#/$defs/qcom-sc7280-tlmm-state"
      - patternProperties:
          "-pins$":
            $ref: "#/$defs/qcom-sc7280-tlmm-state"
        additionalProperties: false

$defs:
  qcom-sc7280-tlmm-state:
    type: object
    description:
      Pinctrl node's client devices use subnodes for desired pin configuration.
      Client device subnodes use below standard properties.
    $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
    unevaluatedProperties: false

    properties:
      pins:
        description:
          List of gpio pins affected by the properties specified in this
          subnode.
        items:
          oneOf:
            - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-6][0-9]|17[0-4])$"
            - enum: [ sdc1_rclk, sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk,
                      sdc2_cmd, sdc2_data, ufs_reset ]
        minItems: 1
        maxItems: 16

      function:
        description:
          Specify the alternative function to be configured for the specified
          pins.

        enum: [ atest_char, atest_char0, atest_char1, atest_char2,
                atest_char3, atest_usb0, atest_usb00, atest_usb01,
                atest_usb02, atest_usb03, atest_usb1, atest_usb10,
                atest_usb11, atest_usb12, atest_usb13, audio_ref,
                cam_mclk, cci_async, cci_i2c, cci_timer0, cci_timer1,
                cci_timer2, cci_timer3, cci_timer4, cmu_rng0, cmu_rng1,
                cmu_rng2, cmu_rng3, coex_uart1, cri_trng, cri_trng0,
                cri_trng1, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1, dp_hot,
                dp_lcd, edp_hot, edp_lcd, gcc_gp1, gcc_gp2, gcc_gp3,
                gpio, host2wlan_sol, ibi_i3c, jitter_bist, lpass_slimbus,
                mdp_vsync, mdp_vsync0, mdp_vsync1, mdp_vsync2, mdp_vsync3,
                mdp_vsync4, mdp_vsync5, mi2s0_data0, mi2s0_data1, mi2s0_sck,
                mi2s0_ws, mi2s1_data0, mi2s1_data1, mi2s1_sck, mi2s1_ws,
                mi2s2_data0, mi2s2_data1, mi2s2_sck, mi2s2_ws, mss_grfc0,
                mss_grfc1, mss_grfc10, mss_grfc11, mss_grfc12, mss_grfc2,
                mss_grfc3, mss_grfc4, mss_grfc5, mss_grfc6, mss_grfc7,
                mss_grfc8, mss_grfc9, nav_gpio0, nav_gpio1, nav_gpio2,
                pa_indicator, pcie0_clkreqn, pcie1_clkreqn, phase_flag,
                pll_bist, pll_bypassnl, pll_clk, pll_reset, pri_mi2s, prng_rosc,
                qdss, qdss_cti, qlink0_enable, qlink0_request, qlink0_wmss,
                qlink1_enable, qlink1_request, qlink1_wmss, qspi_clk, qspi_cs,
                qspi_data, qup00, qup01, qup02, qup03, qup04, qup05, qup06, qup07,
                qup10, qup11, qup12, qup13, qup14, qup15, qup16, qup17,
                sdc40, sdc41, sdc42, sdc43, sdc4_clk, sdc4_cmd, sd_write,
                sec_mi2s, tb_trig, tgu_ch0, tgu_ch1, tsense_pwm1,
                tsense_pwm2, uim0_clk, uim0_data, uim0_present, uim0_reset,
                uim1_clk, uim1_data, uim1_present, uim1_reset, usb2phy_ac,
                usb_phy, vfr_0, vfr_1, vsense_trigger ]

    required:
      - pins

allOf:
  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#

required:
  - compatible
  - reg

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    tlmm: pinctrl@f000000 {
        compatible = "qcom,sc7280-pinctrl";
        reg = <0xf000000 0x1000000>;
        interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
        gpio-controller;
        #gpio-cells = <2>;
        interrupt-controller;
        #interrupt-cells = <2>;
        gpio-ranges = <&tlmm 0 0 175>;
        wakeup-parent = <&pdc>;

        qup_uart5_default: qup-uart5-state {
            pins = "gpio46", "gpio47";
            function = "qup13";
            drive-strength = <2>;
            bias-disable;
        };
    };