| /* |
| * ACP_2_2 Register documentation |
| * |
| * Copyright (C) 2014 Advanced Micro Devices, Inc. |
| * |
| * Permission is hereby granted, free of charge, to any person obtaining a |
| * copy of this software and associated documentation files (the "Software"), |
| * to deal in the Software without restriction, including without limitation |
| * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| * and/or sell copies of the Software, and to permit persons to whom the |
| * Software is furnished to do so, subject to the following conditions: |
| * |
| * The above copyright notice and this permission notice shall be included |
| * in all copies or substantial portions of the Software. |
| * |
| * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
| * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN |
| * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN |
| * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
| */ |
| |
| #ifndef ACP_2_2_SH_MASK_H |
| #define ACP_2_2_SH_MASK_H |
| |
| #define ACP_DMA_CNTL_0__DMAChRst_MASK 0x1 |
| #define ACP_DMA_CNTL_0__DMAChRst__SHIFT 0x0 |
| #define ACP_DMA_CNTL_0__DMAChRun_MASK 0x2 |
| #define ACP_DMA_CNTL_0__DMAChRun__SHIFT 0x1 |
| #define ACP_DMA_CNTL_0__DMAChIOCEn_MASK 0x4 |
| #define ACP_DMA_CNTL_0__DMAChIOCEn__SHIFT 0x2 |
| #define ACP_DMA_CNTL_0__Circular_DMA_En_MASK 0x8 |
| #define ACP_DMA_CNTL_0__Circular_DMA_En__SHIFT 0x3 |
| #define ACP_DMA_CNTL_0__DMAChGracefulRstEn_MASK 0x10 |
| #define ACP_DMA_CNTL_0__DMAChGracefulRstEn__SHIFT 0x4 |
| #define ACP_DMA_CNTL_1__DMAChRst_MASK 0x1 |
| #define ACP_DMA_CNTL_1__DMAChRst__SHIFT 0x0 |
| #define ACP_DMA_CNTL_1__DMAChRun_MASK 0x2 |
| #define ACP_DMA_CNTL_1__DMAChRun__SHIFT 0x1 |
| #define ACP_DMA_CNTL_1__DMAChIOCEn_MASK 0x4 |
| #define ACP_DMA_CNTL_1__DMAChIOCEn__SHIFT 0x2 |
| #define ACP_DMA_CNTL_1__Circular_DMA_En_MASK 0x8 |
| #define ACP_DMA_CNTL_1__Circular_DMA_En__SHIFT 0x3 |
| #define ACP_DMA_CNTL_1__DMAChGracefulRstEn_MASK 0x10 |
| #define ACP_DMA_CNTL_1__DMAChGracefulRstEn__SHIFT 0x4 |
| #define ACP_DMA_CNTL_2__DMAChRst_MASK 0x1 |
| #define ACP_DMA_CNTL_2__DMAChRst__SHIFT 0x0 |
| #define ACP_DMA_CNTL_2__DMAChRun_MASK 0x2 |
| #define ACP_DMA_CNTL_2__DMAChRun__SHIFT 0x1 |
| #define ACP_DMA_CNTL_2__DMAChIOCEn_MASK 0x4 |
| #define ACP_DMA_CNTL_2__DMAChIOCEn__SHIFT 0x2 |
| #define ACP_DMA_CNTL_2__Circular_DMA_En_MASK 0x8 |
| #define ACP_DMA_CNTL_2__Circular_DMA_En__SHIFT 0x3 |
| #define ACP_DMA_CNTL_2__DMAChGracefulRstEn_MASK 0x10 |
| #define ACP_DMA_CNTL_2__DMAChGracefulRstEn__SHIFT 0x4 |
| #define ACP_DMA_CNTL_3__DMAChRst_MASK 0x1 |
| #define ACP_DMA_CNTL_3__DMAChRst__SHIFT 0x0 |
| #define ACP_DMA_CNTL_3__DMAChRun_MASK 0x2 |
| #define ACP_DMA_CNTL_3__DMAChRun__SHIFT 0x1 |
| #define ACP_DMA_CNTL_3__DMAChIOCEn_MASK 0x4 |
| #define ACP_DMA_CNTL_3__DMAChIOCEn__SHIFT 0x2 |
| #define ACP_DMA_CNTL_3__Circular_DMA_En_MASK 0x8 |
| #define ACP_DMA_CNTL_3__Circular_DMA_En__SHIFT 0x3 |
| #define ACP_DMA_CNTL_3__DMAChGracefulRstEn_MASK 0x10 |
| #define ACP_DMA_CNTL_3__DMAChGracefulRstEn__SHIFT 0x4 |
| #define ACP_DMA_CNTL_4__DMAChRst_MASK 0x1 |
| #define ACP_DMA_CNTL_4__DMAChRst__SHIFT 0x0 |
| #define ACP_DMA_CNTL_4__DMAChRun_MASK 0x2 |
| #define ACP_DMA_CNTL_4__DMAChRun__SHIFT 0x1 |
| #define ACP_DMA_CNTL_4__DMAChIOCEn_MASK 0x4 |
| #define ACP_DMA_CNTL_4__DMAChIOCEn__SHIFT 0x2 |
| #define ACP_DMA_CNTL_4__Circular_DMA_En_MASK 0x8 |
| #define ACP_DMA_CNTL_4__Circular_DMA_En__SHIFT 0x3 |
| #define ACP_DMA_CNTL_4__DMAChGracefulRstEn_MASK 0x10 |
| #define ACP_DMA_CNTL_4__DMAChGracefulRstEn__SHIFT 0x4 |
| #define ACP_DMA_CNTL_5__DMAChRst_MASK 0x1 |
| #define ACP_DMA_CNTL_5__DMAChRst__SHIFT 0x0 |
| #define ACP_DMA_CNTL_5__DMAChRun_MASK 0x2 |
| #define ACP_DMA_CNTL_5__DMAChRun__SHIFT 0x1 |
| #define ACP_DMA_CNTL_5__DMAChIOCEn_MASK 0x4 |
| #define ACP_DMA_CNTL_5__DMAChIOCEn__SHIFT 0x2 |
| #define ACP_DMA_CNTL_5__Circular_DMA_En_MASK 0x8 |
| #define ACP_DMA_CNTL_5__Circular_DMA_En__SHIFT 0x3 |
| #define ACP_DMA_CNTL_5__DMAChGracefulRstEn_MASK 0x10 |
| #define ACP_DMA_CNTL_5__DMAChGracefulRstEn__SHIFT 0x4 |
| #define ACP_DMA_CNTL_6__DMAChRst_MASK 0x1 |
| #define ACP_DMA_CNTL_6__DMAChRst__SHIFT 0x0 |
| #define ACP_DMA_CNTL_6__DMAChRun_MASK 0x2 |
| #define ACP_DMA_CNTL_6__DMAChRun__SHIFT 0x1 |
| #define ACP_DMA_CNTL_6__DMAChIOCEn_MASK 0x4 |
| #define ACP_DMA_CNTL_6__DMAChIOCEn__SHIFT 0x2 |
| #define ACP_DMA_CNTL_6__Circular_DMA_En_MASK 0x8 |
| #define ACP_DMA_CNTL_6__Circular_DMA_En__SHIFT 0x3 |
| #define ACP_DMA_CNTL_6__DMAChGracefulRstEn_MASK 0x10 |
| #define ACP_DMA_CNTL_6__DMAChGracefulRstEn__SHIFT 0x4 |
| #define ACP_DMA_CNTL_7__DMAChRst_MASK 0x1 |
| #define ACP_DMA_CNTL_7__DMAChRst__SHIFT 0x0 |
| #define ACP_DMA_CNTL_7__DMAChRun_MASK 0x2 |
| #define ACP_DMA_CNTL_7__DMAChRun__SHIFT 0x1 |
| #define ACP_DMA_CNTL_7__DMAChIOCEn_MASK 0x4 |
| #define ACP_DMA_CNTL_7__DMAChIOCEn__SHIFT 0x2 |
| #define ACP_DMA_CNTL_7__Circular_DMA_En_MASK 0x8 |
| #define ACP_DMA_CNTL_7__Circular_DMA_En__SHIFT 0x3 |
| #define ACP_DMA_CNTL_7__DMAChGracefulRstEn_MASK 0x10 |
| #define ACP_DMA_CNTL_7__DMAChGracefulRstEn__SHIFT 0x4 |
| #define ACP_DMA_CNTL_8__DMAChRst_MASK 0x1 |
| #define ACP_DMA_CNTL_8__DMAChRst__SHIFT 0x0 |
| #define ACP_DMA_CNTL_8__DMAChRun_MASK 0x2 |
| #define ACP_DMA_CNTL_8__DMAChRun__SHIFT 0x1 |
| #define ACP_DMA_CNTL_8__DMAChIOCEn_MASK 0x4 |
| #define ACP_DMA_CNTL_8__DMAChIOCEn__SHIFT 0x2 |
| #define ACP_DMA_CNTL_8__Circular_DMA_En_MASK 0x8 |
| #define ACP_DMA_CNTL_8__Circular_DMA_En__SHIFT 0x3 |
| #define ACP_DMA_CNTL_8__DMAChGracefulRstEn_MASK 0x10 |
| #define ACP_DMA_CNTL_8__DMAChGracefulRstEn__SHIFT 0x4 |
| #define ACP_DMA_CNTL_9__DMAChRst_MASK 0x1 |
| #define ACP_DMA_CNTL_9__DMAChRst__SHIFT 0x0 |
| #define ACP_DMA_CNTL_9__DMAChRun_MASK 0x2 |
| #define ACP_DMA_CNTL_9__DMAChRun__SHIFT 0x1 |
| #define ACP_DMA_CNTL_9__DMAChIOCEn_MASK 0x4 |
| #define ACP_DMA_CNTL_9__DMAChIOCEn__SHIFT 0x2 |
| #define ACP_DMA_CNTL_9__Circular_DMA_En_MASK 0x8 |
| #define ACP_DMA_CNTL_9__Circular_DMA_En__SHIFT 0x3 |
| #define ACP_DMA_CNTL_9__DMAChGracefulRstEn_MASK 0x10 |
| #define ACP_DMA_CNTL_9__DMAChGracefulRstEn__SHIFT 0x4 |
| #define ACP_DMA_CNTL_10__DMAChRst_MASK 0x1 |
| #define ACP_DMA_CNTL_10__DMAChRst__SHIFT 0x0 |
| #define ACP_DMA_CNTL_10__DMAChRun_MASK 0x2 |
| #define ACP_DMA_CNTL_10__DMAChRun__SHIFT 0x1 |
| #define ACP_DMA_CNTL_10__DMAChIOCEn_MASK 0x4 |
| #define ACP_DMA_CNTL_10__DMAChIOCEn__SHIFT 0x2 |
| #define ACP_DMA_CNTL_10__Circular_DMA_En_MASK 0x8 |
| #define ACP_DMA_CNTL_10__Circular_DMA_En__SHIFT 0x3 |
| #define ACP_DMA_CNTL_10__DMAChGracefulRstEn_MASK 0x10 |
| #define ACP_DMA_CNTL_10__DMAChGracefulRstEn__SHIFT 0x4 |
| #define ACP_DMA_CNTL_11__DMAChRst_MASK 0x1 |
| #define ACP_DMA_CNTL_11__DMAChRst__SHIFT 0x0 |
| #define ACP_DMA_CNTL_11__DMAChRun_MASK 0x2 |
| #define ACP_DMA_CNTL_11__DMAChRun__SHIFT 0x1 |
| #define ACP_DMA_CNTL_11__DMAChIOCEn_MASK 0x4 |
| #define ACP_DMA_CNTL_11__DMAChIOCEn__SHIFT 0x2 |
| #define ACP_DMA_CNTL_11__Circular_DMA_En_MASK 0x8 |
| #define ACP_DMA_CNTL_11__Circular_DMA_En__SHIFT 0x3 |
| #define ACP_DMA_CNTL_11__DMAChGracefulRstEn_MASK 0x10 |
| #define ACP_DMA_CNTL_11__DMAChGracefulRstEn__SHIFT 0x4 |
| #define ACP_DMA_CNTL_12__DMAChRst_MASK 0x1 |
| #define ACP_DMA_CNTL_12__DMAChRst__SHIFT 0x0 |
| #define ACP_DMA_CNTL_12__DMAChRun_MASK 0x2 |
| #define ACP_DMA_CNTL_12__DMAChRun__SHIFT 0x1 |
| #define ACP_DMA_CNTL_12__DMAChIOCEn_MASK 0x4 |
| #define ACP_DMA_CNTL_12__DMAChIOCEn__SHIFT 0x2 |
| #define ACP_DMA_CNTL_12__Circular_DMA_En_MASK 0x8 |
| #define ACP_DMA_CNTL_12__Circular_DMA_En__SHIFT 0x3 |
| #define ACP_DMA_CNTL_12__DMAChGracefulRstEn_MASK 0x10 |
| #define ACP_DMA_CNTL_12__DMAChGracefulRstEn__SHIFT 0x4 |
| #define ACP_DMA_CNTL_13__DMAChRst_MASK 0x1 |
| #define ACP_DMA_CNTL_13__DMAChRst__SHIFT 0x0 |
| #define ACP_DMA_CNTL_13__DMAChRun_MASK 0x2 |
| #define ACP_DMA_CNTL_13__DMAChRun__SHIFT 0x1 |
| #define ACP_DMA_CNTL_13__DMAChIOCEn_MASK 0x4 |
| #define ACP_DMA_CNTL_13__DMAChIOCEn__SHIFT 0x2 |
| #define ACP_DMA_CNTL_13__Circular_DMA_En_MASK 0x8 |
| #define ACP_DMA_CNTL_13__Circular_DMA_En__SHIFT 0x3 |
| #define ACP_DMA_CNTL_13__DMAChGracefulRstEn_MASK 0x10 |
| #define ACP_DMA_CNTL_13__DMAChGracefulRstEn__SHIFT 0x4 |
| #define ACP_DMA_CNTL_14__DMAChRst_MASK 0x1 |
| #define ACP_DMA_CNTL_14__DMAChRst__SHIFT 0x0 |
| #define ACP_DMA_CNTL_14__DMAChRun_MASK 0x2 |
| #define ACP_DMA_CNTL_14__DMAChRun__SHIFT 0x1 |
| #define ACP_DMA_CNTL_14__DMAChIOCEn_MASK 0x4 |
| #define ACP_DMA_CNTL_14__DMAChIOCEn__SHIFT 0x2 |
| #define ACP_DMA_CNTL_14__Circular_DMA_En_MASK 0x8 |
| #define ACP_DMA_CNTL_14__Circular_DMA_En__SHIFT 0x3 |
| #define ACP_DMA_CNTL_14__DMAChGracefulRstEn_MASK 0x10 |
| #define ACP_DMA_CNTL_14__DMAChGracefulRstEn__SHIFT 0x4 |
| #define ACP_DMA_CNTL_15__DMAChRst_MASK 0x1 |
| #define ACP_DMA_CNTL_15__DMAChRst__SHIFT 0x0 |
| #define ACP_DMA_CNTL_15__DMAChRun_MASK 0x2 |
| #define ACP_DMA_CNTL_15__DMAChRun__SHIFT 0x1 |
| #define ACP_DMA_CNTL_15__DMAChIOCEn_MASK 0x4 |
| #define ACP_DMA_CNTL_15__DMAChIOCEn__SHIFT 0x2 |
| #define ACP_DMA_CNTL_15__Circular_DMA_En_MASK 0x8 |
| #define ACP_DMA_CNTL_15__Circular_DMA_En__SHIFT 0x3 |
| #define ACP_DMA_CNTL_15__DMAChGracefulRstEn_MASK 0x10 |
| #define ACP_DMA_CNTL_15__DMAChGracefulRstEn__SHIFT 0x4 |
| #define ACP_DMA_DSCR_STRT_IDX_0__DMAChDscrStrtIdx_MASK 0x3ff |
| #define ACP_DMA_DSCR_STRT_IDX_0__DMAChDscrStrtIdx__SHIFT 0x0 |
| #define ACP_DMA_DSCR_STRT_IDX_1__DMAChDscrStrtIdx_MASK 0x3ff |
| #define ACP_DMA_DSCR_STRT_IDX_1__DMAChDscrStrtIdx__SHIFT 0x0 |
| #define ACP_DMA_DSCR_STRT_IDX_2__DMAChDscrStrtIdx_MASK 0x3ff |
| #define ACP_DMA_DSCR_STRT_IDX_2__DMAChDscrStrtIdx__SHIFT 0x0 |
| #define ACP_DMA_DSCR_STRT_IDX_3__DMAChDscrStrtIdx_MASK 0x3ff |
| #define ACP_DMA_DSCR_STRT_IDX_3__DMAChDscrStrtIdx__SHIFT 0x0 |
| #define ACP_DMA_DSCR_STRT_IDX_4__DMAChDscrStrtIdx_MASK 0x3ff |
| #define ACP_DMA_DSCR_STRT_IDX_4__DMAChDscrStrtIdx__SHIFT 0x0 |
| #define ACP_DMA_DSCR_STRT_IDX_5__DMAChDscrStrtIdx_MASK 0x3ff |
| #define ACP_DMA_DSCR_STRT_IDX_5__DMAChDscrStrtIdx__SHIFT 0x0 |
| #define ACP_DMA_DSCR_STRT_IDX_6__DMAChDscrStrtIdx_MASK 0x3ff |
| #define ACP_DMA_DSCR_STRT_IDX_6__DMAChDscrStrtIdx__SHIFT 0x0 |
| #define ACP_DMA_DSCR_STRT_IDX_7__DMAChDscrStrtIdx_MASK 0x3ff |
| #define ACP_DMA_DSCR_STRT_IDX_7__DMAChDscrStrtIdx__SHIFT 0x0 |
| #define ACP_DMA_DSCR_STRT_IDX_8__DMAChDscrStrtIdx_MASK 0x3ff |
| #define ACP_DMA_DSCR_STRT_IDX_8__DMAChDscrStrtIdx__SHIFT 0x0 |
| #define ACP_DMA_DSCR_STRT_IDX_9__DMAChDscrStrtIdx_MASK 0x3ff |
| #define ACP_DMA_DSCR_STRT_IDX_9__DMAChDscrStrtIdx__SHIFT 0x0 |
| #define ACP_DMA_DSCR_STRT_IDX_10__DMAChDscrStrtIdx_MASK 0x3ff |
| #define ACP_DMA_DSCR_STRT_IDX_10__DMAChDscrStrtIdx__SHIFT 0x0 |
| #define ACP_DMA_DSCR_STRT_IDX_11__DMAChDscrStrtIdx_MASK 0x3ff |
| #define ACP_DMA_DSCR_STRT_IDX_11__DMAChDscrStrtIdx__SHIFT 0x0 |
| #define ACP_DMA_DSCR_STRT_IDX_12__DMAChDscrStrtIdx_MASK 0x3ff |
| #define ACP_DMA_DSCR_STRT_IDX_12__DMAChDscrStrtIdx__SHIFT 0x0 |
| #define ACP_DMA_DSCR_STRT_IDX_13__DMAChDscrStrtIdx_MASK 0x3ff |
| #define ACP_DMA_DSCR_STRT_IDX_13__DMAChDscrStrtIdx__SHIFT 0x0 |
| #define ACP_DMA_DSCR_STRT_IDX_14__DMAChDscrStrtIdx_MASK 0x3ff |
| #define ACP_DMA_DSCR_STRT_IDX_14__DMAChDscrStrtIdx__SHIFT 0x0 |
| #define ACP_DMA_DSCR_STRT_IDX_15__DMAChDscrStrtIdx_MASK 0x3ff |
| #define ACP_DMA_DSCR_STRT_IDX_15__DMAChDscrStrtIdx__SHIFT 0x0 |
| #define ACP_DMA_DSCR_CNT_0__DMAChDscrCnt_MASK 0x3ff |
| #define ACP_DMA_DSCR_CNT_0__DMAChDscrCnt__SHIFT 0x0 |
| #define ACP_DMA_DSCR_CNT_1__DMAChDscrCnt_MASK 0x3ff |
| #define ACP_DMA_DSCR_CNT_1__DMAChDscrCnt__SHIFT 0x0 |
| #define ACP_DMA_DSCR_CNT_2__DMAChDscrCnt_MASK 0x3ff |
| #define ACP_DMA_DSCR_CNT_2__DMAChDscrCnt__SHIFT 0x0 |
| #define ACP_DMA_DSCR_CNT_3__DMAChDscrCnt_MASK 0x3ff |
| #define ACP_DMA_DSCR_CNT_3__DMAChDscrCnt__SHIFT 0x0 |
| #define ACP_DMA_DSCR_CNT_4__DMAChDscrCnt_MASK 0x3ff |
| #define ACP_DMA_DSCR_CNT_4__DMAChDscrCnt__SHIFT 0x0 |
| #define ACP_DMA_DSCR_CNT_5__DMAChDscrCnt_MASK 0x3ff |
| #define ACP_DMA_DSCR_CNT_5__DMAChDscrCnt__SHIFT 0x0 |
| #define ACP_DMA_DSCR_CNT_6__DMAChDscrCnt_MASK 0x3ff |
| #define ACP_DMA_DSCR_CNT_6__DMAChDscrCnt__SHIFT 0x0 |
| #define ACP_DMA_DSCR_CNT_7__DMAChDscrCnt_MASK 0x3ff |
| #define ACP_DMA_DSCR_CNT_7__DMAChDscrCnt__SHIFT 0x0 |
| #define ACP_DMA_DSCR_CNT_8__DMAChDscrCnt_MASK 0x3ff |
| #define ACP_DMA_DSCR_CNT_8__DMAChDscrCnt__SHIFT 0x0 |
| #define ACP_DMA_DSCR_CNT_9__DMAChDscrCnt_MASK 0x3ff |
| #define ACP_DMA_DSCR_CNT_9__DMAChDscrCnt__SHIFT 0x0 |
| #define ACP_DMA_DSCR_CNT_10__DMAChDscrCnt_MASK 0x3ff |
| #define ACP_DMA_DSCR_CNT_10__DMAChDscrCnt__SHIFT 0x0 |
| #define ACP_DMA_DSCR_CNT_11__DMAChDscrCnt_MASK 0x3ff |
| #define ACP_DMA_DSCR_CNT_11__DMAChDscrCnt__SHIFT 0x0 |
| #define ACP_DMA_DSCR_CNT_12__DMAChDscrCnt_MASK 0x3ff |
| #define ACP_DMA_DSCR_CNT_12__DMAChDscrCnt__SHIFT 0x0 |
| #define ACP_DMA_DSCR_CNT_13__DMAChDscrCnt_MASK 0x3ff |
| #define ACP_DMA_DSCR_CNT_13__DMAChDscrCnt__SHIFT 0x0 |
| #define ACP_DMA_DSCR_CNT_14__DMAChDscrCnt_MASK 0x3ff |
| #define ACP_DMA_DSCR_CNT_14__DMAChDscrCnt__SHIFT 0x0 |
| #define ACP_DMA_DSCR_CNT_15__DMAChDscrCnt_MASK 0x3ff |
| #define ACP_DMA_DSCR_CNT_15__DMAChDscrCnt__SHIFT 0x0 |
| #define ACP_DMA_PRIO_0__DMAChPrioLvl_MASK 0x1 |
| #define ACP_DMA_PRIO_0__DMAChPrioLvl__SHIFT 0x0 |
| #define ACP_DMA_PRIO_1__DMAChPrioLvl_MASK 0x1 |
| #define ACP_DMA_PRIO_1__DMAChPrioLvl__SHIFT 0x0 |
| #define ACP_DMA_PRIO_2__DMAChPrioLvl_MASK 0x1 |
| #define ACP_DMA_PRIO_2__DMAChPrioLvl__SHIFT 0x0 |
| #define ACP_DMA_PRIO_3__DMAChPrioLvl_MASK 0x1 |
| #define ACP_DMA_PRIO_3__DMAChPrioLvl__SHIFT 0x0 |
| #define ACP_DMA_PRIO_4__DMAChPrioLvl_MASK 0x1 |
| #define ACP_DMA_PRIO_4__DMAChPrioLvl__SHIFT 0x0 |
| #define ACP_DMA_PRIO_5__DMAChPrioLvl_MASK 0x1 |
| #define ACP_DMA_PRIO_5__DMAChPrioLvl__SHIFT 0x0 |
| #define ACP_DMA_PRIO_6__DMAChPrioLvl_MASK 0x1 |
| #define ACP_DMA_PRIO_6__DMAChPrioLvl__SHIFT 0x0 |
| #define ACP_DMA_PRIO_7__DMAChPrioLvl_MASK 0x1 |
| #define ACP_DMA_PRIO_7__DMAChPrioLvl__SHIFT 0x0 |
| #define ACP_DMA_PRIO_8__DMAChPrioLvl_MASK 0x1 |
| #define ACP_DMA_PRIO_8__DMAChPrioLvl__SHIFT 0x0 |
| #define ACP_DMA_PRIO_9__DMAChPrioLvl_MASK 0x1 |
| #define ACP_DMA_PRIO_9__DMAChPrioLvl__SHIFT 0x0 |
| #define ACP_DMA_PRIO_10__DMAChPrioLvl_MASK 0x1 |
| #define ACP_DMA_PRIO_10__DMAChPrioLvl__SHIFT 0x0 |
| #define ACP_DMA_PRIO_11__DMAChPrioLvl_MASK 0x1 |
| #define ACP_DMA_PRIO_11__DMAChPrioLvl__SHIFT 0x0 |
| #define ACP_DMA_PRIO_12__DMAChPrioLvl_MASK 0x1 |
| #define ACP_DMA_PRIO_12__DMAChPrioLvl__SHIFT 0x0 |
| #define ACP_DMA_PRIO_13__DMAChPrioLvl_MASK 0x1 |
| #define ACP_DMA_PRIO_13__DMAChPrioLvl__SHIFT 0x0 |
| #define ACP_DMA_PRIO_14__DMAChPrioLvl_MASK 0x1 |
| #define ACP_DMA_PRIO_14__DMAChPrioLvl__SHIFT 0x0 |
| #define ACP_DMA_PRIO_15__DMAChPrioLvl_MASK 0x1 |
| #define ACP_DMA_PRIO_15__DMAChPrioLvl__SHIFT 0x0 |
| #define ACP_DMA_CUR_DSCR_0__DMAChCurDscrIdx_MASK 0x3ff |
| #define ACP_DMA_CUR_DSCR_0__DMAChCurDscrIdx__SHIFT 0x0 |
| #define ACP_DMA_CUR_DSCR_1__DMAChCurDscrIdx_MASK 0x3ff |
| #define ACP_DMA_CUR_DSCR_1__DMAChCurDscrIdx__SHIFT 0x0 |
| #define ACP_DMA_CUR_DSCR_2__DMAChCurDscrIdx_MASK 0x3ff |
| #define ACP_DMA_CUR_DSCR_2__DMAChCurDscrIdx__SHIFT 0x0 |
| #define ACP_DMA_CUR_DSCR_3__DMAChCurDscrIdx_MASK 0x3ff |
| #define ACP_DMA_CUR_DSCR_3__DMAChCurDscrIdx__SHIFT 0x0 |
| #define ACP_DMA_CUR_DSCR_4__DMAChCurDscrIdx_MASK 0x3ff |
| #define ACP_DMA_CUR_DSCR_4__DMAChCurDscrIdx__SHIFT 0x0 |
| #define ACP_DMA_CUR_DSCR_5__DMAChCurDscrIdx_MASK 0x3ff |
| #define ACP_DMA_CUR_DSCR_5__DMAChCurDscrIdx__SHIFT 0x0 |
| #define ACP_DMA_CUR_DSCR_6__DMAChCurDscrIdx_MASK 0x3ff |
| #define ACP_DMA_CUR_DSCR_6__DMAChCurDscrIdx__SHIFT 0x0 |
| #define ACP_DMA_CUR_DSCR_7__DMAChCurDscrIdx_MASK 0x3ff |
| #define ACP_DMA_CUR_DSCR_7__DMAChCurDscrIdx__SHIFT 0x0 |
| #define ACP_DMA_CUR_DSCR_8__DMAChCurDscrIdx_MASK 0x3ff |
| #define ACP_DMA_CUR_DSCR_8__DMAChCurDscrIdx__SHIFT 0x0 |
| #define ACP_DMA_CUR_DSCR_9__DMAChCurDscrIdx_MASK 0x3ff |
| #define ACP_DMA_CUR_DSCR_9__DMAChCurDscrIdx__SHIFT 0x0 |
| #define ACP_DMA_CUR_DSCR_10__DMAChCurDscrIdx_MASK 0x3ff |
| #define ACP_DMA_CUR_DSCR_10__DMAChCurDscrIdx__SHIFT 0x0 |
| #define ACP_DMA_CUR_DSCR_11__DMAChCurDscrIdx_MASK 0x3ff |
| #define ACP_DMA_CUR_DSCR_11__DMAChCurDscrIdx__SHIFT 0x0 |
| #define ACP_DMA_CUR_DSCR_12__DMAChCurDscrIdx_MASK 0x3ff |
| #define ACP_DMA_CUR_DSCR_12__DMAChCurDscrIdx__SHIFT 0x0 |
| #define ACP_DMA_CUR_DSCR_13__DMAChCurDscrIdx_MASK 0x3ff |
| #define ACP_DMA_CUR_DSCR_13__DMAChCurDscrIdx__SHIFT 0x0 |
| #define ACP_DMA_CUR_DSCR_14__DMAChCurDscrIdx_MASK 0x3ff |
| #define ACP_DMA_CUR_DSCR_14__DMAChCurDscrIdx__SHIFT 0x0 |
| #define ACP_DMA_CUR_DSCR_15__DMAChCurDscrIdx_MASK 0x3ff |
| #define ACP_DMA_CUR_DSCR_15__DMAChCurDscrIdx__SHIFT 0x0 |
| #define ACP_DMA_CUR_TRANS_CNT_0__DMAChCurTransCnt_MASK 0x1ffff |
| #define ACP_DMA_CUR_TRANS_CNT_0__DMAChCurTransCnt__SHIFT 0x0 |
| #define ACP_DMA_CUR_TRANS_CNT_1__DMAChCurTransCnt_MASK 0x1ffff |
| #define ACP_DMA_CUR_TRANS_CNT_1__DMAChCurTransCnt__SHIFT 0x0 |
| #define ACP_DMA_CUR_TRANS_CNT_2__DMAChCurTransCnt_MASK 0x1ffff |
| #define ACP_DMA_CUR_TRANS_CNT_2__DMAChCurTransCnt__SHIFT 0x0 |
| #define ACP_DMA_CUR_TRANS_CNT_3__DMAChCurTransCnt_MASK 0x1ffff |
| #define ACP_DMA_CUR_TRANS_CNT_3__DMAChCurTransCnt__SHIFT 0x0 |
| #define ACP_DMA_CUR_TRANS_CNT_4__DMAChCurTransCnt_MASK 0x1ffff |
| #define ACP_DMA_CUR_TRANS_CNT_4__DMAChCurTransCnt__SHIFT 0x0 |
| #define ACP_DMA_CUR_TRANS_CNT_5__DMAChCurTransCnt_MASK 0x1ffff |
| #define ACP_DMA_CUR_TRANS_CNT_5__DMAChCurTransCnt__SHIFT 0x0 |
| #define ACP_DMA_CUR_TRANS_CNT_6__DMAChCurTransCnt_MASK 0x1ffff |
| #define ACP_DMA_CUR_TRANS_CNT_6__DMAChCurTransCnt__SHIFT 0x0 |
| #define ACP_DMA_CUR_TRANS_CNT_7__DMAChCurTransCnt_MASK 0x1ffff |
| #define ACP_DMA_CUR_TRANS_CNT_7__DMAChCurTransCnt__SHIFT 0x0 |
| #define ACP_DMA_CUR_TRANS_CNT_8__DMAChCurTransCnt_MASK 0x1ffff |
| #define ACP_DMA_CUR_TRANS_CNT_8__DMAChCurTransCnt__SHIFT 0x0 |
| #define ACP_DMA_CUR_TRANS_CNT_9__DMAChCurTransCnt_MASK 0x1ffff |
| #define ACP_DMA_CUR_TRANS_CNT_9__DMAChCurTransCnt__SHIFT 0x0 |
| #define ACP_DMA_CUR_TRANS_CNT_10__DMAChCurTransCnt_MASK 0x1ffff |
| #define ACP_DMA_CUR_TRANS_CNT_10__DMAChCurTransCnt__SHIFT 0x0 |
| #define ACP_DMA_CUR_TRANS_CNT_11__DMAChCurTransCnt_MASK 0x1ffff |
| #define ACP_DMA_CUR_TRANS_CNT_11__DMAChCurTransCnt__SHIFT 0x0 |
| #define ACP_DMA_CUR_TRANS_CNT_12__DMAChCurTransCnt_MASK 0x1ffff |
| #define ACP_DMA_CUR_TRANS_CNT_12__DMAChCurTransCnt__SHIFT 0x0 |
| #define ACP_DMA_CUR_TRANS_CNT_13__DMAChCurTransCnt_MASK 0x1ffff |
| #define ACP_DMA_CUR_TRANS_CNT_13__DMAChCurTransCnt__SHIFT 0x0 |
| #define ACP_DMA_CUR_TRANS_CNT_14__DMAChCurTransCnt_MASK 0x1ffff |
| #define ACP_DMA_CUR_TRANS_CNT_14__DMAChCurTransCnt__SHIFT 0x0 |
| #define ACP_DMA_CUR_TRANS_CNT_15__DMAChCurTransCnt_MASK 0x1ffff |
| #define ACP_DMA_CUR_TRANS_CNT_15__DMAChCurTransCnt__SHIFT 0x0 |
| #define ACP_DMA_ERR_STS_0__DMAChTermErr_MASK 0x1 |
| #define ACP_DMA_ERR_STS_0__DMAChTermErr__SHIFT 0x0 |
| #define ACP_DMA_ERR_STS_0__DMAChErrCode_MASK 0x1e |
| #define ACP_DMA_ERR_STS_0__DMAChErrCode__SHIFT 0x1 |
| #define ACP_DMA_ERR_STS_1__DMAChTermErr_MASK 0x1 |
| #define ACP_DMA_ERR_STS_1__DMAChTermErr__SHIFT 0x0 |
| #define ACP_DMA_ERR_STS_1__DMAChErrCode_MASK 0x1e |
| #define ACP_DMA_ERR_STS_1__DMAChErrCode__SHIFT 0x1 |
| #define ACP_DMA_ERR_STS_2__DMAChTermErr_MASK 0x1 |
| #define ACP_DMA_ERR_STS_2__DMAChTermErr__SHIFT 0x0 |
| #define ACP_DMA_ERR_STS_2__DMAChErrCode_MASK 0x1e |
| #define ACP_DMA_ERR_STS_2__DMAChErrCode__SHIFT 0x1 |
| #define ACP_DMA_ERR_STS_3__DMAChTermErr_MASK 0x1 |
| #define ACP_DMA_ERR_STS_3__DMAChTermErr__SHIFT 0x0 |
| #define ACP_DMA_ERR_STS_3__DMAChErrCode_MASK 0x1e |
| #define ACP_DMA_ERR_STS_3__DMAChErrCode__SHIFT 0x1 |
| #define ACP_DMA_ERR_STS_4__DMAChTermErr_MASK 0x1 |
| #define ACP_DMA_ERR_STS_4__DMAChTermErr__SHIFT 0x0 |
| #define ACP_DMA_ERR_STS_4__DMAChErrCode_MASK 0x1e |
| #define ACP_DMA_ERR_STS_4__DMAChErrCode__SHIFT 0x1 |
| #define ACP_DMA_ERR_STS_5__DMAChTermErr_MASK 0x1 |
| #define ACP_DMA_ERR_STS_5__DMAChTermErr__SHIFT 0x0 |
| #define ACP_DMA_ERR_STS_5__DMAChErrCode_MASK 0x1e |
| #define ACP_DMA_ERR_STS_5__DMAChErrCode__SHIFT 0x1 |
| #define ACP_DMA_ERR_STS_6__DMAChTermErr_MASK 0x1 |
| #define ACP_DMA_ERR_STS_6__DMAChTermErr__SHIFT 0x0 |
| #define ACP_DMA_ERR_STS_6__DMAChErrCode_MASK 0x1e |
| #define ACP_DMA_ERR_STS_6__DMAChErrCode__SHIFT 0x1 |
| #define ACP_DMA_ERR_STS_7__DMAChTermErr_MASK 0x1 |
| #define ACP_DMA_ERR_STS_7__DMAChTermErr__SHIFT 0x0 |
| #define ACP_DMA_ERR_STS_7__DMAChErrCode_MASK 0x1e |
| #define ACP_DMA_ERR_STS_7__DMAChErrCode__SHIFT 0x1 |
| #define ACP_DMA_ERR_STS_8__DMAChTermErr_MASK 0x1 |
| #define ACP_DMA_ERR_STS_8__DMAChTermErr__SHIFT 0x0 |
| #define ACP_DMA_ERR_STS_8__DMAChErrCode_MASK 0x1e |
| #define ACP_DMA_ERR_STS_8__DMAChErrCode__SHIFT 0x1 |
| #define ACP_DMA_ERR_STS_9__DMAChTermErr_MASK 0x1 |
| #define ACP_DMA_ERR_STS_9__DMAChTermErr__SHIFT 0x0 |
| #define ACP_DMA_ERR_STS_9__DMAChErrCode_MASK 0x1e |
| #define ACP_DMA_ERR_STS_9__DMAChErrCode__SHIFT 0x1 |
| #define ACP_DMA_ERR_STS_10__DMAChTermErr_MASK 0x1 |
| #define ACP_DMA_ERR_STS_10__DMAChTermErr__SHIFT 0x0 |
| #define ACP_DMA_ERR_STS_10__DMAChErrCode_MASK 0x1e |
| #define ACP_DMA_ERR_STS_10__DMAChErrCode__SHIFT 0x1 |
| #define ACP_DMA_ERR_STS_11__DMAChTermErr_MASK 0x1 |
| #define ACP_DMA_ERR_STS_11__DMAChTermErr__SHIFT 0x0 |
| #define ACP_DMA_ERR_STS_11__DMAChErrCode_MASK 0x1e |
| #define ACP_DMA_ERR_STS_11__DMAChErrCode__SHIFT 0x1 |
| #define ACP_DMA_ERR_STS_12__DMAChTermErr_MASK 0x1 |
| #define ACP_DMA_ERR_STS_12__DMAChTermErr__SHIFT 0x0 |
| #define ACP_DMA_ERR_STS_12__DMAChErrCode_MASK 0x1e |
| #define ACP_DMA_ERR_STS_12__DMAChErrCode__SHIFT 0x1 |
| #define ACP_DMA_ERR_STS_13__DMAChTermErr_MASK 0x1 |
| #define ACP_DMA_ERR_STS_13__DMAChTermErr__SHIFT 0x0 |
| #define ACP_DMA_ERR_STS_13__DMAChErrCode_MASK 0x1e |
| #define ACP_DMA_ERR_STS_13__DMAChErrCode__SHIFT 0x1 |
| #define ACP_DMA_ERR_STS_14__DMAChTermErr_MASK 0x1 |
| #define ACP_DMA_ERR_STS_14__DMAChTermErr__SHIFT 0x0 |
| #define ACP_DMA_ERR_STS_14__DMAChErrCode_MASK 0x1e |
| #define ACP_DMA_ERR_STS_14__DMAChErrCode__SHIFT 0x1 |
| #define ACP_DMA_ERR_STS_15__DMAChTermErr_MASK 0x1 |
| #define ACP_DMA_ERR_STS_15__DMAChTermErr__SHIFT 0x0 |
| #define ACP_DMA_ERR_STS_15__DMAChErrCode_MASK 0x1e |
| #define ACP_DMA_ERR_STS_15__DMAChErrCode__SHIFT 0x1 |
| #define ACP_DMA_DESC_BASE_ADDR__DescriptorBaseAddr_MASK 0xffffffff |
| #define ACP_DMA_DESC_BASE_ADDR__DescriptorBaseAddr__SHIFT 0x0 |
| #define ACP_DMA_DESC_MAX_NUM_DSCR__MaximumNumberDescr_MASK 0xf |
| #define ACP_DMA_DESC_MAX_NUM_DSCR__MaximumNumberDescr__SHIFT 0x0 |
| #define ACP_DMA_CH_STS__DMAChSts_MASK 0xffff |
| #define ACP_DMA_CH_STS__DMAChSts__SHIFT 0x0 |
| #define ACP_DMA_CH_GROUP__DMAChanelGrouping_MASK 0x1 |
| #define ACP_DMA_CH_GROUP__DMAChanelGrouping__SHIFT 0x0 |
| #define ACP_DSP0_CACHE_OFFSET0__Offset_MASK 0xfffffff |
| #define ACP_DSP0_CACHE_OFFSET0__Offset__SHIFT 0x0 |
| #define ACP_DSP0_CACHE_OFFSET0__OnionGarlicSel_MASK 0x80000000 |
| #define ACP_DSP0_CACHE_OFFSET0__OnionGarlicSel__SHIFT 0x1f |
| #define ACP_DSP0_CACHE_SIZE0__Size_MASK 0xffffff |
| #define ACP_DSP0_CACHE_SIZE0__Size__SHIFT 0x0 |
| #define ACP_DSP0_CACHE_SIZE0__PageEnable_MASK 0x80000000 |
| #define ACP_DSP0_CACHE_SIZE0__PageEnable__SHIFT 0x1f |
| #define ACP_DSP0_CACHE_OFFSET1__Offset_MASK 0xfffffff |
| #define ACP_DSP0_CACHE_OFFSET1__Offset__SHIFT 0x0 |
| #define ACP_DSP0_CACHE_OFFSET1__OnionGarlicSel_MASK 0x80000000 |
| #define ACP_DSP0_CACHE_OFFSET1__OnionGarlicSel__SHIFT 0x1f |
| #define ACP_DSP0_CACHE_SIZE1__Size_MASK 0xffffff |
| #define ACP_DSP0_CACHE_SIZE1__Size__SHIFT 0x0 |
| #define ACP_DSP0_CACHE_SIZE1__PageEnable_MASK 0x80000000 |
| #define ACP_DSP0_CACHE_SIZE1__PageEnable__SHIFT 0x1f |
| #define ACP_DSP0_CACHE_OFFSET2__Offset_MASK 0xfffffff |
| #define ACP_DSP0_CACHE_OFFSET2__Offset__SHIFT 0x0 |
| #define ACP_DSP0_CACHE_OFFSET2__OnionGarlicSel_MASK 0x80000000 |
| #define ACP_DSP0_CACHE_OFFSET2__OnionGarlicSel__SHIFT 0x1f |
| #define ACP_DSP0_CACHE_SIZE2__Size_MASK 0xffffff |
| #define ACP_DSP0_CACHE_SIZE2__Size__SHIFT 0x0 |
| #define ACP_DSP0_CACHE_SIZE2__PageEnable_MASK 0x80000000 |
| #define ACP_DSP0_CACHE_SIZE2__PageEnable__SHIFT 0x1f |
| #define ACP_DSP0_CACHE_OFFSET3__Offset_MASK 0xfffffff |
| #define ACP_DSP0_CACHE_OFFSET3__Offset__SHIFT 0x0 |
| #define ACP_DSP0_CACHE_OFFSET3__OnionGarlicSel_MASK 0x80000000 |
| #define ACP_DSP0_CACHE_OFFSET3__OnionGarlicSel__SHIFT 0x1f |
| #define ACP_DSP0_CACHE_SIZE3__Size_MASK 0xffffff |
| #define ACP_DSP0_CACHE_SIZE3__Size__SHIFT 0x0 |
| #define ACP_DSP0_CACHE_SIZE3__PageEnable_MASK 0x80000000 |
| #define ACP_DSP0_CACHE_SIZE3__PageEnable__SHIFT 0x1f |
| #define ACP_DSP0_CACHE_OFFSET4__Offset_MASK 0xfffffff |
| #define ACP_DSP0_CACHE_OFFSET4__Offset__SHIFT 0x0 |
| #define ACP_DSP0_CACHE_OFFSET4__OnionGarlicSel_MASK 0x80000000 |
| #define ACP_DSP0_CACHE_OFFSET4__OnionGarlicSel__SHIFT 0x1f |
| #define ACP_DSP0_CACHE_SIZE4__Size_MASK 0xffffff |
| #define ACP_DSP0_CACHE_SIZE4__Size__SHIFT 0x0 |
| #define ACP_DSP0_CACHE_SIZE4__PageEnable_MASK 0x80000000 |
| #define ACP_DSP0_CACHE_SIZE4__PageEnable__SHIFT 0x1f |
| #define ACP_DSP0_CACHE_OFFSET5__Offset_MASK 0xfffffff |
| #define ACP_DSP0_CACHE_OFFSET5__Offset__SHIFT 0x0 |
| #define ACP_DSP0_CACHE_OFFSET5__OnionGarlicSel_MASK 0x80000000 |
| #define ACP_DSP0_CACHE_OFFSET5__OnionGarlicSel__SHIFT 0x1f |
| #define ACP_DSP0_CACHE_SIZE5__Size_MASK 0xffffff |
| #define ACP_DSP0_CACHE_SIZE5__Size__SHIFT 0x0 |
| #define ACP_DSP0_CACHE_SIZE5__PageEnable_MASK 0x80000000 |
| #define ACP_DSP0_CACHE_SIZE5__PageEnable__SHIFT 0x1f |
| #define ACP_DSP0_CACHE_OFFSET6__Offset_MASK 0xfffffff |
| #define ACP_DSP0_CACHE_OFFSET6__Offset__SHIFT 0x0 |
| #define ACP_DSP0_CACHE_OFFSET6__OnionGarlicSel_MASK 0x80000000 |
| #define ACP_DSP0_CACHE_OFFSET6__OnionGarlicSel__SHIFT 0x1f |
| #define ACP_DSP0_CACHE_SIZE6__Size_MASK 0xffffff |
| #define ACP_DSP0_CACHE_SIZE6__Size__SHIFT 0x0 |
| #define ACP_DSP0_CACHE_SIZE6__PageEnable_MASK 0x80000000 |
| #define ACP_DSP0_CACHE_SIZE6__PageEnable__SHIFT 0x1f |
| #define ACP_DSP0_CACHE_OFFSET7__Offset_MASK 0xfffffff |
| #define ACP_DSP0_CACHE_OFFSET7__Offset__SHIFT 0x0 |
| #define ACP_DSP0_CACHE_OFFSET7__OnionGarlicSel_MASK 0x80000000 |
| #define ACP_DSP0_CACHE_OFFSET7__OnionGarlicSel__SHIFT 0x1f |
| #define ACP_DSP0_CACHE_SIZE7__Size_MASK 0xffffff |
| #define ACP_DSP0_CACHE_SIZE7__Size__SHIFT 0x0 |
| #define ACP_DSP0_CACHE_SIZE7__PageEnable_MASK 0x80000000 |
| #define ACP_DSP0_CACHE_SIZE7__PageEnable__SHIFT 0x1f |
| #define ACP_DSP0_CACHE_OFFSET8__Offset_MASK 0xfffffff |
| #define ACP_DSP0_CACHE_OFFSET8__Offset__SHIFT 0x0 |
| #define ACP_DSP0_CACHE_OFFSET8__OnionGarlicSel_MASK 0x80000000 |
| #define ACP_DSP0_CACHE_OFFSET8__OnionGarlicSel__SHIFT 0x1f |
| #define ACP_DSP0_CACHE_SIZE8__Size_MASK 0xffffff |
| #define ACP_DSP0_CACHE_SIZE8__Size__SHIFT 0x0 |
| #define ACP_DSP0_CACHE_SIZE8__PageEnable_MASK 0x80000000 |
| #define ACP_DSP0_CACHE_SIZE8__PageEnable__SHIFT 0x1f |
| #define ACP_DSP0_NONCACHE_OFFSET0__Offset_MASK 0xfffffff |
| #define ACP_DSP0_NONCACHE_OFFSET0__Offset__SHIFT 0x0 |
| #define ACP_DSP0_NONCACHE_OFFSET0__OnionGarlicSel_MASK 0x80000000 |
| #define ACP_DSP0_NONCACHE_OFFSET0__OnionGarlicSel__SHIFT 0x1f |
| #define ACP_DSP0_NONCACHE_SIZE0__Size_MASK 0xffffff |
| #define ACP_DSP0_NONCACHE_SIZE0__Size__SHIFT 0x0 |
| #define ACP_DSP0_NONCACHE_SIZE0__PageEnable_MASK 0x80000000 |
| #define ACP_DSP0_NONCACHE_SIZE0__PageEnable__SHIFT 0x1f |
| #define ACP_DSP0_NONCACHE_OFFSET1__Offset_MASK 0xfffffff |
| #define ACP_DSP0_NONCACHE_OFFSET1__Offset__SHIFT 0x0 |
| #define ACP_DSP0_NONCACHE_OFFSET1__OnionGarlicSel_MASK 0x80000000 |
| #define ACP_DSP0_NONCACHE_OFFSET1__OnionGarlicSel__SHIFT 0x1f |
| #define ACP_DSP0_NONCACHE_SIZE1__Size_MASK 0xffffff |
| #define ACP_DSP0_NONCACHE_SIZE1__Size__SHIFT 0x0 |
| #define ACP_DSP0_NONCACHE_SIZE1__PageEnable_MASK 0x80000000 |
| #define ACP_DSP0_NONCACHE_SIZE1__PageEnable__SHIFT 0x1f |
| #define ACP_DSP0_DEBUG_PC__DebugPC_MASK 0xffffffff |
| #define ACP_DSP0_DEBUG_PC__DebugPC__SHIFT 0x0 |
| #define ACP_DSP0_NMI_SEL__NMISel_MASK 0x1 |
| #define ACP_DSP0_NMI_SEL__NMISel__SHIFT 0x0 |
| #define ACP_DSP0_CLKRST_CNTL__ClkEn_MASK 0x1 |
| #define ACP_DSP0_CLKRST_CNTL__ClkEn__SHIFT 0x0 |
| #define ACP_DSP0_CLKRST_CNTL__SoftResetDSP_MASK 0x2 |
| #define ACP_DSP0_CLKRST_CNTL__SoftResetDSP__SHIFT 0x1 |
| #define ACP_DSP0_CLKRST_CNTL__InternalSoftResetMode_MASK 0x4 |
| #define ACP_DSP0_CLKRST_CNTL__InternalSoftResetMode__SHIFT 0x2 |
| #define ACP_DSP0_CLKRST_CNTL__ExternalSoftResetMode_MASK 0x8 |
| #define ACP_DSP0_CLKRST_CNTL__ExternalSoftResetMode__SHIFT 0x3 |
| #define ACP_DSP0_CLKRST_CNTL__SoftResetDSPDone_MASK 0x10 |
| #define ACP_DSP0_CLKRST_CNTL__SoftResetDSPDone__SHIFT 0x4 |
| #define ACP_DSP0_CLKRST_CNTL__Clk_ON_Status_MASK 0x20 |
| #define ACP_DSP0_CLKRST_CNTL__Clk_ON_Status__SHIFT 0x5 |
| #define ACP_DSP0_RUNSTALL__RunStallCntl_MASK 0x1 |
| #define ACP_DSP0_RUNSTALL__RunStallCntl__SHIFT 0x0 |
| #define ACP_DSP0_OCD_HALT_ON_RST__OCD_HALT_ON_RST_MASK 0x1 |
| #define ACP_DSP0_OCD_HALT_ON_RST__OCD_HALT_ON_RST__SHIFT 0x0 |
| #define ACP_DSP0_WAIT_MODE__WaitMode_MASK 0x1 |
| #define ACP_DSP0_WAIT_MODE__WaitMode__SHIFT 0x0 |
| #define ACP_DSP0_VECT_SEL__StaticVectorSel_MASK 0x1 |
| #define ACP_DSP0_VECT_SEL__StaticVectorSel__SHIFT 0x0 |
| #define ACP_DSP0_DEBUG_REG1__ACP_DSP_DEBUG_REG1_MASK 0xffffffff |
| #define ACP_DSP0_DEBUG_REG1__ACP_DSP_DEBUG_REG1__SHIFT 0x0 |
| #define ACP_DSP0_DEBUG_REG2__ACP_DSP_DEBUG_REG2_MASK 0xffffffff |
| #define ACP_DSP0_DEBUG_REG2__ACP_DSP_DEBUG_REG2__SHIFT 0x0 |
| #define ACP_DSP0_DEBUG_REG3__ACP_DSP_DEBUG_REG3_MASK 0xffffffff |
| #define ACP_DSP0_DEBUG_REG3__ACP_DSP_DEBUG_REG3__SHIFT 0x0 |
| #define ACP_DSP1_CACHE_OFFSET0__Offset_MASK 0xfffffff |
| #define ACP_DSP1_CACHE_OFFSET0__Offset__SHIFT 0x0 |
| #define ACP_DSP1_CACHE_OFFSET0__OnionGarlicSel_MASK 0x80000000 |
| #define ACP_DSP1_CACHE_OFFSET0__OnionGarlicSel__SHIFT 0x1f |
| #define ACP_DSP1_CACHE_SIZE0__Size_MASK 0xffffff |
| #define ACP_DSP1_CACHE_SIZE0__Size__SHIFT 0x0 |
| #define ACP_DSP1_CACHE_SIZE0__PageEnable_MASK 0x80000000 |
| #define ACP_DSP1_CACHE_SIZE0__PageEnable__SHIFT 0x1f |
| #define ACP_DSP1_CACHE_OFFSET1__Offset_MASK 0xfffffff |
| #define ACP_DSP1_CACHE_OFFSET1__Offset__SHIFT 0x0 |
| #define ACP_DSP1_CACHE_OFFSET1__OnionGarlicSel_MASK 0x80000000 |
| #define ACP_DSP1_CACHE_OFFSET1__OnionGarlicSel__SHIFT 0x1f |
| #define ACP_DSP1_CACHE_SIZE1__Size_MASK 0xffffff |
| #define ACP_DSP1_CACHE_SIZE1__Size__SHIFT 0x0 |
| #define ACP_DSP1_CACHE_SIZE1__PageEnable_MASK 0x80000000 |
| #define ACP_DSP1_CACHE_SIZE1__PageEnable__SHIFT 0x1f |
| #define ACP_DSP1_CACHE_OFFSET2__Offset_MASK 0xfffffff |
| #define ACP_DSP1_CACHE_OFFSET2__Offset__SHIFT 0x0 |
| #define ACP_DSP1_CACHE_OFFSET2__OnionGarlicSel_MASK 0x80000000 |
| #define ACP_DSP1_CACHE_OFFSET2__OnionGarlicSel__SHIFT 0x1f |
| #define ACP_DSP1_CACHE_SIZE2__Size_MASK 0xffffff |
| #define ACP_DSP1_CACHE_SIZE2__Size__SHIFT 0x0 |
| #define ACP_DSP1_CACHE_SIZE2__PageEnable_MASK 0x80000000 |
| #define ACP_DSP1_CACHE_SIZE2__PageEnable__SHIFT 0x1f |
| #define ACP_DSP1_CACHE_OFFSET3__Offset_MASK 0xfffffff |
| #define ACP_DSP1_CACHE_OFFSET3__Offset__SHIFT 0x0 |
| #define ACP_DSP1_CACHE_OFFSET3__OnionGarlicSel_MASK 0x80000000 |
| #define ACP_DSP1_CACHE_OFFSET3__OnionGarlicSel__SHIFT 0x1f |
| #define ACP_DSP1_CACHE_SIZE3__Size_MASK 0xffffff |
| #define ACP_DSP1_CACHE_SIZE3__Size__SHIFT 0x0 |
| #define ACP_DSP1_CACHE_SIZE3__PageEnable_MASK 0x80000000 |
| #define ACP_DSP1_CACHE_SIZE3__PageEnable__SHIFT 0x1f |
| #define ACP_DSP1_CACHE_OFFSET4__Offset_MASK 0xfffffff |
| #define ACP_DSP1_CACHE_OFFSET4__Offset__SHIFT 0x0 |
| #define ACP_DSP1_CACHE_OFFSET4__OnionGarlicSel_MASK 0x80000000 |
| #define ACP_DSP1_CACHE_OFFSET4__OnionGarlicSel__SHIFT 0x1f |
| #define ACP_DSP1_CACHE_SIZE4__Size_MASK 0xffffff |
| #define ACP_DSP1_CACHE_SIZE4__Size__SHIFT 0x0 |
| #define ACP_DSP1_CACHE_SIZE4__PageEnable_MASK 0x80000000 |
| #define ACP_DSP1_CACHE_SIZE4__PageEnable__SHIFT 0x1f |
| #define ACP_DSP1_CACHE_OFFSET5__Offset_MASK 0xfffffff |
| #define ACP_DSP1_CACHE_OFFSET5__Offset__SHIFT 0x0 |
| #define ACP_DSP1_CACHE_OFFSET5__OnionGarlicSel_MASK 0x80000000 |
| #define ACP_DSP1_CACHE_OFFSET5__OnionGarlicSel__SHIFT 0x1f |
| #define ACP_DSP1_CACHE_SIZE5__Size_MASK 0xffffff |
| #define ACP_DSP1_CACHE_SIZE5__Size__SHIFT 0x0 |
| #define ACP_DSP1_CACHE_SIZE5__PageEnable_MASK 0x80000000 |
| #define ACP_DSP1_CACHE_SIZE5__PageEnable__SHIFT 0x1f |
| #define ACP_DSP1_CACHE_OFFSET6__Offset_MASK 0xfffffff |
| #define ACP_DSP1_CACHE_OFFSET6__Offset__SHIFT 0x0 |
| #define ACP_DSP1_CACHE_OFFSET6__OnionGarlicSel_MASK 0x80000000 |
| #define ACP_DSP1_CACHE_OFFSET6__OnionGarlicSel__SHIFT 0x1f |
| #define ACP_DSP1_CACHE_SIZE6__Size_MASK 0xffffff |
| #define ACP_DSP1_CACHE_SIZE6__Size__SHIFT 0x0 |
| #define ACP_DSP1_CACHE_SIZE6__PageEnable_MASK 0x80000000 |
| #define ACP_DSP1_CACHE_SIZE6__PageEnable__SHIFT 0x1f |
| #define ACP_DSP1_CACHE_OFFSET7__Offset_MASK 0xfffffff |
| #define ACP_DSP1_CACHE_OFFSET7__Offset__SHIFT 0x0 |
| #define ACP_DSP1_CACHE_OFFSET7__OnionGarlicSel_MASK 0x80000000 |
| #define ACP_DSP1_CACHE_OFFSET7__OnionGarlicSel__SHIFT 0x1f |
| #define ACP_DSP1_CACHE_SIZE7__Size_MASK 0xffffff |
| #define ACP_DSP1_CACHE_SIZE7__Size__SHIFT 0x0 |
| #define ACP_DSP1_CACHE_SIZE7__PageEnable_MASK 0x80000000 |
| #define ACP_DSP1_CACHE_SIZE7__PageEnable__SHIFT 0x1f |
| #define ACP_DSP1_CACHE_OFFSET8__Offset_MASK 0xfffffff |
| #define ACP_DSP1_CACHE_OFFSET8__Offset__SHIFT 0x0 |
| #define ACP_DSP1_CACHE_OFFSET8__OnionGarlicSel_MASK 0x80000000 |
| #define ACP_DSP1_CACHE_OFFSET8__OnionGarlicSel__SHIFT 0x1f |
| #define ACP_DSP1_CACHE_SIZE8__Size_MASK 0xffffff |
| #define ACP_DSP1_CACHE_SIZE8__Size__SHIFT 0x0 |
| #define ACP_DSP1_CACHE_SIZE8__PageEnable_MASK 0x80000000 |
| #define ACP_DSP1_CACHE_SIZE8__PageEnable__SHIFT 0x1f |
| #define ACP_DSP1_NONCACHE_OFFSET0__Offset_MASK 0xfffffff |
| #define ACP_DSP1_NONCACHE_OFFSET0__Offset__SHIFT 0x0 |
| #define ACP_DSP1_NONCACHE_OFFSET0__OnionGarlicSel_MASK 0x80000000 |
| #define ACP_DSP1_NONCACHE_OFFSET0__OnionGarlicSel__SHIFT 0x1f |
| #define ACP_DSP1_NONCACHE_SIZE0__Size_MASK 0xffffff |
| #define ACP_DSP1_NONCACHE_SIZE0__Size__SHIFT 0x0 |
| #define ACP_DSP1_NONCACHE_SIZE0__PageEnable_MASK 0x80000000 |
| #define ACP_DSP1_NONCACHE_SIZE0__PageEnable__SHIFT 0x1f |
| #define ACP_DSP1_NONCACHE_OFFSET1__Offset_MASK 0xfffffff |
| #define ACP_DSP1_NONCACHE_OFFSET1__Offset__SHIFT 0x0 |
| #define ACP_DSP1_NONCACHE_OFFSET1__OnionGarlicSel_MASK 0x80000000 |
| #define ACP_DSP1_NONCACHE_OFFSET1__OnionGarlicSel__SHIFT 0x1f |
| #define ACP_DSP1_NONCACHE_SIZE1__Size_MASK 0xffffff |
| #define ACP_DSP1_NONCACHE_SIZE1__Size__SHIFT 0x0 |
| #define ACP_DSP1_NONCACHE_SIZE1__PageEnable_MASK 0x80000000 |
| #define ACP_DSP1_NONCACHE_SIZE1__PageEnable__SHIFT 0x1f |
| #define ACP_DSP1_DEBUG_PC__DebugPC_MASK 0xffffffff |
| #define ACP_DSP1_DEBUG_PC__DebugPC__SHIFT 0x0 |
| #define ACP_DSP1_NMI_SEL__NMISel_MASK 0x1 |
| #define ACP_DSP1_NMI_SEL__NMISel__SHIFT 0x0 |
| #define ACP_DSP1_CLKRST_CNTL__ClkEn_MASK 0x1 |
| #define ACP_DSP1_CLKRST_CNTL__ClkEn__SHIFT 0x0 |
| #define ACP_DSP1_CLKRST_CNTL__SoftResetDSP_MASK 0x2 |
| #define ACP_DSP1_CLKRST_CNTL__SoftResetDSP__SHIFT 0x1 |
| #define ACP_DSP1_CLKRST_CNTL__InternalSoftResetMode_MASK 0x4 |
| #define ACP_DSP1_CLKRST_CNTL__InternalSoftResetMode__SHIFT 0x2 |
| #define ACP_DSP1_CLKRST_CNTL__ExternalSoftResetMode_MASK 0x8 |
| #define ACP_DSP1_CLKRST_CNTL__ExternalSoftResetMode__SHIFT 0x3 |
| #define ACP_DSP1_CLKRST_CNTL__SoftResetDSPDone_MASK 0x10 |
| #define ACP_DSP1_CLKRST_CNTL__SoftResetDSPDone__SHIFT 0x4 |
| #define ACP_DSP1_CLKRST_CNTL__Clk_ON_Status_MASK 0x20 |
| #define ACP_DSP1_CLKRST_CNTL__Clk_ON_Status__SHIFT 0x5 |
| #define ACP_DSP1_RUNSTALL__RunStallCntl_MASK 0x1 |
| #define ACP_DSP1_RUNSTALL__RunStallCntl__SHIFT 0x0 |
| #define ACP_DSP1_OCD_HALT_ON_RST__OCD_HALT_ON_RST_MASK 0x1 |
| #define ACP_DSP1_OCD_HALT_ON_RST__OCD_HALT_ON_RST__SHIFT 0x0 |
| #define ACP_DSP1_WAIT_MODE__WaitMode_MASK 0x1 |
| #define ACP_DSP1_WAIT_MODE__WaitMode__SHIFT 0x0 |
| #define ACP_DSP1_VECT_SEL__StaticVectorSel_MASK 0x1 |
| #define ACP_DSP1_VECT_SEL__StaticVectorSel__SHIFT 0x0 |
| #define ACP_DSP1_DEBUG_REG1__ACP_DSP_DEBUG_REG1_MASK 0xffffffff |
| #define ACP_DSP1_DEBUG_REG1__ACP_DSP_DEBUG_REG1__SHIFT 0x0 |
| #define ACP_DSP1_DEBUG_REG2__ACP_DSP_DEBUG_REG2_MASK 0xffffffff |
| #define ACP_DSP1_DEBUG_REG2__ACP_DSP_DEBUG_REG2__SHIFT 0x0 |
| #define ACP_DSP1_DEBUG_REG3__ACP_DSP_DEBUG_REG3_MASK 0xffffffff |
| #define ACP_DSP1_DEBUG_REG3__ACP_DSP_DEBUG_REG3__SHIFT 0x0 |
| #define ACP_DSP2_CACHE_OFFSET0__Offset_MASK 0xfffffff |
| #define ACP_DSP2_CACHE_OFFSET0__Offset__SHIFT 0x0 |
| #define ACP_DSP2_CACHE_OFFSET0__OnionGarlicSel_MASK 0x80000000 |
| #define ACP_DSP2_CACHE_OFFSET0__OnionGarlicSel__SHIFT 0x1f |
| #define ACP_DSP2_CACHE_SIZE0__Size_MASK 0xffffff |
| #define ACP_DSP2_CACHE_SIZE0__Size__SHIFT 0x0 |
| #define ACP_DSP2_CACHE_SIZE0__PageEnable_MASK 0x80000000 |
| #define ACP_DSP2_CACHE_SIZE0__PageEnable__SHIFT 0x1f |
| #define ACP_DSP2_CACHE_OFFSET1__Offset_MASK 0xfffffff |
| #define ACP_DSP2_CACHE_OFFSET1__Offset__SHIFT 0x0 |
| #define ACP_DSP2_CACHE_OFFSET1__OnionGarlicSel_MASK 0x80000000 |
| #define ACP_DSP2_CACHE_OFFSET1__OnionGarlicSel__SHIFT 0x1f |
| #define ACP_DSP2_CACHE_SIZE1__Size_MASK 0xffffff |
| #define ACP_DSP2_CACHE_SIZE1__Size__SHIFT 0x0 |
| #define ACP_DSP2_CACHE_SIZE1__PageEnable_MASK 0x80000000 |
| #define ACP_DSP2_CACHE_SIZE1__PageEnable__SHIFT 0x1f |
| #define ACP_DSP2_CACHE_OFFSET2__Offset_MASK 0xfffffff |
| #define ACP_DSP2_CACHE_OFFSET2__Offset__SHIFT 0x0 |
| #define ACP_DSP2_CACHE_OFFSET2__OnionGarlicSel_MASK 0x80000000 |
| #define ACP_DSP2_CACHE_OFFSET2__OnionGarlicSel__SHIFT 0x1f |
| #define ACP_DSP2_CACHE_SIZE2__Size_MASK 0xffffff |
| #define ACP_DSP2_CACHE_SIZE2__Size__SHIFT 0x0 |
| #define ACP_DSP2_CACHE_SIZE2__PageEnable_MASK 0x80000000 |
| #define ACP_DSP2_CACHE_SIZE2__PageEnable__SHIFT 0x1f |
| #define ACP_DSP2_CACHE_OFFSET3__Offset_MASK 0xfffffff |
| #define ACP_DSP2_CACHE_OFFSET3__Offset__SHIFT 0x0 |
| #define ACP_DSP2_CACHE_OFFSET3__OnionGarlicSel_MASK 0x80000000 |
| #define ACP_DSP2_CACHE_OFFSET3__OnionGarlicSel__SHIFT 0x1f |
| #define ACP_DSP2_CACHE_SIZE3__Size_MASK 0xffffff |
| #define ACP_DSP2_CACHE_SIZE3__Size__SHIFT 0x0 |
| #define ACP_DSP2_CACHE_SIZE3__PageEnable_MASK 0x80000000 |
| #define ACP_DSP2_CACHE_SIZE3__PageEnable__SHIFT 0x1f |
| #define ACP_DSP2_CACHE_OFFSET4__Offset_MASK 0xfffffff |
| #define ACP_DSP2_CACHE_OFFSET4__Offset__SHIFT 0x0 |
| #define ACP_DSP2_CACHE_OFFSET4__OnionGarlicSel_MASK 0x80000000 |
| #define ACP_DSP2_CACHE_OFFSET4__OnionGarlicSel__SHIFT 0x1f |
| #define ACP_DSP2_CACHE_SIZE4__Size_MASK 0xffffff |
| #define ACP_DSP2_CACHE_SIZE4__Size__SHIFT 0x0 |
| #define ACP_DSP2_CACHE_SIZE4__PageEnable_MASK 0x80000000 |
| #define ACP_DSP2_CACHE_SIZE4__PageEnable__SHIFT 0x1f |
| #define ACP_DSP2_CACHE_OFFSET5__Offset_MASK 0xfffffff |
| #define ACP_DSP2_CACHE_OFFSET5__Offset__SHIFT 0x0 |
| #define ACP_DSP2_CACHE_OFFSET5__OnionGarlicSel_MASK 0x80000000 |
| #define ACP_DSP2_CACHE_OFFSET5__OnionGarlicSel__SHIFT 0x1f |
| #define ACP_DSP2_CACHE_SIZE5__Size_MASK 0xffffff |
| #define ACP_DSP2_CACHE_SIZE5__Size__SHIFT 0x0 |
| #define ACP_DSP2_CACHE_SIZE5__PageEnable_MASK 0x80000000 |
| #define ACP_DSP2_CACHE_SIZE5__PageEnable__SHIFT 0x1f |
| #define ACP_DSP2_CACHE_OFFSET6__Offset_MASK 0xfffffff |
| #define ACP_DSP2_CACHE_OFFSET6__Offset__SHIFT 0x0 |
| #define ACP_DSP2_CACHE_OFFSET6__OnionGarlicSel_MASK 0x80000000 |
| #define ACP_DSP2_CACHE_OFFSET6__OnionGarlicSel__SHIFT 0x1f |
| #define ACP_DSP2_CACHE_SIZE6__Size_MASK 0xffffff |
| #define ACP_DSP2_CACHE_SIZE6__Size__SHIFT 0x0 |
| #define ACP_DSP2_CACHE_SIZE6__PageEnable_MASK 0x80000000 |
| #define ACP_DSP2_CACHE_SIZE6__PageEnable__SHIFT 0x1f |
| #define ACP_DSP2_CACHE_OFFSET7__Offset_MASK 0xfffffff |
| #define ACP_DSP2_CACHE_OFFSET7__Offset__SHIFT 0x0 |
| #define ACP_DSP2_CACHE_OFFSET7__OnionGarlicSel_MASK 0x80000000 |
| #define ACP_DSP2_CACHE_OFFSET7__OnionGarlicSel__SHIFT 0x1f |
| #define ACP_DSP2_CACHE_SIZE7__Size_MASK 0xffffff |
| #define ACP_DSP2_CACHE_SIZE7__Size__SHIFT 0x0 |
| #define ACP_DSP2_CACHE_SIZE7__PageEnable_MASK 0x80000000 |
| #define ACP_DSP2_CACHE_SIZE7__PageEnable__SHIFT 0x1f |
| #define ACP_DSP2_CACHE_OFFSET8__Offset_MASK 0xfffffff |
| #define ACP_DSP2_CACHE_OFFSET8__Offset__SHIFT 0x0 |
| #define ACP_DSP2_CACHE_OFFSET8__OnionGarlicSel_MASK 0x80000000 |
| #define ACP_DSP2_CACHE_OFFSET8__OnionGarlicSel__SHIFT 0x1f |
| #define ACP_DSP2_CACHE_SIZE8__Size_MASK 0xffffff |
| #define ACP_DSP2_CACHE_SIZE8__Size__SHIFT 0x0 |
| #define ACP_DSP2_CACHE_SIZE8__PageEnable_MASK 0x80000000 |
| #define ACP_DSP2_CACHE_SIZE8__PageEnable__SHIFT 0x1f |
| #define ACP_DSP2_NONCACHE_OFFSET0__Offset_MASK 0xfffffff |
| #define ACP_DSP2_NONCACHE_OFFSET0__Offset__SHIFT 0x0 |
| #define ACP_DSP2_NONCACHE_OFFSET0__OnionGarlicSel_MASK 0x80000000 |
| #define ACP_DSP2_NONCACHE_OFFSET0__OnionGarlicSel__SHIFT 0x1f |
| #define ACP_DSP2_NONCACHE_SIZE0__Size_MASK 0xffffff |
| #define ACP_DSP2_NONCACHE_SIZE0__Size__SHIFT 0x0 |
| #define ACP_DSP2_NONCACHE_SIZE0__PageEnable_MASK 0x80000000 |
| #define ACP_DSP2_NONCACHE_SIZE0__PageEnable__SHIFT 0x1f |
| #define ACP_DSP2_NONCACHE_OFFSET1__Offset_MASK 0xfffffff |
| #define ACP_DSP2_NONCACHE_OFFSET1__Offset__SHIFT 0x0 |
| #define ACP_DSP2_NONCACHE_OFFSET1__OnionGarlicSel_MASK 0x80000000 |
| #define ACP_DSP2_NONCACHE_OFFSET1__OnionGarlicSel__SHIFT 0x1f |
| #define ACP_DSP2_NONCACHE_SIZE1__Size_MASK 0xffffff |
| #define ACP_DSP2_NONCACHE_SIZE1__Size__SHIFT 0x0 |
| #define ACP_DSP2_NONCACHE_SIZE1__PageEnable_MASK 0x80000000 |
| #define ACP_DSP2_NONCACHE_SIZE1__PageEnable__SHIFT 0x1f |
| #define ACP_DSP2_DEBUG_PC__DebugPC_MASK 0xffffffff |
| #define ACP_DSP2_DEBUG_PC__DebugPC__SHIFT 0x0 |
| #define ACP_DSP2_NMI_SEL__NMISel_MASK 0x1 |
| #define ACP_DSP2_NMI_SEL__NMISel__SHIFT 0x0 |
| #define ACP_DSP2_CLKRST_CNTL__ClkEn_MASK 0x1 |
| #define ACP_DSP2_CLKRST_CNTL__ClkEn__SHIFT 0x0 |
| #define ACP_DSP2_CLKRST_CNTL__SoftResetDSP_MASK 0x2 |
| #define ACP_DSP2_CLKRST_CNTL__SoftResetDSP__SHIFT 0x1 |
| #define ACP_DSP2_CLKRST_CNTL__InternalSoftResetMode_MASK 0x4 |
| #define ACP_DSP2_CLKRST_CNTL__InternalSoftResetMode__SHIFT 0x2 |
| #define ACP_DSP2_CLKRST_CNTL__ExternalSoftResetMode_MASK 0x8 |
| #define ACP_DSP2_CLKRST_CNTL__ExternalSoftResetMode__SHIFT 0x3 |
| #define ACP_DSP2_CLKRST_CNTL__SoftResetDSPDone_MASK 0x10 |
| #define ACP_DSP2_CLKRST_CNTL__SoftResetDSPDone__SHIFT 0x4 |
| #define ACP_DSP2_CLKRST_CNTL__Clk_ON_Status_MASK 0x20 |
| #define ACP_DSP2_CLKRST_CNTL__Clk_ON_Status__SHIFT 0x5 |
| #define ACP_DSP2_RUNSTALL__RunStallCntl_MASK 0x1 |
| #define ACP_DSP2_RUNSTALL__RunStallCntl__SHIFT 0x0 |
| #define ACP_DSP2_OCD_HALT_ON_RST__OCD_HALT_ON_RST_MASK 0x1 |
| #define ACP_DSP2_OCD_HALT_ON_RST__OCD_HALT_ON_RST__SHIFT 0x0 |
| #define ACP_DSP2_WAIT_MODE__WaitMode_MASK 0x1 |
| #define ACP_DSP2_WAIT_MODE__WaitMode__SHIFT 0x0 |
| #define ACP_DSP2_VECT_SEL__StaticVectorSel_MASK 0x1 |
| #define ACP_DSP2_VECT_SEL__StaticVectorSel__SHIFT 0x0 |
| #define ACP_DSP2_DEBUG_REG1__ACP_DSP_DEBUG_REG1_MASK 0xffffffff |
| #define ACP_DSP2_DEBUG_REG1__ACP_DSP_DEBUG_REG1__SHIFT 0x0 |
| #define ACP_DSP2_DEBUG_REG2__ACP_DSP_DEBUG_REG2_MASK 0xffffffff |
| #define ACP_DSP2_DEBUG_REG2__ACP_DSP_DEBUG_REG2__SHIFT 0x0 |
| #define ACP_DSP2_DEBUG_REG3__ACP_DSP_DEBUG_REG3_MASK 0xffffffff |
| #define ACP_DSP2_DEBUG_REG3__ACP_DSP_DEBUG_REG3__SHIFT 0x0 |
| #define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBDataSwap_MASK 0x3 |
| #define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBDataSwap__SHIFT 0x0 |
| #define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBEnbMultRdReq_MASK 0x4 |
| #define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBEnbMultRdReq__SHIFT 0x2 |
| #define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBEnbMultWrReq_MASK 0x18 |
| #define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBEnbMultWrReq__SHIFT 0x3 |
| #define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBMaxReadBurst_MASK 0x60 |
| #define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBMaxReadBurst__SHIFT 0x5 |
| #define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBStallEnb_MASK 0x80 |
| #define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBStallEnb__SHIFT 0x7 |
| #define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBNackChkEnb_MASK 0x100 |
| #define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBNackChkEnb__SHIFT 0x8 |
| #define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBAdrWinViolChkEnb_MASK 0x200 |
| #define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBAdrWinViolChkEnb__SHIFT 0x9 |
| #define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBUrgEnb_MASK 0x400 |
| #define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBUrgEnb__SHIFT 0xa |
| #define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBUrgCntMult_MASK 0x1800 |
| #define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBUrgCntMult__SHIFT 0xb |
| #define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBStallMode_MASK 0x2000 |
| #define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBStallMode__SHIFT 0xd |
| #define ACP_AXI2DAGB_ONION_ERR_STATUS_WR__AXI2DAGBAdrWinViolOver_MASK 0x2000000 |
| #define ACP_AXI2DAGB_ONION_ERR_STATUS_WR__AXI2DAGBAdrWinViolOver__SHIFT 0x19 |
| #define ACP_AXI2DAGB_ONION_ERR_STATUS_WR__AXI2DAGBAdrWinViolSource_MASK 0x1c000000 |
| #define ACP_AXI2DAGB_ONION_ERR_STATUS_WR__AXI2DAGBAdrWinViolSource__SHIFT 0x1a |
| #define ACP_AXI2DAGB_ONION_ERR_STATUS_WR__AXI2DAGBAdrWinViol_MASK 0x20000000 |
| #define ACP_AXI2DAGB_ONION_ERR_STATUS_WR__AXI2DAGBAdrWinViol__SHIFT 0x1d |
| #define ACP_AXI2DAGB_ONION_ERR_STATUS_WR__AXI2DAGBNackOver_MASK 0x40000000 |
| #define ACP_AXI2DAGB_ONION_ERR_STATUS_WR__AXI2DAGBNackOver__SHIFT 0x1e |
| #define ACP_AXI2DAGB_ONION_ERR_STATUS_WR__AXI2DAGBNackVal_MASK 0x80000000 |
| #define ACP_AXI2DAGB_ONION_ERR_STATUS_WR__AXI2DAGBNackVal__SHIFT 0x1f |
| #define ACP_AXI2DAGB_ONION_ERR_STATUS_RD__AXI2DAGBAdrWinViolOver_MASK 0x2000000 |
| #define ACP_AXI2DAGB_ONION_ERR_STATUS_RD__AXI2DAGBAdrWinViolOver__SHIFT 0x19 |
| #define ACP_AXI2DAGB_ONION_ERR_STATUS_RD__AXI2DAGBAdrWinViolSource_MASK 0x1c000000 |
| #define ACP_AXI2DAGB_ONION_ERR_STATUS_RD__AXI2DAGBAdrWinViolSource__SHIFT 0x1a |
| #define ACP_AXI2DAGB_ONION_ERR_STATUS_RD__AXI2DAGBAdrWinViol_MASK 0x20000000 |
| #define ACP_AXI2DAGB_ONION_ERR_STATUS_RD__AXI2DAGBAdrWinViol__SHIFT 0x1d |
| #define ACP_AXI2DAGB_ONION_ERR_STATUS_RD__AXI2DAGBNackOver_MASK 0x40000000 |
| #define ACP_AXI2DAGB_ONION_ERR_STATUS_RD__AXI2DAGBNackOver__SHIFT 0x1e |
| #define ACP_AXI2DAGB_ONION_ERR_STATUS_RD__AXI2DAGBNackVal_MASK 0x80000000 |
| #define ACP_AXI2DAGB_ONION_ERR_STATUS_RD__AXI2DAGBNackVal__SHIFT 0x1f |
| #define ACP_DAGB_Onion_TransPerf_Counter_Control__EnbDAGBTransPerfCntr_MASK 0x1 |
| #define ACP_DAGB_Onion_TransPerf_Counter_Control__EnbDAGBTransPerfCntr__SHIFT 0x0 |
| #define ACP_DAGB_Onion_Wr_TransPerf_Counter_Current__CurDAGBTransPerfCntrTime_MASK 0x1ffff |
| #define ACP_DAGB_Onion_Wr_TransPerf_Counter_Current__CurDAGBTransPerfCntrTime__SHIFT 0x0 |
| #define ACP_DAGB_Onion_Wr_TransPerf_Counter_Current__ClrCurDAGBTransPerfCntr_MASK 0x80000000 |
| #define ACP_DAGB_Onion_Wr_TransPerf_Counter_Current__ClrCurDAGBTransPerfCntr__SHIFT 0x1f |
| #define ACP_DAGB_Onion_Wr_TransPerf_Counter_Peak__PeakDAGBTransPerfCntrTime_MASK 0x1ffff |
| #define ACP_DAGB_Onion_Wr_TransPerf_Counter_Peak__PeakDAGBTransPerfCntrTime__SHIFT 0x0 |
| #define ACP_DAGB_Onion_Wr_TransPerf_Counter_Peak__ClrPeakDAGBTransPerfCntr_MASK 0x80000000 |
| #define ACP_DAGB_Onion_Wr_TransPerf_Counter_Peak__ClrPeakDAGBTransPerfCntr__SHIFT 0x1f |
| #define ACP_DAGB_Onion_Rd_TransPerf_Counter_Current__CurDAGBTransPerfCntrTime_MASK 0x1ffff |
| #define ACP_DAGB_Onion_Rd_TransPerf_Counter_Current__CurDAGBTransPerfCntrTime__SHIFT 0x0 |
| #define ACP_DAGB_Onion_Rd_TransPerf_Counter_Current__ClrCurDAGBTransPerfCntr_MASK 0x80000000 |
| #define ACP_DAGB_Onion_Rd_TransPerf_Counter_Current__ClrCurDAGBTransPerfCntr__SHIFT 0x1f |
| #define ACP_DAGB_Onion_Rd_TransPerf_Counter_Peak__PeakDAGBTransPerfCntrTime_MASK 0x1ffff |
| #define ACP_DAGB_Onion_Rd_TransPerf_Counter_Peak__PeakDAGBTransPerfCntrTime__SHIFT 0x0 |
| #define ACP_DAGB_Onion_Rd_TransPerf_Counter_Peak__ClrPeakDAGBTransPerfCntr_MASK 0x80000000 |
| #define ACP_DAGB_Onion_Rd_TransPerf_Counter_Peak__ClrPeakDAGBTransPerfCntr__SHIFT 0x1f |
| #define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBDataSwap_MASK 0x3 |
| #define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBDataSwap__SHIFT 0x0 |
| #define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBEnbMultRdReq_MASK 0x4 |
| #define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBEnbMultRdReq__SHIFT 0x2 |
| #define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBEnbMultWrReq_MASK 0x18 |
| #define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBEnbMultWrReq__SHIFT 0x3 |
| #define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBMaxReadBurst_MASK 0x60 |
| #define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBMaxReadBurst__SHIFT 0x5 |
| #define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBStallEnb_MASK 0x80 |
| #define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBStallEnb__SHIFT 0x7 |
| #define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBNackChkEnb_MASK 0x100 |
| #define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBNackChkEnb__SHIFT 0x8 |
| #define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBAdrWinViolChkEnb_MASK 0x200 |
| #define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBAdrWinViolChkEnb__SHIFT 0x9 |
| #define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBUrgEnb_MASK 0x400 |
| #define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBUrgEnb__SHIFT 0xa |
| #define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBUrgCntMult_MASK 0x1800 |
| #define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBUrgCntMult__SHIFT 0xb |
| #define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBStallMode_MASK 0x2000 |
| #define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBStallMode__SHIFT 0xd |
| #define ACP_AXI2DAGB_GARLIC_ERR_STATUS_WR__AXI2DAGBAdrWinViolOver_MASK 0x2000000 |
| #define ACP_AXI2DAGB_GARLIC_ERR_STATUS_WR__AXI2DAGBAdrWinViolOver__SHIFT 0x19 |
| #define ACP_AXI2DAGB_GARLIC_ERR_STATUS_WR__AXI2DAGBAdrWinViolSource_MASK 0x1c000000 |
| #define ACP_AXI2DAGB_GARLIC_ERR_STATUS_WR__AXI2DAGBAdrWinViolSource__SHIFT 0x1a |
| #define ACP_AXI2DAGB_GARLIC_ERR_STATUS_WR__AXI2DAGBAdrWinViol_MASK 0x20000000 |
| #define ACP_AXI2DAGB_GARLIC_ERR_STATUS_WR__AXI2DAGBAdrWinViol__SHIFT 0x1d |
| #define ACP_AXI2DAGB_GARLIC_ERR_STATUS_WR__AXI2DAGBNackOver_MASK 0x40000000 |
| #define ACP_AXI2DAGB_GARLIC_ERR_STATUS_WR__AXI2DAGBNackOver__SHIFT 0x1e |
| #define ACP_AXI2DAGB_GARLIC_ERR_STATUS_WR__AXI2DAGBNackVal_MASK 0x80000000 |
| #define ACP_AXI2DAGB_GARLIC_ERR_STATUS_WR__AXI2DAGBNackVal__SHIFT 0x1f |
| #define ACP_AXI2DAGB_GARLIC_ERR_STATUS_RD__AXI2DAGBAdrWinViolOver_MASK 0x2000000 |
| #define ACP_AXI2DAGB_GARLIC_ERR_STATUS_RD__AXI2DAGBAdrWinViolOver__SHIFT 0x19 |
| #define ACP_AXI2DAGB_GARLIC_ERR_STATUS_RD__AXI2DAGBAdrWinViolSource_MASK 0x1c000000 |
| #define ACP_AXI2DAGB_GARLIC_ERR_STATUS_RD__AXI2DAGBAdrWinViolSource__SHIFT 0x1a |
| #define ACP_AXI2DAGB_GARLIC_ERR_STATUS_RD__AXI2DAGBAdrWinViol_MASK 0x20000000 |
| #define ACP_AXI2DAGB_GARLIC_ERR_STATUS_RD__AXI2DAGBAdrWinViol__SHIFT 0x1d |
| #define ACP_AXI2DAGB_GARLIC_ERR_STATUS_RD__AXI2DAGBNackOver_MASK 0x40000000 |
| #define ACP_AXI2DAGB_GARLIC_ERR_STATUS_RD__AXI2DAGBNackOver__SHIFT 0x1e |
| #define ACP_AXI2DAGB_GARLIC_ERR_STATUS_RD__AXI2DAGBNackVal_MASK 0x80000000 |
| #define ACP_AXI2DAGB_GARLIC_ERR_STATUS_RD__AXI2DAGBNackVal__SHIFT 0x1f |
| #define ACP_DAGB_Garlic_TransPerf_Counter_Control__EnbDAGBTransPerfCntr_MASK 0x1 |
| #define ACP_DAGB_Garlic_TransPerf_Counter_Control__EnbDAGBTransPerfCntr__SHIFT 0x0 |
| #define ACP_DAGB_Garlic_Wr_TransPerf_Counter_Current__CurDAGBTransPerfCntrTime_MASK 0x1ffff |
| #define ACP_DAGB_Garlic_Wr_TransPerf_Counter_Current__CurDAGBTransPerfCntrTime__SHIFT 0x0 |
| #define ACP_DAGB_Garlic_Wr_TransPerf_Counter_Current__ClrCurDAGBTransPerfCntr_MASK 0x80000000 |
| #define ACP_DAGB_Garlic_Wr_TransPerf_Counter_Current__ClrCurDAGBTransPerfCntr__SHIFT 0x1f |
| #define ACP_DAGB_Garlic_Wr_TransPerf_Counter_Peak__PeakDAGBTransPerfCntrTime_MASK 0x1ffff |
| #define ACP_DAGB_Garlic_Wr_TransPerf_Counter_Peak__PeakDAGBTransPerfCntrTime__SHIFT 0x0 |
| #define ACP_DAGB_Garlic_Wr_TransPerf_Counter_Peak__ClrPeakDAGBTransPerfCntr_MASK 0x80000000 |
| #define ACP_DAGB_Garlic_Wr_TransPerf_Counter_Peak__ClrPeakDAGBTransPerfCntr__SHIFT 0x1f |
| #define ACP_DAGB_Garlic_Rd_TransPerf_Counter_Current__CurDAGBTransPerfCntrTime_MASK 0x1ffff |
| #define ACP_DAGB_Garlic_Rd_TransPerf_Counter_Current__CurDAGBTransPerfCntrTime__SHIFT 0x0 |
| #define ACP_DAGB_Garlic_Rd_TransPerf_Counter_Current__ClrCurDAGBTransPerfCntr_MASK 0x80000000 |
| #define ACP_DAGB_Garlic_Rd_TransPerf_Counter_Current__ClrCurDAGBTransPerfCntr__SHIFT 0x1f |
| #define ACP_DAGB_Garlic_Rd_TransPerf_Counter_Peak__PeakDAGBTransPerfCntrTime_MASK 0x1ffff |
| #define ACP_DAGB_Garlic_Rd_TransPerf_Counter_Peak__PeakDAGBTransPerfCntrTime__SHIFT 0x0 |
| #define ACP_DAGB_Garlic_Rd_TransPerf_Counter_Peak__ClrPeakDAGBTransPerfCntr_MASK 0x80000000 |
| #define ACP_DAGB_Garlic_Rd_TransPerf_Counter_Peak__ClrPeakDAGBTransPerfCntr__SHIFT 0x1f |
| #define ACP_DAGB_PAGE_SIZE_GRP_1__AXI2DAGBPageSize_MASK 0x3 |
| #define ACP_DAGB_PAGE_SIZE_GRP_1__AXI2DAGBPageSize__SHIFT 0x0 |
| #define ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBBaseAddr_MASK 0xfffffff |
| #define ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBBaseAddr__SHIFT 0x0 |
| #define ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBSnoopSel_MASK 0x20000000 |
| #define ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBSnoopSel__SHIFT 0x1d |
| #define ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBTargetMemSel_MASK 0x40000000 |
| #define ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBTargetMemSel__SHIFT 0x1e |
| #define ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBGrpEnable_MASK 0x80000000 |
| #define ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBGrpEnable__SHIFT 0x1f |
| #define ACP_DAGB_PAGE_SIZE_GRP_2__AXI2DAGBPageSize_MASK 0x3 |
| #define ACP_DAGB_PAGE_SIZE_GRP_2__AXI2DAGBPageSize__SHIFT 0x0 |
| #define ACP_DAGB_BASE_ADDR_GRP_2__AXI2DAGBBaseAddr_MASK 0xfffffff |
| #define ACP_DAGB_BASE_ADDR_GRP_2__AXI2DAGBBaseAddr__SHIFT 0x0 |
| #define ACP_DAGB_BASE_ADDR_GRP_2__AXI2DAGBSnoopSel_MASK 0x20000000 |
| #define ACP_DAGB_BASE_ADDR_GRP_2__AXI2DAGBSnoopSel__SHIFT 0x1d |
| #define ACP_DAGB_BASE_ADDR_GRP_2__AXI2DAGBTargetMemSel_MASK 0x40000000 |
| #define ACP_DAGB_BASE_ADDR_GRP_2__AXI2DAGBTargetMemSel__SHIFT 0x1e |
| #define ACP_DAGB_BASE_ADDR_GRP_2__AXI2DAGBGrpEnable_MASK 0x80000000 |
| #define ACP_DAGB_BASE_ADDR_GRP_2__AXI2DAGBGrpEnable__SHIFT 0x1f |
| #define ACP_DAGB_PAGE_SIZE_GRP_3__AXI2DAGBPageSize_MASK 0x3 |
| #define ACP_DAGB_PAGE_SIZE_GRP_3__AXI2DAGBPageSize__SHIFT 0x0 |
| #define ACP_DAGB_BASE_ADDR_GRP_3__AXI2DAGBBaseAddr_MASK 0xfffffff |
| #define ACP_DAGB_BASE_ADDR_GRP_3__AXI2DAGBBaseAddr__SHIFT 0x0 |
| #define ACP_DAGB_BASE_ADDR_GRP_3__AXI2DAGBSnoopSel_MASK 0x20000000 |
| #define ACP_DAGB_BASE_ADDR_GRP_3__AXI2DAGBSnoopSel__SHIFT 0x1d |
| #define ACP_DAGB_BASE_ADDR_GRP_3__AXI2DAGBTargetMemSel_MASK 0x40000000 |
| #define ACP_DAGB_BASE_ADDR_GRP_3__AXI2DAGBTargetMemSel__SHIFT 0x1e |
| #define ACP_DAGB_BASE_ADDR_GRP_3__AXI2DAGBGrpEnable_MASK 0x80000000 |
| #define ACP_DAGB_BASE_ADDR_GRP_3__AXI2DAGBGrpEnable__SHIFT 0x1f |
| #define ACP_DAGB_PAGE_SIZE_GRP_4__AXI2DAGBPageSize_MASK 0x3 |
| #define ACP_DAGB_PAGE_SIZE_GRP_4__AXI2DAGBPageSize__SHIFT 0x0 |
| #define ACP_DAGB_BASE_ADDR_GRP_4__AXI2DAGBBaseAddr_MASK 0xfffffff |
| #define ACP_DAGB_BASE_ADDR_GRP_4__AXI2DAGBBaseAddr__SHIFT 0x0 |
| #define ACP_DAGB_BASE_ADDR_GRP_4__AXI2DAGBSnoopSel_MASK 0x20000000 |
| #define ACP_DAGB_BASE_ADDR_GRP_4__AXI2DAGBSnoopSel__SHIFT 0x1d |
| #define ACP_DAGB_BASE_ADDR_GRP_4__AXI2DAGBTargetMemSel_MASK 0x40000000 |
| #define ACP_DAGB_BASE_ADDR_GRP_4__AXI2DAGBTargetMemSel__SHIFT 0x1e |
| #define ACP_DAGB_BASE_ADDR_GRP_4__AXI2DAGBGrpEnable_MASK 0x80000000 |
| #define ACP_DAGB_BASE_ADDR_GRP_4__AXI2DAGBGrpEnable__SHIFT 0x1f |
| #define ACP_DAGB_PAGE_SIZE_GRP_5__AXI2DAGBPageSize_MASK 0x3 |
| #define ACP_DAGB_PAGE_SIZE_GRP_5__AXI2DAGBPageSize__SHIFT 0x0 |
| #define ACP_DAGB_BASE_ADDR_GRP_5__AXI2DAGBBaseAddr_MASK 0xfffffff |
| #define ACP_DAGB_BASE_ADDR_GRP_5__AXI2DAGBBaseAddr__SHIFT 0x0 |
| #define ACP_DAGB_BASE_ADDR_GRP_5__AXI2DAGBSnoopSel_MASK 0x20000000 |
| #define ACP_DAGB_BASE_ADDR_GRP_5__AXI2DAGBSnoopSel__SHIFT 0x1d |
| #define ACP_DAGB_BASE_ADDR_GRP_5__AXI2DAGBTargetMemSel_MASK 0x40000000 |
| #define ACP_DAGB_BASE_ADDR_GRP_5__AXI2DAGBTargetMemSel__SHIFT 0x1e |
| #define ACP_DAGB_BASE_ADDR_GRP_5__AXI2DAGBGrpEnable_MASK 0x80000000 |
| #define ACP_DAGB_BASE_ADDR_GRP_5__AXI2DAGBGrpEnable__SHIFT 0x1f |
| #define ACP_DAGB_PAGE_SIZE_GRP_6__AXI2DAGBPageSize_MASK 0x3 |
| #define ACP_DAGB_PAGE_SIZE_GRP_6__AXI2DAGBPageSize__SHIFT 0x0 |
| #define ACP_DAGB_BASE_ADDR_GRP_6__AXI2DAGBBaseAddr_MASK 0xfffffff |
| #define ACP_DAGB_BASE_ADDR_GRP_6__AXI2DAGBBaseAddr__SHIFT 0x0 |
| #define ACP_DAGB_BASE_ADDR_GRP_6__AXI2DAGBSnoopSel_MASK 0x20000000 |
| #define ACP_DAGB_BASE_ADDR_GRP_6__AXI2DAGBSnoopSel__SHIFT 0x1d |
| #define ACP_DAGB_BASE_ADDR_GRP_6__AXI2DAGBTargetMemSel_MASK 0x40000000 |
| #define ACP_DAGB_BASE_ADDR_GRP_6__AXI2DAGBTargetMemSel__SHIFT 0x1e |
| #define ACP_DAGB_BASE_ADDR_GRP_6__AXI2DAGBGrpEnable_MASK 0x80000000 |
| #define ACP_DAGB_BASE_ADDR_GRP_6__AXI2DAGBGrpEnable__SHIFT 0x1f |
| #define ACP_DAGB_PAGE_SIZE_GRP_7__AXI2DAGBPageSize_MASK 0x3 |
| #define ACP_DAGB_PAGE_SIZE_GRP_7__AXI2DAGBPageSize__SHIFT 0x0 |
| #define ACP_DAGB_BASE_ADDR_GRP_7__AXI2DAGBBaseAddr_MASK 0xfffffff |
| #define ACP_DAGB_BASE_ADDR_GRP_7__AXI2DAGBBaseAddr__SHIFT 0x0 |
| #define ACP_DAGB_BASE_ADDR_GRP_7__AXI2DAGBSnoopSel_MASK 0x20000000 |
| #define ACP_DAGB_BASE_ADDR_GRP_7__AXI2DAGBSnoopSel__SHIFT 0x1d |
| #define ACP_DAGB_BASE_ADDR_GRP_7__AXI2DAGBTargetMemSel_MASK 0x40000000 |
| #define ACP_DAGB_BASE_ADDR_GRP_7__AXI2DAGBTargetMemSel__SHIFT 0x1e |
| #define ACP_DAGB_BASE_ADDR_GRP_7__AXI2DAGBGrpEnable_MASK 0x80000000 |
| #define ACP_DAGB_BASE_ADDR_GRP_7__AXI2DAGBGrpEnable__SHIFT 0x1f |
| #define ACP_DAGB_PAGE_SIZE_GRP_8__AXI2DAGBPageSize_MASK 0x3 |
| #define ACP_DAGB_PAGE_SIZE_GRP_8__AXI2DAGBPageSize__SHIFT 0x0 |
| #define ACP_DAGB_BASE_ADDR_GRP_8__AXI2DAGBBaseAddr_MASK 0xfffffff |
| #define ACP_DAGB_BASE_ADDR_GRP_8__AXI2DAGBBaseAddr__SHIFT 0x0 |
| #define ACP_DAGB_BASE_ADDR_GRP_8__AXI2DAGBSnoopSel_MASK 0x20000000 |
| #define ACP_DAGB_BASE_ADDR_GRP_8__AXI2DAGBSnoopSel__SHIFT 0x1d |
| #define ACP_DAGB_BASE_ADDR_GRP_8__AXI2DAGBTargetMemSel_MASK 0x40000000 |
| #define ACP_DAGB_BASE_ADDR_GRP_8__AXI2DAGBTargetMemSel__SHIFT 0x1e |
| #define ACP_DAGB_BASE_ADDR_GRP_8__AXI2DAGBGrpEnable_MASK 0x80000000 |
| #define ACP_DAGB_BASE_ADDR_GRP_8__AXI2DAGBGrpEnable__SHIFT 0x1f |
| #define ACP_DAGB_ATU_CTRL__AXI2DAGBCacheInvalidate_MASK 0x1 |
| #define ACP_DAGB_ATU_CTRL__AXI2DAGBCacheInvalidate__SHIFT 0x0 |
| #define ACP_CONTROL__ClkEn_MASK 0x1 |
| #define ACP_CONTROL__ClkEn__SHIFT 0x0 |
| #define ACP_CONTROL__JtagEn_MASK 0x400 |
| #define ACP_CONTROL__JtagEn__SHIFT 0xa |
| #define ACP_STATUS__ClkOn_MASK 0x1 |
| #define ACP_STATUS__ClkOn__SHIFT 0x0 |
| #define ACP_STATUS__ACPRefClkSpd_MASK 0x2 |
| #define ACP_STATUS__ACPRefClkSpd__SHIFT 0x1 |
| #define ACP_STATUS__SMUStutterLastEdge_MASK 0x4 |
| #define ACP_STATUS__SMUStutterLastEdge__SHIFT 0x2 |
| #define ACP_STATUS__MCStutterLastEdge_MASK 0x8 |
| #define ACP_STATUS__MCStutterLastEdge__SHIFT 0x3 |
| #define ACP_SOFT_RESET__SoftResetAud_MASK 0x100 |
| #define ACP_SOFT_RESET__SoftResetAud__SHIFT 0x8 |
| #define ACP_SOFT_RESET__SoftResetDMA_MASK 0x200 |
| #define ACP_SOFT_RESET__SoftResetDMA__SHIFT 0x9 |
| #define ACP_SOFT_RESET__InternalSoftResetMode_MASK 0x4000 |
| #define ACP_SOFT_RESET__InternalSoftResetMode__SHIFT 0xe |
| #define ACP_SOFT_RESET__ExternalSoftResetMode_MASK 0x8000 |
| #define ACP_SOFT_RESET__ExternalSoftResetMode__SHIFT 0xf |
| #define ACP_SOFT_RESET__SoftResetAudDone_MASK 0x1000000 |
| #define ACP_SOFT_RESET__SoftResetAudDone__SHIFT 0x18 |
| #define ACP_SOFT_RESET__SoftResetDMADone_MASK 0x2000000 |
| #define ACP_SOFT_RESET__SoftResetDMADone__SHIFT 0x19 |
| #define ACP_PwrMgmt_CNTL__SCLKSleepCntl_MASK 0x3 |
| #define ACP_PwrMgmt_CNTL__SCLKSleepCntl__SHIFT 0x0 |
| #define ACP_CAC_INDICATOR_CONTROL__ACP_Cac_Indicator_Counter_MASK 0xffff |
| #define ACP_CAC_INDICATOR_CONTROL__ACP_Cac_Indicator_Counter__SHIFT 0x0 |
| #define ACP_SMU_MAILBOX__ACP_SMU_Mailbox_MASK 0xffffffff |
| #define ACP_SMU_MAILBOX__ACP_SMU_Mailbox__SHIFT 0x0 |
| #define ACP_FUTURE_REG_SCLK_0__ACPFutureReg_MASK 0xffffffff |
| #define ACP_FUTURE_REG_SCLK_0__ACPFutureReg__SHIFT 0x0 |
| #define ACP_FUTURE_REG_SCLK_1__ACPFutureReg_MASK 0xffffffff |
| #define ACP_FUTURE_REG_SCLK_1__ACPFutureReg__SHIFT 0x0 |
| #define ACP_FUTURE_REG_SCLK_2__ACPFutureReg_MASK 0xffffffff |
| #define ACP_FUTURE_REG_SCLK_2__ACPFutureReg__SHIFT 0x0 |
| #define ACP_FUTURE_REG_SCLK_3__ACPFutureReg_MASK 0xffffffff |
| #define ACP_FUTURE_REG_SCLK_3__ACPFutureReg__SHIFT 0x0 |
| #define ACP_FUTURE_REG_SCLK_4__ACPFutureReg_MASK 0xffffffff |
| #define ACP_FUTURE_REG_SCLK_4__ACPFutureReg__SHIFT 0x0 |
| #define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_wr_ask_cnt_enable_MASK 0x1 |
| #define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_wr_ask_cnt_enable__SHIFT 0x0 |
| #define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_wr_go_cnt_enable_MASK 0x2 |
| #define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_wr_go_cnt_enable__SHIFT 0x1 |
| #define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_wr_exp_respcnt_enable_MASK 0x4 |
| #define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_wr_exp_respcnt_enable__SHIFT 0x2 |
| #define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_wr_actual_respcnt_enable_MASK 0x8 |
| #define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_wr_actual_respcnt_enable__SHIFT 0x3 |
| #define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_rd_ask_cnt_enable_MASK 0x10 |
| #define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_rd_ask_cnt_enable__SHIFT 0x4 |
| #define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_rd_go_cnt_enable_MASK 0x20 |
| #define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_rd_go_cnt_enable__SHIFT 0x5 |
| #define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_rd_exp_respcnt_enable_MASK 0x40 |
| #define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_rd_exp_respcnt_enable__SHIFT 0x6 |
| #define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_rd_actual_respcnt_enable_MASK 0x80 |
| #define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_rd_actual_respcnt_enable__SHIFT 0x7 |
| #define ACP_DAGB_DEBUG_CNT_ENABLE__onion_wr_ask_cnt_enable_MASK 0x100 |
| #define ACP_DAGB_DEBUG_CNT_ENABLE__onion_wr_ask_cnt_enable__SHIFT 0x8 |
| #define ACP_DAGB_DEBUG_CNT_ENABLE__onion_wr_go_cnt_enable_MASK 0x200 |
| #define ACP_DAGB_DEBUG_CNT_ENABLE__onion_wr_go_cnt_enable__SHIFT 0x9 |
| #define ACP_DAGB_DEBUG_CNT_ENABLE__onion_wr_exp_respcnt_enable_MASK 0x400 |
| #define ACP_DAGB_DEBUG_CNT_ENABLE__onion_wr_exp_respcnt_enable__SHIFT 0xa |
| #define ACP_DAGB_DEBUG_CNT_ENABLE__onion_wr_actual_respcnt_enable_MASK 0x800 |
| #define ACP_DAGB_DEBUG_CNT_ENABLE__onion_wr_actual_respcnt_enable__SHIFT 0xb |
| #define ACP_DAGB_DEBUG_CNT_ENABLE__onion_rd_ask_cnt_enable_MASK 0x1000 |
| #define ACP_DAGB_DEBUG_CNT_ENABLE__onion_rd_ask_cnt_enable__SHIFT 0xc |
| #define ACP_DAGB_DEBUG_CNT_ENABLE__onion_rd_go_cnt_enable_MASK 0x2000 |
| #define ACP_DAGB_DEBUG_CNT_ENABLE__onion_rd_go_cnt_enable__SHIFT 0xd |
| #define ACP_DAGB_DEBUG_CNT_ENABLE__onion_rd_exp_respcnt_enable_MASK 0x4000 |
| #define ACP_DAGB_DEBUG_CNT_ENABLE__onion_rd_exp_respcnt_enable__SHIFT 0xe |
| #define ACP_DAGB_DEBUG_CNT_ENABLE__onion_rd_actual_respcnt_enable_MASK 0x8000 |
| #define ACP_DAGB_DEBUG_CNT_ENABLE__onion_rd_actual_respcnt_enable__SHIFT 0xf |
| #define ACP_DAGBG_WR_ASK_CNT__garlic_wr_only_ask_cnt_MASK 0xffff |
| #define ACP_DAGBG_WR_ASK_CNT__garlic_wr_only_ask_cnt__SHIFT 0x0 |
| #define ACP_DAGBG_WR_GO_CNT__garlic_wr_only_go_cnt_MASK 0xffff |
| #define ACP_DAGBG_WR_GO_CNT__garlic_wr_only_go_cnt__SHIFT 0x0 |
| #define ACP_DAGBG_WR_EXP_RESP_CNT__garlic_wr_exp_resp_cnt_MASK 0xffff |
| #define ACP_DAGBG_WR_EXP_RESP_CNT__garlic_wr_exp_resp_cnt__SHIFT 0x0 |
| #define ACP_DAGBG_WR_ACTUAL_RESP_CNT__garlic_wr_actual_resp_cnt_MASK 0xffff |
| #define ACP_DAGBG_WR_ACTUAL_RESP_CNT__garlic_wr_actual_resp_cnt__SHIFT 0x0 |
| #define ACP_DAGBG_RD_ASK_CNT__garlic_rd_only_ask_cnt_MASK 0xffff |
| #define ACP_DAGBG_RD_ASK_CNT__garlic_rd_only_ask_cnt__SHIFT 0x0 |
| #define ACP_DAGBG_RD_GO_CNT__garlic_rd_only_go_cnt_MASK 0xffff |
| #define ACP_DAGBG_RD_GO_CNT__garlic_rd_only_go_cnt__SHIFT 0x0 |
| #define ACP_DAGBG_RD_EXP_RESP_CNT__garlic_rd_exp_resp_cnt_MASK 0xffff |
| #define ACP_DAGBG_RD_EXP_RESP_CNT__garlic_rd_exp_resp_cnt__SHIFT 0x0 |
| #define ACP_DAGBG_RD_ACTUAL_RESP_CNT__garlic_rd_actual_resp_cnt_MASK 0xffff |
| #define ACP_DAGBG_RD_ACTUAL_RESP_CNT__garlic_rd_actual_resp_cnt__SHIFT 0x0 |
| #define ACP_DAGBO_WR_ASK_CNT__onion_wr_only_ask_cnt_MASK 0xffff |
| #define ACP_DAGBO_WR_ASK_CNT__onion_wr_only_ask_cnt__SHIFT 0x0 |
| #define ACP_DAGBO_WR_GO_CNT__onion_wr_only_go_cnt_MASK 0xffff |
| #define ACP_DAGBO_WR_GO_CNT__onion_wr_only_go_cnt__SHIFT 0x0 |
| #define ACP_DAGBO_WR_EXP_RESP_CNT__onion_wr_exp_resp_cnt_MASK 0xffff |
| #define ACP_DAGBO_WR_EXP_RESP_CNT__onion_wr_exp_resp_cnt__SHIFT 0x0 |
| #define ACP_DAGBO_WR_ACTUAL_RESP_CNT__onion_wr_actual_resp_cnt_MASK 0xffff |
| #define ACP_DAGBO_WR_ACTUAL_RESP_CNT__onion_wr_actual_resp_cnt__SHIFT 0x0 |
| #define ACP_DAGBO_RD_ASK_CNT__onion_rd_only_ask_cnt_MASK 0xffff |
| #define ACP_DAGBO_RD_ASK_CNT__onion_rd_only_ask_cnt__SHIFT 0x0 |
| #define ACP_DAGBO_RD_GO_CNT__onion_rd_only_go_cnt_MASK 0xffff |
| #define ACP_DAGBO_RD_GO_CNT__onion_rd_only_go_cnt__SHIFT 0x0 |
| #define ACP_DAGBO_RD_EXP_RESP_CNT__onion_rd_exp_resp_cnt_MASK 0xffff |
| #define ACP_DAGBO_RD_EXP_RESP_CNT__onion_rd_exp_resp_cnt__SHIFT 0x0 |
| #define ACP_DAGBO_RD_ACTUAL_RESP_CNT__onion_rd_actual_resp_cnt_MASK 0xffff |
| #define ACP_DAGBO_RD_ACTUAL_RESP_CNT__onion_rd_actual_resp_cnt__SHIFT 0x0 |
| #define ACP_BRB_CONTROL__BRB_BlockSharedRAMArbCntrl_MASK 0xf |
| #define ACP_BRB_CONTROL__BRB_BlockSharedRAMArbCntrl__SHIFT 0x0 |
| #define ACP_EXTERNAL_INTR_ENB__ACPExtIntrEnb_MASK 0x1 |
| #define ACP_EXTERNAL_INTR_ENB__ACPExtIntrEnb__SHIFT 0x0 |
| #define ACP_EXTERNAL_INTR_CNTL__ACPErrMask_MASK 0x1 |
| #define ACP_EXTERNAL_INTR_CNTL__ACPErrMask__SHIFT 0x0 |
| #define ACP_EXTERNAL_INTR_CNTL__I2SMicDataAvMask_MASK 0x2 |
| #define ACP_EXTERNAL_INTR_CNTL__I2SMicDataAvMask__SHIFT 0x1 |
| #define ACP_EXTERNAL_INTR_CNTL__I2SSpkr0DataEmptyMask_MASK 0x4 |
| #define ACP_EXTERNAL_INTR_CNTL__I2SSpkr0DataEmptyMask__SHIFT 0x2 |
| #define ACP_EXTERNAL_INTR_CNTL__I2SSpkr1DataEmptyMask_MASK 0x8 |
| #define ACP_EXTERNAL_INTR_CNTL__I2SSpkr1DataEmptyMask__SHIFT 0x3 |
| #define ACP_EXTERNAL_INTR_CNTL__I2SBTDataAvMask_MASK 0x10 |
| #define ACP_EXTERNAL_INTR_CNTL__I2SBTDataAvMask__SHIFT 0x4 |
| #define ACP_EXTERNAL_INTR_CNTL__AzaliaIntrMask_MASK 0x40 |
| #define ACP_EXTERNAL_INTR_CNTL__AzaliaIntrMask__SHIFT 0x6 |
| #define ACP_EXTERNAL_INTR_CNTL__DSP0TimeoutMask_MASK 0x100 |
| #define ACP_EXTERNAL_INTR_CNTL__DSP0TimeoutMask__SHIFT 0x8 |
| #define ACP_EXTERNAL_INTR_CNTL__DSP1TimeoutMask_MASK 0x200 |
| #define ACP_EXTERNAL_INTR_CNTL__DSP1TimeoutMask__SHIFT 0x9 |
| #define ACP_EXTERNAL_INTR_CNTL__DSP2TimeoutMask_MASK 0x400 |
| #define ACP_EXTERNAL_INTR_CNTL__DSP2TimeoutMask__SHIFT 0xa |
| #define ACP_EXTERNAL_INTR_CNTL__I2SBTDataEmptyMask_MASK 0x800 |
| #define ACP_EXTERNAL_INTR_CNTL__I2SBTDataEmptyMask__SHIFT 0xb |
| #define ACP_EXTERNAL_INTR_CNTL__DMAIOCMask_MASK 0xffff0000 |
| #define ACP_EXTERNAL_INTR_CNTL__DMAIOCMask__SHIFT 0x10 |
| #define ACP_ERROR_SOURCE_STS__ACPRegUdefADDRErr_MASK 0x1 |
| #define ACP_ERROR_SOURCE_STS__ACPRegUdefADDRErr__SHIFT 0x0 |
| #define ACP_ERROR_SOURCE_STS__ACPRegUdefADDRErrSource_MASK 0xe |
| #define ACP_ERROR_SOURCE_STS__ACPRegUdefADDRErrSource__SHIFT 0x1 |
| #define ACP_ERROR_SOURCE_STS__ACPRegUdefADDRErrSourceOver_MASK 0x10 |
| #define ACP_ERROR_SOURCE_STS__ACPRegUdefADDRErrSourceOver__SHIFT 0x4 |
| #define ACP_ERROR_SOURCE_STS__BRBAddrErr_MASK 0x20 |
| #define ACP_ERROR_SOURCE_STS__BRBAddrErr__SHIFT 0x5 |
| #define ACP_ERROR_SOURCE_STS__BRBAddrErrSource_MASK 0x3c0 |
| #define ACP_ERROR_SOURCE_STS__BRBAddrErrSource__SHIFT 0x6 |
| #define ACP_ERROR_SOURCE_STS__BRBAddrErrSourceOver_MASK 0x400 |
| #define ACP_ERROR_SOURCE_STS__BRBAddrErrSourceOver__SHIFT 0xa |
| #define ACP_ERROR_SOURCE_STS__I2SMicOverFlowErr_MASK 0x800 |
| #define ACP_ERROR_SOURCE_STS__I2SMicOverFlowErr__SHIFT 0xb |
| #define ACP_ERROR_SOURCE_STS__I2SSpeaker0OverFlowErr_MASK 0x1000 |
| #define ACP_ERROR_SOURCE_STS__I2SSpeaker0OverFlowErr__SHIFT 0xc |
| #define ACP_ERROR_SOURCE_STS__I2SSpeaker1OverFlowErr_MASK 0x2000 |
| #define ACP_ERROR_SOURCE_STS__I2SSpeaker1OverFlowErr__SHIFT 0xd |
| #define ACP_ERROR_SOURCE_STS__I2SBTRxFifoOverFlowErr_MASK 0x4000 |
| #define ACP_ERROR_SOURCE_STS__I2SBTRxFifoOverFlowErr__SHIFT 0xe |
| #define ACP_ERROR_SOURCE_STS__DSPAdrTransRangeErr_MASK 0x8000 |
| #define ACP_ERROR_SOURCE_STS__DSPAdrTransRangeErr__SHIFT 0xf |
| #define ACP_ERROR_SOURCE_STS__DSPAdrTransRangeErrSource_MASK 0x70000 |
| #define ACP_ERROR_SOURCE_STS__DSPAdrTransRangeErrSource__SHIFT 0x10 |
| #define ACP_ERROR_SOURCE_STS__DSPAdrTransRangeErrSourceOver_MASK 0x80000 |
| #define ACP_ERROR_SOURCE_STS__DSPAdrTransRangeErrSourceOver__SHIFT 0x13 |
| #define ACP_ERROR_SOURCE_STS__DAGBErr_MASK 0x100000 |
| #define ACP_ERROR_SOURCE_STS__DAGBErr__SHIFT 0x14 |
| #define ACP_ERROR_SOURCE_STS__DAGBErrSource_MASK 0x1e00000 |
| #define ACP_ERROR_SOURCE_STS__DAGBErrSource__SHIFT 0x15 |
| #define ACP_ERROR_SOURCE_STS__DAGBErrSourceOver_MASK 0x2000000 |
| #define ACP_ERROR_SOURCE_STS__DAGBErrSourceOver__SHIFT 0x19 |
| #define ACP_ERROR_SOURCE_STS__DMATermOnErr_MASK 0x4000000 |
| #define ACP_ERROR_SOURCE_STS__DMATermOnErr__SHIFT 0x1a |
| #define ACP_ERROR_SOURCE_STS__I2SBTTxFifoOverFlowErr_MASK 0x10000000 |
| #define ACP_ERROR_SOURCE_STS__I2SBTTxFifoOverFlowErr__SHIFT 0x1c |
| #define ACP_DSP_SW_INTR_TRIG__TrigSWIntHostDSP0_MASK 0x1 |
| #define ACP_DSP_SW_INTR_TRIG__TrigSWIntHostDSP0__SHIFT 0x0 |
| #define ACP_DSP_SW_INTR_TRIG__TrigSWIntHostDSP1_MASK 0x2 |
| #define ACP_DSP_SW_INTR_TRIG__TrigSWIntHostDSP1__SHIFT 0x1 |
| #define ACP_DSP_SW_INTR_TRIG__TrigSWIntHostDSP2_MASK 0x4 |
| #define ACP_DSP_SW_INTR_TRIG__TrigSWIntHostDSP2__SHIFT 0x2 |
| #define ACP_DSP_SW_INTR_TRIG__TrigSWIntDSPnDSP0_MASK 0x100 |
| #define ACP_DSP_SW_INTR_TRIG__TrigSWIntDSPnDSP0__SHIFT 0x8 |
| #define ACP_DSP_SW_INTR_TRIG__TrigSWIntDSPnDSP1_MASK 0x200 |
| #define ACP_DSP_SW_INTR_TRIG__TrigSWIntDSPnDSP1__SHIFT 0x9 |
| #define ACP_DSP_SW_INTR_TRIG__TrigSWIntDSPnDSP2_MASK 0x400 |
| #define ACP_DSP_SW_INTR_TRIG__TrigSWIntDSPnDSP2__SHIFT 0xa |
| #define ACP_DSP_SW_INTR_TRIG__TrigSWIntDSP0Host_MASK 0x10000 |
| #define ACP_DSP_SW_INTR_TRIG__TrigSWIntDSP0Host__SHIFT 0x10 |
| #define ACP_DSP_SW_INTR_TRIG__TrigSWIntDSP1Host_MASK 0x20000 |
| #define ACP_DSP_SW_INTR_TRIG__TrigSWIntDSP1Host__SHIFT 0x11 |
| #define ACP_DSP_SW_INTR_TRIG__TrigSWIntDSP2Host_MASK 0x40000 |
| #define ACP_DSP_SW_INTR_TRIG__TrigSWIntDSP2Host__SHIFT 0x12 |
| #define ACP_DSP_SW_INTR_CNTL__EnbSWIntHostDSP0_MASK 0x1 |
| #define ACP_DSP_SW_INTR_CNTL__EnbSWIntHostDSP0__SHIFT 0x0 |
| #define ACP_DSP_SW_INTR_CNTL__EnbSWIntHostDSP1_MASK 0x2 |
| #define ACP_DSP_SW_INTR_CNTL__EnbSWIntHostDSP1__SHIFT 0x1 |
| #define ACP_DSP_SW_INTR_CNTL__EnbSWIntHostDSP2_MASK 0x4 |
| #define ACP_DSP_SW_INTR_CNTL__EnbSWIntHostDSP2__SHIFT 0x2 |
| #define ACP_DSP_SW_INTR_CNTL__EnbSWIntDSPnDSP0_MASK 0x100 |
| #define ACP_DSP_SW_INTR_CNTL__EnbSWIntDSPnDSP0__SHIFT 0x8 |
| #define ACP_DSP_SW_INTR_CNTL__EnbSWIntDSPnDSP1_MASK 0x200 |
| #define ACP_DSP_SW_INTR_CNTL__EnbSWIntDSPnDSP1__SHIFT 0x9 |
| #define ACP_DSP_SW_INTR_CNTL__EnbSWIntDSPnDSP2_MASK 0x400 |
| #define ACP_DSP_SW_INTR_CNTL__EnbSWIntDSPnDSP2__SHIFT 0xa |
| #define ACP_DSP_SW_INTR_CNTL__EnbKernelIntrDSP0Mask_MASK 0x10000 |
| #define ACP_DSP_SW_INTR_CNTL__EnbKernelIntrDSP0Mask__SHIFT 0x10 |
| #define ACP_DSP_SW_INTR_CNTL__EmbKernelIntrDSP1Mask_MASK 0x20000 |
| #define ACP_DSP_SW_INTR_CNTL__EmbKernelIntrDSP1Mask__SHIFT 0x11 |
| #define ACP_DSP_SW_INTR_CNTL__EmbKernelIntrDSP2Mask_MASK 0x40000 |
| #define ACP_DSP_SW_INTR_CNTL__EmbKernelIntrDSP2Mask__SHIFT 0x12 |
| #define ACP_DAGBG_TIMEOUT_CNTL__DAGBGTimeoutValue_MASK 0x3ffff |
| #define ACP_DAGBG_TIMEOUT_CNTL__DAGBGTimeoutValue__SHIFT 0x0 |
| #define ACP_DAGBG_TIMEOUT_CNTL__CntEn_MASK 0x80000000 |
| #define ACP_DAGBG_TIMEOUT_CNTL__CntEn__SHIFT 0x1f |
| #define ACP_DAGBO_TIMEOUT_CNTL__DAGBOTimeoutValue_MASK 0x3ffff |
| #define ACP_DAGBO_TIMEOUT_CNTL__DAGBOTimeoutValue__SHIFT 0x0 |
| #define ACP_DAGBO_TIMEOUT_CNTL__CntEn_MASK 0x80000000 |
| #define ACP_DAGBO_TIMEOUT_CNTL__CntEn__SHIFT 0x1f |
| #define ACP_EXTERNAL_INTR_STAT__ACPErrStat_MASK 0x1 |
| #define ACP_EXTERNAL_INTR_STAT__ACPErrStat__SHIFT 0x0 |
| #define ACP_EXTERNAL_INTR_STAT__ACPErrAck_MASK 0x1 |
| #define ACP_EXTERNAL_INTR_STAT__ACPErrAck__SHIFT 0x0 |
| #define ACP_EXTERNAL_INTR_STAT__I2SMicDataAvStat_MASK 0x2 |
| #define ACP_EXTERNAL_INTR_STAT__I2SMicDataAvStat__SHIFT 0x1 |
| #define ACP_EXTERNAL_INTR_STAT__I2SMicDataAvAck_MASK 0x2 |
| #define ACP_EXTERNAL_INTR_STAT__I2SMicDataAvAck__SHIFT 0x1 |
| #define ACP_EXTERNAL_INTR_STAT__I2SSpkr0DataEmptyStat_MASK 0x4 |
| #define ACP_EXTERNAL_INTR_STAT__I2SSpkr0DataEmptyStat__SHIFT 0x2 |
| #define ACP_EXTERNAL_INTR_STAT__I2SSpkr0DataEmptyAck_MASK 0x4 |
| #define ACP_EXTERNAL_INTR_STAT__I2SSpkr0DataEmptyAck__SHIFT 0x2 |
| #define ACP_EXTERNAL_INTR_STAT__I2SSpkr1DataEmptyStat_MASK 0x8 |
| #define ACP_EXTERNAL_INTR_STAT__I2SSpkr1DataEmptyStat__SHIFT 0x3 |
| #define ACP_EXTERNAL_INTR_STAT__I2SSpkr1DataEmptyAck_MASK 0x8 |
| #define ACP_EXTERNAL_INTR_STAT__I2SSpkr1DataEmptyAck__SHIFT 0x3 |
| #define ACP_EXTERNAL_INTR_STAT__I2SBTDataAvStat_MASK 0x10 |
| #define ACP_EXTERNAL_INTR_STAT__I2SBTDataAvStat__SHIFT 0x4 |
| #define ACP_EXTERNAL_INTR_STAT__I2SBTDataAvAck_MASK 0x10 |
| #define ACP_EXTERNAL_INTR_STAT__I2SBTDataAvAck__SHIFT 0x4 |
| #define ACP_EXTERNAL_INTR_STAT__AzaliaIntrStat_MASK 0x40 |
| #define ACP_EXTERNAL_INTR_STAT__AzaliaIntrStat__SHIFT 0x6 |
| #define ACP_EXTERNAL_INTR_STAT__AzaliaIntrAck_MASK 0x40 |
| #define ACP_EXTERNAL_INTR_STAT__AzaliaIntrAck__SHIFT 0x6 |
| #define ACP_EXTERNAL_INTR_STAT__DSP0TimeoutStat_MASK 0x100 |
| #define ACP_EXTERNAL_INTR_STAT__DSP0TimeoutStat__SHIFT 0x8 |
| #define ACP_EXTERNAL_INTR_STAT__DSP0TimeoutAck_MASK 0x100 |
| #define ACP_EXTERNAL_INTR_STAT__DSP0TimeoutAck__SHIFT 0x8 |
| #define ACP_EXTERNAL_INTR_STAT__DSP1TimeoutStat_MASK 0x200 |
| #define ACP_EXTERNAL_INTR_STAT__DSP1TimeoutStat__SHIFT 0x9 |
| #define ACP_EXTERNAL_INTR_STAT__DSP1TimeoutAck_MASK 0x200 |
| #define ACP_EXTERNAL_INTR_STAT__DSP1TimeoutAck__SHIFT 0x9 |
| #define ACP_EXTERNAL_INTR_STAT__DSP2TimeoutStat_MASK 0x400 |
| #define ACP_EXTERNAL_INTR_STAT__DSP2TimeoutStat__SHIFT 0xa |
| #define ACP_EXTERNAL_INTR_STAT__DSP2TimeoutAck_MASK 0x400 |
| #define ACP_EXTERNAL_INTR_STAT__DSP2TimeoutAck__SHIFT 0xa |
| #define ACP_EXTERNAL_INTR_STAT__I2SBTDataEmptyStat_MASK 0x800 |
| #define ACP_EXTERNAL_INTR_STAT__I2SBTDataEmptyStat__SHIFT 0xb |
| #define ACP_EXTERNAL_INTR_STAT__I2SBTDataEmptyAck_MASK 0x800 |
| #define ACP_EXTERNAL_INTR_STAT__I2SBTDataEmptyAck__SHIFT 0xb |
| #define ACP_EXTERNAL_INTR_STAT__DMAIOCStat_MASK 0xffff0000 |
| #define ACP_EXTERNAL_INTR_STAT__DMAIOCStat__SHIFT 0x10 |
| #define ACP_EXTERNAL_INTR_STAT__DMAIOCAck_MASK 0xffff0000 |
| #define ACP_EXTERNAL_INTR_STAT__DMAIOCAck__SHIFT 0x10 |
| #define ACP_DSP_SW_INTR_STAT__SWIntHostDSP0Stat_MASK 0x1 |
| #define ACP_DSP_SW_INTR_STAT__SWIntHostDSP0Stat__SHIFT 0x0 |
| #define ACP_DSP_SW_INTR_STAT__SWIntHostDSP0Ack_MASK 0x1 |
| #define ACP_DSP_SW_INTR_STAT__SWIntHostDSP0Ack__SHIFT 0x0 |
| #define ACP_DSP_SW_INTR_STAT__SWIntHostDSP1Stat_MASK 0x2 |
| #define ACP_DSP_SW_INTR_STAT__SWIntHostDSP1Stat__SHIFT 0x1 |
| #define ACP_DSP_SW_INTR_STAT__SWIntHostDSP1Ack_MASK 0x2 |
| #define ACP_DSP_SW_INTR_STAT__SWIntHostDSP1Ack__SHIFT 0x1 |
| #define ACP_DSP_SW_INTR_STAT__SWIntHostDSP2Stat_MASK 0x4 |
| #define ACP_DSP_SW_INTR_STAT__SWIntHostDSP2Stat__SHIFT 0x2 |
| #define ACP_DSP_SW_INTR_STAT__SWIntHostDSP2Ack_MASK 0x4 |
| #define ACP_DSP_SW_INTR_STAT__SWIntHostDSP2Ack__SHIFT 0x2 |
| #define ACP_DSP_SW_INTR_STAT__SWIntDSPnDSP0Stat_MASK 0x100 |
| #define ACP_DSP_SW_INTR_STAT__SWIntDSPnDSP0Stat__SHIFT 0x8 |
| #define ACP_DSP_SW_INTR_STAT__SWIntDSPnDSP0Ack_MASK 0x100 |
| #define ACP_DSP_SW_INTR_STAT__SWIntDSPnDSP0Ack__SHIFT 0x8 |
| #define ACP_DSP_SW_INTR_STAT__SWIntDSPnDSP1Stat_MASK 0x200 |
| #define ACP_DSP_SW_INTR_STAT__SWIntDSPnDSP1Stat__SHIFT 0x9 |
| #define ACP_DSP_SW_INTR_STAT__SWIntDSPnDSP1Ack_MASK 0x200 |
| #define ACP_DSP_SW_INTR_STAT__SWIntDSPnDSP1Ack__SHIFT 0x9 |
| #define ACP_DSP_SW_INTR_STAT__SWIntDSPnDSP2Stat_MASK 0x400 |
| #define ACP_DSP_SW_INTR_STAT__SWIntDSPnDSP2Stat__SHIFT 0xa |
| #define ACP_DSP_SW_INTR_STAT__SWIntDSPnDSP2Ack_MASK 0x400 |
| #define ACP_DSP_SW_INTR_STAT__SWIntDSPnDSP2Ack__SHIFT 0xa |
| #define ACP_DSP_SW_INTR_STAT__SWKernelIntrDSP0Stat_MASK 0x10000 |
| #define ACP_DSP_SW_INTR_STAT__SWKernelIntrDSP0Stat__SHIFT 0x10 |
| #define ACP_DSP_SW_INTR_STAT__SWKernelIntrDSP0Ack_MASK 0x10000 |
| #define ACP_DSP_SW_INTR_STAT__SWKernelIntrDSP0Ack__SHIFT 0x10 |
| #define ACP_DSP_SW_INTR_STAT__SWKernelIntrDSP1Stat_MASK 0x20000 |
| #define ACP_DSP_SW_INTR_STAT__SWKernelIntrDSP1Stat__SHIFT 0x11 |
| #define ACP_DSP_SW_INTR_STAT__SWKernelIntrDSP1Ack_MASK 0x20000 |
| #define ACP_DSP_SW_INTR_STAT__SWKernelIntrDSP1Ack__SHIFT 0x11 |
| #define ACP_DSP_SW_INTR_STAT__SWKernelIntrDSP2Stat_MASK 0x40000 |
| #define ACP_DSP_SW_INTR_STAT__SWKernelIntrDSP2Stat__SHIFT 0x12 |
| #define ACP_DSP_SW_INTR_STAT__SWKernelIntrDSP2Ack_MASK 0x40000 |
| #define ACP_DSP_SW_INTR_STAT__SWKernelIntrDSP2Ack__SHIFT 0x12 |
| #define ACP_DSP0_INTR_CNTL__ACPErrMask_MASK 0x1 |
| #define ACP_DSP0_INTR_CNTL__ACPErrMask__SHIFT 0x0 |
| #define ACP_DSP0_INTR_CNTL__I2SMicDataAvMask_MASK 0x2 |
| #define ACP_DSP0_INTR_CNTL__I2SMicDataAvMask__SHIFT 0x1 |
| #define ACP_DSP0_INTR_CNTL__I2SSpkr0DataEmptyMask_MASK 0x4 |
| #define ACP_DSP0_INTR_CNTL__I2SSpkr0DataEmptyMask__SHIFT 0x2 |
| #define ACP_DSP0_INTR_CNTL__I2SSpkr1DataEmptyMask_MASK 0x8 |
| #define ACP_DSP0_INTR_CNTL__I2SSpkr1DataEmptyMask__SHIFT 0x3 |
| #define ACP_DSP0_INTR_CNTL__I2SBTDataAvMask_MASK 0x10 |
| #define ACP_DSP0_INTR_CNTL__I2SBTDataAvMask__SHIFT 0x4 |
| #define ACP_DSP0_INTR_CNTL__AzaliaIntrMask_MASK 0x40 |
| #define ACP_DSP0_INTR_CNTL__AzaliaIntrMask__SHIFT 0x6 |
| #define ACP_DSP0_INTR_CNTL__SMUMailboxWriteMask_MASK 0x100 |
| #define ACP_DSP0_INTR_CNTL__SMUMailboxWriteMask__SHIFT 0x8 |
| #define ACP_DSP0_INTR_CNTL__SMUStutterStatusMask_MASK 0x200 |
| #define ACP_DSP0_INTR_CNTL__SMUStutterStatusMask__SHIFT 0x9 |
| #define ACP_DSP0_INTR_CNTL__MCStutterStatusMask_MASK 0x400 |
| #define ACP_DSP0_INTR_CNTL__MCStutterStatusMask__SHIFT 0xa |
| #define ACP_DSP0_INTR_CNTL__DSPExtTimerMask_MASK 0x800 |
| #define ACP_DSP0_INTR_CNTL__DSPExtTimerMask__SHIFT 0xb |
| #define ACP_DSP0_INTR_CNTL__DSPSemRespMask_MASK 0x1000 |
| #define ACP_DSP0_INTR_CNTL__DSPSemRespMask__SHIFT 0xc |
| #define ACP_DSP0_INTR_CNTL__I2SBTDataEmptyMask_MASK 0x2000 |
| #define ACP_DSP0_INTR_CNTL__I2SBTDataEmptyMask__SHIFT 0xd |
| #define ACP_DSP0_INTR_CNTL__DMAIOCMask_MASK 0xffff0000 |
| #define ACP_DSP0_INTR_CNTL__DMAIOCMask__SHIFT 0x10 |
| #define ACP_DSP0_INTR_STAT__ACPErrStat_MASK 0x1 |
| #define ACP_DSP0_INTR_STAT__ACPErrStat__SHIFT 0x0 |
| #define ACP_DSP0_INTR_STAT__ACPErrAck_MASK 0x1 |
| #define ACP_DSP0_INTR_STAT__ACPErrAck__SHIFT 0x0 |
| #define ACP_DSP0_INTR_STAT__I2SMicDataAvStat_MASK 0x2 |
| #define ACP_DSP0_INTR_STAT__I2SMicDataAvStat__SHIFT 0x1 |
| #define ACP_DSP0_INTR_STAT__I2SMicDataAvAck_MASK 0x2 |
| #define ACP_DSP0_INTR_STAT__I2SMicDataAvAck__SHIFT 0x1 |
| #define ACP_DSP0_INTR_STAT__I2SSpkr0DataEmptyStat_MASK 0x4 |
| #define ACP_DSP0_INTR_STAT__I2SSpkr0DataEmptyStat__SHIFT 0x2 |
| #define ACP_DSP0_INTR_STAT__I2SSpkr0DataEmptyAck_MASK 0x4 |
| #define ACP_DSP0_INTR_STAT__I2SSpkr0DataEmptyAck__SHIFT 0x2 |
| #define ACP_DSP0_INTR_STAT__I2SSpkr1DataEmptyStat_MASK 0x8 |
| #define ACP_DSP0_INTR_STAT__I2SSpkr1DataEmptyStat__SHIFT 0x3 |
| #define ACP_DSP0_INTR_STAT__I2SSpkr1DataEmptyAck_MASK 0x8 |
| #define ACP_DSP0_INTR_STAT__I2SSpkr1DataEmptyAck__SHIFT 0x3 |
| #define ACP_DSP0_INTR_STAT__I2SBTDataAvStat_MASK 0x10 |
| #define ACP_DSP0_INTR_STAT__I2SBTDataAvStat__SHIFT 0x4 |
| #define ACP_DSP0_INTR_STAT__I2SBTDataAvAck_MASK 0x10 |
| #define ACP_DSP0_INTR_STAT__I2SBTDataAvAck__SHIFT 0x4 |
| #define ACP_DSP0_INTR_STAT__AzaliaIntrStat_MASK 0x40 |
| #define ACP_DSP0_INTR_STAT__AzaliaIntrStat__SHIFT 0x6 |
| #define ACP_DSP0_INTR_STAT__AzaliaIntrAck_MASK 0x40 |
| #define ACP_DSP0_INTR_STAT__AzaliaIntrAck__SHIFT 0x6 |
| #define ACP_DSP0_INTR_STAT__SMUMailboxWriteStat_MASK 0x100 |
| #define ACP_DSP0_INTR_STAT__SMUMailboxWriteStat__SHIFT 0x8 |
| #define ACP_DSP0_INTR_STAT__SMUMailboxWriteAck_MASK 0x100 |
| #define ACP_DSP0_INTR_STAT__SMUMailboxWriteAck__SHIFT 0x8 |
| #define ACP_DSP0_INTR_STAT__SMUStutterStatusStat_MASK 0x200 |
| #define ACP_DSP0_INTR_STAT__SMUStutterStatusStat__SHIFT 0x9 |
| #define ACP_DSP0_INTR_STAT__SMUStutterStatusAck_MASK 0x200 |
| #define ACP_DSP0_INTR_STAT__SMUStutterStatusAck__SHIFT 0x9 |
| #define ACP_DSP0_INTR_STAT__MCStutterStatusStat_MASK 0x400 |
| #define ACP_DSP0_INTR_STAT__MCStutterStatusStat__SHIFT 0xa |
| #define ACP_DSP0_INTR_STAT__MCStutterStatusAck_MASK 0x400 |
| #define ACP_DSP0_INTR_STAT__MCStutterStatusAck__SHIFT 0xa |
| #define ACP_DSP0_INTR_STAT__DSPExtTimerStat_MASK 0x800 |
| #define ACP_DSP0_INTR_STAT__DSPExtTimerStat__SHIFT 0xb |
| #define ACP_DSP0_INTR_STAT__DSPExtTimerAck_MASK 0x800 |
| #define ACP_DSP0_INTR_STAT__DSPExtTimerAck__SHIFT 0xb |
| #define ACP_DSP0_INTR_STAT__DSPSemRespStat_MASK 0x1000 |
| #define ACP_DSP0_INTR_STAT__DSPSemRespStat__SHIFT 0xc |
| #define ACP_DSP0_INTR_STAT__DSPSemRespAck_MASK 0x1000 |
| #define ACP_DSP0_INTR_STAT__DSPSemRespAck__SHIFT 0xc |
| #define ACP_DSP0_INTR_STAT__I2SBTDataEmptyStat_MASK 0x2000 |
| #define ACP_DSP0_INTR_STAT__I2SBTDataEmptyStat__SHIFT 0xd |
| #define ACP_DSP0_INTR_STAT__I2SBTDataEmptyAck_MASK 0x2000 |
| #define ACP_DSP0_INTR_STAT__I2SBTDataEmptyAck__SHIFT 0xd |
| #define ACP_DSP0_INTR_STAT__DMAIOCStat_MASK 0xffff0000 |
| #define ACP_DSP0_INTR_STAT__DMAIOCStat__SHIFT 0x10 |
| #define ACP_DSP0_INTR_STAT__DMAIOCAck_MASK 0xffff0000 |
| #define ACP_DSP0_INTR_STAT__DMAIOCAck__SHIFT 0x10 |
| #define ACP_DSP0_TIMEOUT_CNTL__DSP0TimeoutValue_MASK 0x3ffff |
| #define ACP_DSP0_TIMEOUT_CNTL__DSP0TimeoutValue__SHIFT 0x0 |
| #define ACP_DSP0_TIMEOUT_CNTL__CntEn_MASK 0x80000000 |
| #define ACP_DSP0_TIMEOUT_CNTL__CntEn__SHIFT 0x1f |
| #define ACP_DSP1_INTR_CNTL__ACPErrMask_MASK 0x1 |
| #define ACP_DSP1_INTR_CNTL__ACPErrMask__SHIFT 0x0 |
| #define ACP_DSP1_INTR_CNTL__I2SMicDataAvMask_MASK 0x2 |
| #define ACP_DSP1_INTR_CNTL__I2SMicDataAvMask__SHIFT 0x1 |
| #define ACP_DSP1_INTR_CNTL__I2SSpkr0DataEmptyMask_MASK 0x4 |
| #define ACP_DSP1_INTR_CNTL__I2SSpkr0DataEmptyMask__SHIFT 0x2 |
| #define ACP_DSP1_INTR_CNTL__I2SSpkr1DataEmptyMask_MASK 0x8 |
| #define ACP_DSP1_INTR_CNTL__I2SSpkr1DataEmptyMask__SHIFT 0x3 |
| #define ACP_DSP1_INTR_CNTL__I2SBTDataAvMask_MASK 0x10 |
| #define ACP_DSP1_INTR_CNTL__I2SBTDataAvMask__SHIFT 0x4 |
| #define ACP_DSP1_INTR_CNTL__AzaliaIntrMask_MASK 0x40 |
| #define ACP_DSP1_INTR_CNTL__AzaliaIntrMask__SHIFT 0x6 |
| #define ACP_DSP1_INTR_CNTL__SMUMailboxWriteMask_MASK 0x100 |
| #define ACP_DSP1_INTR_CNTL__SMUMailboxWriteMask__SHIFT 0x8 |
| #define ACP_DSP1_INTR_CNTL__SMUStutterStatusMask_MASK 0x200 |
| #define ACP_DSP1_INTR_CNTL__SMUStutterStatusMask__SHIFT 0x9 |
| #define ACP_DSP1_INTR_CNTL__MCStutterStatusMask_MASK 0x400 |
| #define ACP_DSP1_INTR_CNTL__MCStutterStatusMask__SHIFT 0xa |
| #define ACP_DSP1_INTR_CNTL__DSPExtTimerMask_MASK 0x800 |
| #define ACP_DSP1_INTR_CNTL__DSPExtTimerMask__SHIFT 0xb |
| #define ACP_DSP1_INTR_CNTL__DSPSemRespMask_MASK 0x1000 |
| #define ACP_DSP1_INTR_CNTL__DSPSemRespMask__SHIFT 0xc |
| #define ACP_DSP1_INTR_CNTL__I2SBTDataEmptyMask_MASK 0x2000 |
| #define ACP_DSP1_INTR_CNTL__I2SBTDataEmptyMask__SHIFT 0xd |
| #define ACP_DSP1_INTR_CNTL__DMAIOCMask_MASK 0xffff0000 |
| #define ACP_DSP1_INTR_CNTL__DMAIOCMask__SHIFT 0x10 |
| #define ACP_DSP1_INTR_STAT__ACPErrStat_MASK 0x1 |
| #define ACP_DSP1_INTR_STAT__ACPErrStat__SHIFT 0x0 |
| #define ACP_DSP1_INTR_STAT__ACPErrAck_MASK 0x1 |
| #define ACP_DSP1_INTR_STAT__ACPErrAck__SHIFT 0x0 |
| #define ACP_DSP1_INTR_STAT__I2SMicDataAvStat_MASK 0x2 |
| #define ACP_DSP1_INTR_STAT__I2SMicDataAvStat__SHIFT 0x1 |
| #define ACP_DSP1_INTR_STAT__I2SMicDataAvAck_MASK 0x2 |
| #define ACP_DSP1_INTR_STAT__I2SMicDataAvAck__SHIFT 0x1 |
| #define ACP_DSP1_INTR_STAT__I2SSpkr0DataEmptyStat_MASK 0x4 |
| #define ACP_DSP1_INTR_STAT__I2SSpkr0DataEmptyStat__SHIFT 0x2 |
| #define ACP_DSP1_INTR_STAT__I2SSpkr0DataEmptyAck_MASK 0x4 |
| #define ACP_DSP1_INTR_STAT__I2SSpkr0DataEmptyAck__SHIFT 0x2 |
| #define ACP_DSP1_INTR_STAT__I2SSpkr1DataEmptyStat_MASK 0x8 |
| #define ACP_DSP1_INTR_STAT__I2SSpkr1DataEmptyStat__SHIFT 0x3 |
| #define ACP_DSP1_INTR_STAT__I2SSpkr1DataEmptyAck_MASK 0x8 |
| #define ACP_DSP1_INTR_STAT__I2SSpkr1DataEmptyAck__SHIFT 0x3 |
| #define ACP_DSP1_INTR_STAT__I2SBTDataAvStat_MASK 0x10 |
| #define ACP_DSP1_INTR_STAT__I2SBTDataAvStat__SHIFT 0x4 |
| #define ACP_DSP1_INTR_STAT__I2SBTDataAvAck_MASK 0x10 |
| #define ACP_DSP1_INTR_STAT__I2SBTDataAvAck__SHIFT 0x4 |
| #define ACP_DSP1_INTR_STAT__AzaliaIntrStat_MASK 0x40 |
| #define ACP_DSP1_INTR_STAT__AzaliaIntrStat__SHIFT 0x6 |
| #define ACP_DSP1_INTR_STAT__AzaliaIntrAck_MASK 0x40 |
| #define ACP_DSP1_INTR_STAT__AzaliaIntrAck__SHIFT 0x6 |
| #define ACP_DSP1_INTR_STAT__SMUMailboxWriteStat_MASK 0x100 |
| #define ACP_DSP1_INTR_STAT__SMUMailboxWriteStat__SHIFT 0x8 |
| #define ACP_DSP1_INTR_STAT__SMUMailboxWriteAck_MASK 0x100 |
| #define ACP_DSP1_INTR_STAT__SMUMailboxWriteAck__SHIFT 0x8 |
| #define ACP_DSP1_INTR_STAT__SMUStutterStatusStat_MASK 0x200 |
| #define ACP_DSP1_INTR_STAT__SMUStutterStatusStat__SHIFT 0x9 |
| #define ACP_DSP1_INTR_STAT__SMUStutterStatusAck_MASK 0x200 |
| #define ACP_DSP1_INTR_STAT__SMUStutterStatusAck__SHIFT 0x9 |
| #define ACP_DSP1_INTR_STAT__MCStutterStatusStat_MASK 0x400 |
| #define ACP_DSP1_INTR_STAT__MCStutterStatusStat__SHIFT 0xa |
| #define ACP_DSP1_INTR_STAT__MCStutterStatusAck_MASK 0x400 |
| #define ACP_DSP1_INTR_STAT__MCStutterStatusAck__SHIFT 0xa |
| #define ACP_DSP1_INTR_STAT__DSPExtTimerStat_MASK 0x800 |
| #define ACP_DSP1_INTR_STAT__DSPExtTimerStat__SHIFT 0xb |
| #define ACP_DSP1_INTR_STAT__DSPExtTimerAck_MASK 0x800 |
| #define ACP_DSP1_INTR_STAT__DSPExtTimerAck__SHIFT 0xb |
| #define ACP_DSP1_INTR_STAT__DSPSemRespStat_MASK 0x1000 |
| #define ACP_DSP1_INTR_STAT__DSPSemRespStat__SHIFT 0xc |
| #define ACP_DSP1_INTR_STAT__DSPSemRespAck_MASK 0x1000 |
| #define ACP_DSP1_INTR_STAT__DSPSemRespAck__SHIFT 0xc |
| #define ACP_DSP1_INTR_STAT__I2SBTDataEmptyStat_MASK 0x2000 |
| #define ACP_DSP1_INTR_STAT__I2SBTDataEmptyStat__SHIFT 0xd |
| #define ACP_DSP1_INTR_STAT__I2SBTDataEmptyAck_MASK 0x2000 |
| #define ACP_DSP1_INTR_STAT__I2SBTDataEmptyAck__SHIFT 0xd |
| #define ACP_DSP1_INTR_STAT__DMAIOCStat_MASK 0xffff0000 |
| #define ACP_DSP1_INTR_STAT__DMAIOCStat__SHIFT 0x10 |
| #define ACP_DSP1_INTR_STAT__DMAIOCAck_MASK 0xffff0000 |
| #define ACP_DSP1_INTR_STAT__DMAIOCAck__SHIFT 0x10 |
| #define ACP_DSP1_TIMEOUT_CNTL__DSP1TimeoutValue_MASK 0x3ffff |
| #define ACP_DSP1_TIMEOUT_CNTL__DSP1TimeoutValue__SHIFT 0x0 |
| #define ACP_DSP1_TIMEOUT_CNTL__CntEn_MASK 0x80000000 |
| #define ACP_DSP1_TIMEOUT_CNTL__CntEn__SHIFT 0x1f |
| #define ACP_DSP2_INTR_CNTL__ACPErrMask_MASK 0x1 |
| #define ACP_DSP2_INTR_CNTL__ACPErrMask__SHIFT 0x0 |
| #define ACP_DSP2_INTR_CNTL__I2SMicDataAvMask_MASK 0x2 |
| #define ACP_DSP2_INTR_CNTL__I2SMicDataAvMask__SHIFT 0x1 |
| #define ACP_DSP2_INTR_CNTL__I2SSpkr0DataEmptyMask_MASK 0x4 |
| #define ACP_DSP2_INTR_CNTL__I2SSpkr0DataEmptyMask__SHIFT 0x2 |
| #define ACP_DSP2_INTR_CNTL__I2SSpkr1DataEmptyMask_MASK 0x8 |
| #define ACP_DSP2_INTR_CNTL__I2SSpkr1DataEmptyMask__SHIFT 0x3 |
| #define ACP_DSP2_INTR_CNTL__I2SBTDataAvMask_MASK 0x10 |
| #define ACP_DSP2_INTR_CNTL__I2SBTDataAvMask__SHIFT 0x4 |
| #define ACP_DSP2_INTR_CNTL__AzaliaIntrMask_MASK 0x40 |
| #define ACP_DSP2_INTR_CNTL__AzaliaIntrMask__SHIFT 0x6 |
| #define ACP_DSP2_INTR_CNTL__SMUMailboxWriteMask_MASK 0x100 |
| #define ACP_DSP2_INTR_CNTL__SMUMailboxWriteMask__SHIFT 0x8 |
| #define ACP_DSP2_INTR_CNTL__SMUStutterStatusMask_MASK 0x200 |
| #define ACP_DSP2_INTR_CNTL__SMUStutterStatusMask__SHIFT 0x9 |
| #define ACP_DSP2_INTR_CNTL__MCStutterStatusMask_MASK 0x400 |
| #define ACP_DSP2_INTR_CNTL__MCStutterStatusMask__SHIFT 0xa |
| #define ACP_DSP2_INTR_CNTL__DSPExtTimerMask_MASK 0x800 |
| #define ACP_DSP2_INTR_CNTL__DSPExtTimerMask__SHIFT 0xb |
| #define ACP_DSP2_INTR_CNTL__DSPSemRespMask_MASK 0x1000 |
| #define ACP_DSP2_INTR_CNTL__DSPSemRespMask__SHIFT 0xc |
| #define ACP_DSP2_INTR_CNTL__I2SBTDataEmptyMask_MASK 0x2000 |
| #define ACP_DSP2_INTR_CNTL__I2SBTDataEmptyMask__SHIFT 0xd |
| #define ACP_DSP2_INTR_CNTL__DMAIOCMask_MASK 0xffff0000 |
| #define ACP_DSP2_INTR_CNTL__DMAIOCMask__SHIFT 0x10 |
| #define ACP_DSP2_INTR_STAT__ACPErrStat_MASK 0x1 |
| #define ACP_DSP2_INTR_STAT__ACPErrStat__SHIFT 0x0 |
| #define ACP_DSP2_INTR_STAT__ACPErrAck_MASK 0x1 |
| #define ACP_DSP2_INTR_STAT__ACPErrAck__SHIFT 0x0 |
| #define ACP_DSP2_INTR_STAT__I2SMicDataAvStat_MASK 0x2 |
| #define ACP_DSP2_INTR_STAT__I2SMicDataAvStat__SHIFT 0x1 |
| #define ACP_DSP2_INTR_STAT__I2SMicDataAvAck_MASK 0x2 |
| #define ACP_DSP2_INTR_STAT__I2SMicDataAvAck__SHIFT 0x1 |
| #define ACP_DSP2_INTR_STAT__I2SSpkr0DataEmptyStat_MASK 0x4 |
| #define ACP_DSP2_INTR_STAT__I2SSpkr0DataEmptyStat__SHIFT 0x2 |
| #define ACP_DSP2_INTR_STAT__I2SSpkr0DataEmptyAck_MASK 0x4 |
| #define ACP_DSP2_INTR_STAT__I2SSpkr0DataEmptyAck__SHIFT 0x2 |
| #define ACP_DSP2_INTR_STAT__I2SSpkr1DataEmptyStat_MASK 0x8 |
| #define ACP_DSP2_INTR_STAT__I2SSpkr1DataEmptyStat__SHIFT 0x3 |
| #define ACP_DSP2_INTR_STAT__I2SSpkr1DataEmptyAck_MASK 0x8 |
| #define ACP_DSP2_INTR_STAT__I2SSpkr1DataEmptyAck__SHIFT 0x3 |
| #define ACP_DSP2_INTR_STAT__I2SBTDataAvStat_MASK 0x10 |
| #define ACP_DSP2_INTR_STAT__I2SBTDataAvStat__SHIFT 0x4 |
| #define ACP_DSP2_INTR_STAT__I2SBTDataAvAck_MASK 0x10 |
| #define ACP_DSP2_INTR_STAT__I2SBTDataAvAck__SHIFT 0x4 |
| #define ACP_DSP2_INTR_STAT__AzaliaIntrStat_MASK 0x40 |
| #define ACP_DSP2_INTR_STAT__AzaliaIntrStat__SHIFT 0x6 |
| #define ACP_DSP2_INTR_STAT__AzaliaIntrAck_MASK 0x40 |
| #define ACP_DSP2_INTR_STAT__AzaliaIntrAck__SHIFT 0x6 |
| #define ACP_DSP2_INTR_STAT__SMUMailboxWriteStat_MASK 0x100 |
| #define ACP_DSP2_INTR_STAT__SMUMailboxWriteStat__SHIFT 0x8 |
| #define ACP_DSP2_INTR_STAT__SMUMailboxWriteAck_MASK 0x100 |
| #define ACP_DSP2_INTR_STAT__SMUMailboxWriteAck__SHIFT 0x8 |
| #define ACP_DSP2_INTR_STAT__SMUStutterStatusStat_MASK 0x200 |
| #define ACP_DSP2_INTR_STAT__SMUStutterStatusStat__SHIFT 0x9 |
| #define ACP_DSP2_INTR_STAT__SMUStutterStatusAck_MASK 0x200 |
| #define ACP_DSP2_INTR_STAT__SMUStutterStatusAck__SHIFT 0x9 |
| #define ACP_DSP2_INTR_STAT__MCStutterStatusStat_MASK 0x400 |
| #define ACP_DSP2_INTR_STAT__MCStutterStatusStat__SHIFT 0xa |
| #define ACP_DSP2_INTR_STAT__MCStutterStatusAck_MASK 0x400 |
| #define ACP_DSP2_INTR_STAT__MCStutterStatusAck__SHIFT 0xa |
| #define ACP_DSP2_INTR_STAT__DSPExtTimerStat_MASK 0x800 |
| #define ACP_DSP2_INTR_STAT__DSPExtTimerStat__SHIFT 0xb |
| #define ACP_DSP2_INTR_STAT__DSPExtTimerAck_MASK 0x800 |
| #define ACP_DSP2_INTR_STAT__DSPExtTimerAck__SHIFT 0xb |
| #define ACP_DSP2_INTR_STAT__DSPSemRespStat_MASK 0x1000 |
| #define ACP_DSP2_INTR_STAT__DSPSemRespStat__SHIFT 0xc |
| #define ACP_DSP2_INTR_STAT__DSPSemRespAck_MASK 0x1000 |
| #define ACP_DSP2_INTR_STAT__DSPSemRespAck__SHIFT 0xc |
| #define ACP_DSP2_INTR_STAT__I2SBTDataEmptyStat_MASK 0x2000 |
| #define ACP_DSP2_INTR_STAT__I2SBTDataEmptyStat__SHIFT 0xd |
| #define ACP_DSP2_INTR_STAT__I2SBTDataEmptyAck_MASK 0x2000 |
| #define ACP_DSP2_INTR_STAT__I2SBTDataEmptyAck__SHIFT 0xd |
| #define ACP_DSP2_INTR_STAT__DMAIOCStat_MASK 0xffff0000 |
| #define ACP_DSP2_INTR_STAT__DMAIOCStat__SHIFT 0x10 |
| #define ACP_DSP2_INTR_STAT__DMAIOCAck_MASK 0xffff0000 |
| #define ACP_DSP2_INTR_STAT__DMAIOCAck__SHIFT 0x10 |
| #define ACP_DSP2_TIMEOUT_CNTL__DSP2TimeoutValue_MASK 0x3ffff |
| #define ACP_DSP2_TIMEOUT_CNTL__DSP2TimeoutValue__SHIFT 0x0 |
| #define ACP_DSP2_TIMEOUT_CNTL__CntEn_MASK 0x80000000 |
| #define ACP_DSP2_TIMEOUT_CNTL__CntEn__SHIFT 0x1f |
| #define ACP_DSP0_EXT_TIMER_CNTL__TimerCount_MASK 0xffffff |
| #define ACP_DSP0_EXT_TIMER_CNTL__TimerCount__SHIFT 0x0 |
| #define ACP_DSP0_EXT_TIMER_CNTL__TimerCntl_MASK 0xc0000000 |
| #define ACP_DSP0_EXT_TIMER_CNTL__TimerCntl__SHIFT 0x1e |
| #define ACP_DSP1_EXT_TIMER_CNTL__TimerCount_MASK 0xffffff |
| #define ACP_DSP1_EXT_TIMER_CNTL__TimerCount__SHIFT 0x0 |
| #define ACP_DSP1_EXT_TIMER_CNTL__TimerCntl_MASK 0xc0000000 |
| #define ACP_DSP1_EXT_TIMER_CNTL__TimerCntl__SHIFT 0x1e |
| #define ACP_DSP2_EXT_TIMER_CNTL__TimerCount_MASK 0xffffff |
| #define ACP_DSP2_EXT_TIMER_CNTL__TimerCount__SHIFT 0x0 |
| #define ACP_DSP2_EXT_TIMER_CNTL__TimerCntl_MASK 0xc0000000 |
| #define ACP_DSP2_EXT_TIMER_CNTL__TimerCntl__SHIFT 0x1e |
| #define ACP_AXI2DAGB_SEM_0__AXI2DAGBGblSemReg_MASK 0x1 |
| #define ACP_AXI2DAGB_SEM_0__AXI2DAGBGblSemReg__SHIFT 0x0 |
| #define ACP_AXI2DAGB_SEM_1__AXI2DAGBGblSemReg_MASK 0x1 |
| #define ACP_AXI2DAGB_SEM_1__AXI2DAGBGblSemReg__SHIFT 0x0 |
| #define ACP_AXI2DAGB_SEM_2__AXI2DAGBGblSemReg_MASK 0x1 |
| #define ACP_AXI2DAGB_SEM_2__AXI2DAGBGblSemReg__SHIFT 0x0 |
| #define ACP_AXI2DAGB_SEM_3__AXI2DAGBGblSemReg_MASK 0x1 |
| #define ACP_AXI2DAGB_SEM_3__AXI2DAGBGblSemReg__SHIFT 0x0 |
| #define ACP_AXI2DAGB_SEM_4__AXI2DAGBGblSemReg_MASK 0x1 |
| #define ACP_AXI2DAGB_SEM_4__AXI2DAGBGblSemReg__SHIFT 0x0 |
| #define ACP_AXI2DAGB_SEM_5__AXI2DAGBGblSemReg_MASK 0x1 |
| #define ACP_AXI2DAGB_SEM_5__AXI2DAGBGblSemReg__SHIFT 0x0 |
| #define ACP_AXI2DAGB_SEM_6__AXI2DAGBGblSemReg_MASK 0x1 |
| #define ACP_AXI2DAGB_SEM_6__AXI2DAGBGblSemReg__SHIFT 0x0 |
| #define ACP_AXI2DAGB_SEM_7__AXI2DAGBGblSemReg_MASK 0x1 |
| #define ACP_AXI2DAGB_SEM_7__AXI2DAGBGblSemReg__SHIFT 0x0 |
| #define ACP_AXI2DAGB_SEM_8__AXI2DAGBGblSemReg_MASK 0x1 |
| #define ACP_AXI2DAGB_SEM_8__AXI2DAGBGblSemReg__SHIFT 0x0 |
| #define ACP_AXI2DAGB_SEM_9__AXI2DAGBGblSemReg_MASK 0x1 |
| #define ACP_AXI2DAGB_SEM_9__AXI2DAGBGblSemReg__SHIFT 0x0 |
| #define ACP_AXI2DAGB_SEM_10__AXI2DAGBGblSemReg_MASK 0x1 |
| #define ACP_AXI2DAGB_SEM_10__AXI2DAGBGblSemReg__SHIFT 0x0 |
| #define ACP_AXI2DAGB_SEM_11__AXI2DAGBGblSemReg_MASK 0x1 |
| #define ACP_AXI2DAGB_SEM_11__AXI2DAGBGblSemReg__SHIFT 0x0 |
| #define ACP_AXI2DAGB_SEM_12__AXI2DAGBGblSemReg_MASK 0x1 |
| #define ACP_AXI2DAGB_SEM_12__AXI2DAGBGblSemReg__SHIFT 0x0 |
| #define ACP_AXI2DAGB_SEM_13__AXI2DAGBGblSemReg_MASK 0x1 |
| #define ACP_AXI2DAGB_SEM_13__AXI2DAGBGblSemReg__SHIFT 0x0 |
| #define ACP_AXI2DAGB_SEM_14__AXI2DAGBGblSemReg_MASK 0x1 |
| #define ACP_AXI2DAGB_SEM_14__AXI2DAGBGblSemReg__SHIFT 0x0 |
| #define ACP_AXI2DAGB_SEM_15__AXI2DAGBGblSemReg_MASK 0x1 |
| #define ACP_AXI2DAGB_SEM_15__AXI2DAGBGblSemReg__SHIFT 0x0 |
| #define ACP_AXI2DAGB_SEM_16__AXI2DAGBGblSemReg_MASK 0x1 |
| #define ACP_AXI2DAGB_SEM_16__AXI2DAGBGblSemReg__SHIFT 0x0 |
| #define ACP_AXI2DAGB_SEM_17__AXI2DAGBGblSemReg_MASK 0x1 |
| #define ACP_AXI2DAGB_SEM_17__AXI2DAGBGblSemReg__SHIFT 0x0 |
| #define ACP_AXI2DAGB_SEM_18__AXI2DAGBGblSemReg_MASK 0x1 |
| #define ACP_AXI2DAGB_SEM_18__AXI2DAGBGblSemReg__SHIFT 0x0 |
| #define ACP_AXI2DAGB_SEM_19__AXI2DAGBGblSemReg_MASK 0x1 |
| #define ACP_AXI2DAGB_SEM_19__AXI2DAGBGblSemReg__SHIFT 0x0 |
| #define ACP_AXI2DAGB_SEM_20__AXI2DAGBGblSemReg_MASK 0x1 |
| #define ACP_AXI2DAGB_SEM_20__AXI2DAGBGblSemReg__SHIFT 0x0 |
| #define ACP_AXI2DAGB_SEM_21__AXI2DAGBGblSemReg_MASK 0x1 |
| #define ACP_AXI2DAGB_SEM_21__AXI2DAGBGblSemReg__SHIFT 0x0 |
| #define ACP_AXI2DAGB_SEM_22__AXI2DAGBGblSemReg_MASK 0x1 |
| #define ACP_AXI2DAGB_SEM_22__AXI2DAGBGblSemReg__SHIFT 0x0 |
| #define ACP_AXI2DAGB_SEM_23__AXI2DAGBGblSemReg_MASK 0x1 |
| #define ACP_AXI2DAGB_SEM_23__AXI2DAGBGblSemReg__SHIFT 0x0 |
| #define ACP_AXI2DAGB_SEM_24__AXI2DAGBGblSemReg_MASK 0x1 |
| #define ACP_AXI2DAGB_SEM_24__AXI2DAGBGblSemReg__SHIFT 0x0 |
| #define ACP_AXI2DAGB_SEM_25__AXI2DAGBGblSemReg_MASK 0x1 |
| #define ACP_AXI2DAGB_SEM_25__AXI2DAGBGblSemReg__SHIFT 0x0 |
| #define ACP_AXI2DAGB_SEM_26__AXI2DAGBGblSemReg_MASK 0x1 |
| #define ACP_AXI2DAGB_SEM_26__AXI2DAGBGblSemReg__SHIFT 0x0 |
| #define ACP_AXI2DAGB_SEM_27__AXI2DAGBGblSemReg_MASK 0x1 |
| #define ACP_AXI2DAGB_SEM_27__AXI2DAGBGblSemReg__SHIFT 0x0 |
| #define ACP_AXI2DAGB_SEM_28__AXI2DAGBGblSemReg_MASK 0x1 |
| #define ACP_AXI2DAGB_SEM_28__AXI2DAGBGblSemReg__SHIFT 0x0 |
| #define ACP_AXI2DAGB_SEM_29__AXI2DAGBGblSemReg_MASK 0x1 |
| #define ACP_AXI2DAGB_SEM_29__AXI2DAGBGblSemReg__SHIFT 0x0 |
| #define ACP_AXI2DAGB_SEM_30__AXI2DAGBGblSemReg_MASK 0x1 |
| #define ACP_AXI2DAGB_SEM_30__AXI2DAGBGblSemReg__SHIFT 0x0 |
| #define ACP_AXI2DAGB_SEM_31__AXI2DAGBGblSemReg_MASK 0x1 |
| #define ACP_AXI2DAGB_SEM_31__AXI2DAGBGblSemReg__SHIFT 0x0 |
| #define ACP_AXI2DAGB_SEM_32__AXI2DAGBGblSemReg_MASK 0x1 |
| #define ACP_AXI2DAGB_SEM_32__AXI2DAGBGblSemReg__SHIFT 0x0 |
| #define ACP_AXI2DAGB_SEM_33__AXI2DAGBGblSemReg_MASK 0x1 |
| #define ACP_AXI2DAGB_SEM_33__AXI2DAGBGblSemReg__SHIFT 0x0 |
| #define ACP_AXI2DAGB_SEM_34__AXI2DAGBGblSemReg_MASK 0x1 |
| #define ACP_AXI2DAGB_SEM_34__AXI2DAGBGblSemReg__SHIFT 0x0 |
| #define ACP_AXI2DAGB_SEM_35__AXI2DAGBGblSemReg_MASK 0x1 |
| #define ACP_AXI2DAGB_SEM_35__AXI2DAGBGblSemReg__SHIFT 0x0 |
| #define ACP_AXI2DAGB_SEM_36__AXI2DAGBGblSemReg_MASK 0x1 |
| #define ACP_AXI2DAGB_SEM_36__AXI2DAGBGblSemReg__SHIFT 0x0 |
| #define ACP_AXI2DAGB_SEM_37__AXI2DAGBGblSemReg_MASK 0x1 |
| #define ACP_AXI2DAGB_SEM_37__AXI2DAGBGblSemReg__SHIFT 0x0 |
| #define ACP_AXI2DAGB_SEM_38__AXI2DAGBGblSemReg_MASK 0x1 |
| #define ACP_AXI2DAGB_SEM_38__AXI2DAGBGblSemReg__SHIFT 0x0 |
| #define ACP_AXI2DAGB_SEM_39__AXI2DAGBGblSemReg_MASK 0x1 |
| #define ACP_AXI2DAGB_SEM_39__AXI2DAGBGblSemReg__SHIFT 0x0 |
| #define ACP_AXI2DAGB_SEM_40__AXI2DAGBGblSemReg_MASK 0x1 |
| #define ACP_AXI2DAGB_SEM_40__AXI2DAGBGblSemReg__SHIFT 0x0 |
| #define ACP_AXI2DAGB_SEM_41__AXI2DAGBGblSemReg_MASK 0x1 |
| #define ACP_AXI2DAGB_SEM_41__AXI2DAGBGblSemReg__SHIFT 0x0 |
| #define ACP_AXI2DAGB_SEM_42__AXI2DAGBGblSemReg_MASK 0x1 |
| #define ACP_AXI2DAGB_SEM_42__AXI2DAGBGblSemReg__SHIFT 0x0 |
| #define ACP_AXI2DAGB_SEM_43__AXI2DAGBGblSemReg_MASK 0x1 |
| #define ACP_AXI2DAGB_SEM_43__AXI2DAGBGblSemReg__SHIFT 0x0 |
| #define ACP_AXI2DAGB_SEM_44__AXI2DAGBGblSemReg_MASK 0x1 |
| #define ACP_AXI2DAGB_SEM_44__AXI2DAGBGblSemReg__SHIFT 0x0 |
| #define ACP_AXI2DAGB_SEM_45__AXI2DAGBGblSemReg_MASK 0x1 |
| #define ACP_AXI2DAGB_SEM_45__AXI2DAGBGblSemReg__SHIFT 0x0 |
| #define ACP_AXI2DAGB_SEM_46__AXI2DAGBGblSemReg_MASK 0x1 |
| #define ACP_AXI2DAGB_SEM_46__AXI2DAGBGblSemReg__SHIFT 0x0 |
| #define ACP_AXI2DAGB_SEM_47__AXI2DAGBGblSemReg_MASK 0x1 |
| #define ACP_AXI2DAGB_SEM_47__AXI2DAGBGblSemReg__SHIFT 0x0 |
| #define ACP_SRBM_Client_Base_Addr__SRBM_Client_base_addr_MASK 0xff |
| #define ACP_SRBM_Client_Base_Addr__SRBM_Client_base_addr__SHIFT 0x0 |
| #define ACP_SRBM_Client_RDDATA__ReadData_MASK 0xffffffff |
| #define ACP_SRBM_Client_RDDATA__ReadData__SHIFT 0x0 |
| #define ACP_SRBM_Cycle_Sts__SRBM_Client_Sts_MASK 0x1 |
| #define ACP_SRBM_Cycle_Sts__SRBM_Client_Sts__SHIFT 0x0 |
| #define ACP_SRBM_Targ_Idx_Addr__SRBM_Targ_Idx_addr_MASK 0x7ffffff |
| #define ACP_SRBM_Targ_Idx_Addr__SRBM_Targ_Idx_addr__SHIFT 0x0 |
| #define ACP_SRBM_Targ_Idx_Data__SRBM_Targ_Idx_Data_MASK 0xffffffff |
| #define ACP_SRBM_Targ_Idx_Data__SRBM_Targ_Idx_Data__SHIFT 0x0 |
| #define ACP_SEMA_ADDR_LOW__ADDR_9_3_MASK 0x7f |
| #define ACP_SEMA_ADDR_LOW__ADDR_9_3__SHIFT 0x0 |
| #define ACP_SEMA_ADDR_HIGH__ADDR_39_10_MASK 0x3fffffff |
| #define ACP_SEMA_ADDR_HIGH__ADDR_39_10__SHIFT 0x0 |
| #define ACP_SEMA_CMD__REQ_CMD_MASK 0xf |
| #define ACP_SEMA_CMD__REQ_CMD__SHIFT 0x0 |
| #define ACP_SEMA_CMD__WR_PHASE_MASK 0x30 |
| #define ACP_SEMA_CMD__WR_PHASE__SHIFT 0x4 |
| #define ACP_SEMA_CMD__VMID_EN_MASK 0x80 |
| #define ACP_SEMA_CMD__VMID_EN__SHIFT 0x7 |
| #define ACP_SEMA_CMD__VMID_MASK 0xf00 |
| #define ACP_SEMA_CMD__VMID__SHIFT 0x8 |
| #define ACP_SEMA_CMD__ATC_MASK 0x1000 |
| #define ACP_SEMA_CMD__ATC__SHIFT 0xc |
| #define ACP_SEMA_STS__REQ_STS_MASK 0x3 |
| #define ACP_SEMA_STS__REQ_STS__SHIFT 0x0 |
| #define ACP_SEMA_STS__REQ_RESP_AVAIL_MASK 0x100 |
| #define ACP_SEMA_STS__REQ_RESP_AVAIL__SHIFT 0x8 |
| #define ACP_SEMA_REQ__ISSUE_POLL_REQ_MASK 0x1 |
| #define ACP_SEMA_REQ__ISSUE_POLL_REQ__SHIFT 0x0 |
| #define ACP_FW_STATUS__RUN_MASK 0x1 |
| #define ACP_FW_STATUS__RUN__SHIFT 0x0 |
| #define ACP_FUTURE_REG_ACLK_0__ACPFutureReg_MASK 0xffffffff |
| #define ACP_FUTURE_REG_ACLK_0__ACPFutureReg__SHIFT 0x0 |
| #define ACP_FUTURE_REG_ACLK_1__ACPFutureReg_MASK 0xffffffff |
| #define ACP_FUTURE_REG_ACLK_1__ACPFutureReg__SHIFT 0x0 |
| #define ACP_FUTURE_REG_ACLK_2__ACPFutureReg_MASK 0xffffffff |
| #define ACP_FUTURE_REG_ACLK_2__ACPFutureReg__SHIFT 0x0 |
| #define ACP_FUTURE_REG_ACLK_3__ACPFutureReg_MASK 0xffffffff |
| #define ACP_FUTURE_REG_ACLK_3__ACPFutureReg__SHIFT 0x0 |
| #define ACP_FUTURE_REG_ACLK_4__ACPFutureReg_MASK 0xffffffff |
| #define ACP_FUTURE_REG_ACLK_4__ACPFutureReg__SHIFT 0x0 |
| #define ACP_TIMER__ACP_Timer_count_MASK 0xffffffff |
| #define ACP_TIMER__ACP_Timer_count__SHIFT 0x0 |
| #define ACP_TIMER_CNTL__ACP_Timer_control_MASK 0x1 |
| #define ACP_TIMER_CNTL__ACP_Timer_control__SHIFT 0x0 |
| #define ACP_DSP0_TIMER__ACP_DSP0_timer_MASK 0xffffff |
| #define ACP_DSP0_TIMER__ACP_DSP0_timer__SHIFT 0x0 |
| #define ACP_DSP1_TIMER__ACP_DSP1_timer_MASK 0xffffff |
| #define ACP_DSP1_TIMER__ACP_DSP1_timer__SHIFT 0x0 |
| #define ACP_DSP2_TIMER__ACP_DSP2_timer_MASK 0xffffff |
| #define ACP_DSP2_TIMER__ACP_DSP2_timer__SHIFT 0x0 |
| #define ACP_I2S_TRANSMIT_BYTE_CNT_HIGH__i2s_sp_tx_byte_cnt_high_MASK 0xffffffff |
| #define ACP_I2S_TRANSMIT_BYTE_CNT_HIGH__i2s_sp_tx_byte_cnt_high__SHIFT 0x0 |
| #define ACP_I2S_TRANSMIT_BYTE_CNT_LOW__i2s_sp_tx_byte_cnt_low_MASK 0xffffffff |
| #define ACP_I2S_TRANSMIT_BYTE_CNT_LOW__i2s_sp_tx_byte_cnt_low__SHIFT 0x0 |
| #define ACP_I2S_BT_TRANSMIT_BYTE_CNT_HIGH__i2s_bt_tx_byte_cnt_high_MASK 0xffffffff |
| #define ACP_I2S_BT_TRANSMIT_BYTE_CNT_HIGH__i2s_bt_tx_byte_cnt_high__SHIFT 0x0 |
| #define ACP_I2S_BT_TRANSMIT_BYTE_CNT_LOW__i2s_bt_tx_byte_cnt_low_MASK 0xffffffff |
| #define ACP_I2S_BT_TRANSMIT_BYTE_CNT_LOW__i2s_bt_tx_byte_cnt_low__SHIFT 0x0 |
| #define ACP_I2S_BT_RECEIVE_BYTE_CNT_HIGH__i2s_bt_rx_byte_cnt_high_MASK 0xffffffff |
| #define ACP_I2S_BT_RECEIVE_BYTE_CNT_HIGH__i2s_bt_rx_byte_cnt_high__SHIFT 0x0 |
| #define ACP_I2S_BT_RECEIVE_BYTE_CNT_LOW__i2s_bt_rx_byte_cnt_low_MASK 0xffffffff |
| #define ACP_I2S_BT_RECEIVE_BYTE_CNT_LOW__i2s_bt_rx_byte_cnt_low__SHIFT 0x0 |
| #define ACP_DSP0_CS_STATE__DSP0_CS_state_MASK 0x1 |
| #define ACP_DSP0_CS_STATE__DSP0_CS_state__SHIFT 0x0 |
| #define ACP_DSP1_CS_STATE__DSP1_CS_state_MASK 0x1 |
| #define ACP_DSP1_CS_STATE__DSP1_CS_state__SHIFT 0x0 |
| #define ACP_DSP2_CS_STATE__DSP2_CS_state_MASK 0x1 |
| #define ACP_DSP2_CS_STATE__DSP2_CS_state__SHIFT 0x0 |
| #define ACP_SCRATCH_REG_BASE_ADDR__SCRATCH_REG_BASE_ADDR_MASK 0x7ffff |
| #define ACP_SCRATCH_REG_BASE_ADDR__SCRATCH_REG_BASE_ADDR__SHIFT 0x0 |
| #define CC_ACP_EFUSE__DSP0_DISABLE_MASK 0x2 |
| #define CC_ACP_EFUSE__DSP0_DISABLE__SHIFT 0x1 |
| #define CC_ACP_EFUSE__DSP1_DISABLE_MASK 0x4 |
| #define CC_ACP_EFUSE__DSP1_DISABLE__SHIFT 0x2 |
| #define CC_ACP_EFUSE__DSP2_DISABLE_MASK 0x8 |
| #define CC_ACP_EFUSE__DSP2_DISABLE__SHIFT 0x3 |
| #define CC_ACP_EFUSE__ACP_DISABLE_MASK 0x10 |
| #define CC_ACP_EFUSE__ACP_DISABLE__SHIFT 0x4 |
| #define ACP_PGFSM_RETAIN_REG__ACP_P1_ON_OFF_MASK 0x1 |
| #define ACP_PGFSM_RETAIN_REG__ACP_P1_ON_OFF__SHIFT 0x0 |
| #define ACP_PGFSM_RETAIN_REG__ACP_P2_ON_OFF_MASK 0x2 |
| #define ACP_PGFSM_RETAIN_REG__ACP_P2_ON_OFF__SHIFT 0x1 |
| #define ACP_PGFSM_RETAIN_REG__ACP_DSP0_ON_OFF_MASK 0x4 |
| #define ACP_PGFSM_RETAIN_REG__ACP_DSP0_ON_OFF__SHIFT 0x2 |
| #define ACP_PGFSM_RETAIN_REG__ACP_DSP1_ON_OFF_MASK 0x8 |
| #define ACP_PGFSM_RETAIN_REG__ACP_DSP1_ON_OFF__SHIFT 0x3 |
| #define ACP_PGFSM_RETAIN_REG__ACP_DSP2_ON_OFF_MASK 0x10 |
| #define ACP_PGFSM_RETAIN_REG__ACP_DSP2_ON_OFF__SHIFT 0x4 |
| #define ACP_PGFSM_RETAIN_REG__ACP_AZ_ON_OFF_MASK 0x20 |
| #define ACP_PGFSM_RETAIN_REG__ACP_AZ_ON_OFF__SHIFT 0x5 |
| #define ACP_PGFSM_CONFIG_REG__FSM_ADDR_MASK 0xff |
| #define ACP_PGFSM_CONFIG_REG__FSM_ADDR__SHIFT 0x0 |
| #define ACP_PGFSM_CONFIG_REG__Power_Down_MASK 0x100 |
| #define ACP_PGFSM_CONFIG_REG__Power_Down__SHIFT 0x8 |
| #define ACP_PGFSM_CONFIG_REG__Power_Up_MASK 0x200 |
| #define ACP_PGFSM_CONFIG_REG__Power_Up__SHIFT 0x9 |
| #define ACP_PGFSM_CONFIG_REG__P1_Select_MASK 0x400 |
| #define ACP_PGFSM_CONFIG_REG__P1_Select__SHIFT 0xa |
| #define ACP_PGFSM_CONFIG_REG__P2_Select_MASK 0x800 |
| #define ACP_PGFSM_CONFIG_REG__P2_Select__SHIFT 0xb |
| #define ACP_PGFSM_CONFIG_REG__Wr_MASK 0x1000 |
| #define ACP_PGFSM_CONFIG_REG__Wr__SHIFT 0xc |
| #define ACP_PGFSM_CONFIG_REG__Rd_MASK 0x2000 |
| #define ACP_PGFSM_CONFIG_REG__Rd__SHIFT 0xd |
| #define ACP_PGFSM_CONFIG_REG__RdData_Reset_MASK 0x4000 |
| #define ACP_PGFSM_CONFIG_REG__RdData_Reset__SHIFT 0xe |
| #define ACP_PGFSM_CONFIG_REG__Short_Format_MASK 0x8000 |
| #define ACP_PGFSM_CONFIG_REG__Short_Format__SHIFT 0xf |
| #define ACP_PGFSM_CONFIG_REG__BPM_CG_MG_FGCG_MASK 0x3ff0000 |
| #define ACP_PGFSM_CONFIG_REG__BPM_CG_MG_FGCG__SHIFT 0x10 |
| #define ACP_PGFSM_CONFIG_REG__SRBM_override_MASK 0x4000000 |
| #define ACP_PGFSM_CONFIG_REG__SRBM_override__SHIFT 0x1a |
| #define ACP_PGFSM_CONFIG_REG__Rsvd_BPM_Addr_MASK 0x8000000 |
| #define ACP_PGFSM_CONFIG_REG__Rsvd_BPM_Addr__SHIFT 0x1b |
| #define ACP_PGFSM_CONFIG_REG__REG_ADDR_MASK 0xf0000000 |
| #define ACP_PGFSM_CONFIG_REG__REG_ADDR__SHIFT 0x1c |
| #define ACP_PGFSM_WRITE_REG__Write_value_MASK 0xffffffff |
| #define ACP_PGFSM_WRITE_REG__Write_value__SHIFT 0x0 |
| #define ACP_PGFSM_READ_REG_0__Read_value_MASK 0xffffff |
| #define ACP_PGFSM_READ_REG_0__Read_value__SHIFT 0x0 |
| #define ACP_PGFSM_READ_REG_1__Read_value_MASK 0xffffff |
| #define ACP_PGFSM_READ_REG_1__Read_value__SHIFT 0x0 |
| #define ACP_PGFSM_READ_REG_2__Read_value_MASK 0xffffff |
| #define ACP_PGFSM_READ_REG_2__Read_value__SHIFT 0x0 |
| #define ACP_PGFSM_READ_REG_3__Read_value_MASK 0xffffff |
| #define ACP_PGFSM_READ_REG_3__Read_value__SHIFT 0x0 |
| #define ACP_PGFSM_READ_REG_4__Read_value_MASK 0xffffff |
| #define ACP_PGFSM_READ_REG_4__Read_value__SHIFT 0x0 |
| #define ACP_PGFSM_READ_REG_5__Read_value_MASK 0xffffff |
| #define ACP_PGFSM_READ_REG_5__Read_value__SHIFT 0x0 |
| #define ACP_IP_PGFSM_ENABLE__ACP_IP_ACCESS_MASK 0x1 |
| #define ACP_IP_PGFSM_ENABLE__ACP_IP_ACCESS__SHIFT 0x0 |
| #define ACP_I2S_PIN_CONFIG__ACP_I2S_PIN_CONFIG_MASK 0x3 |
| #define ACP_I2S_PIN_CONFIG__ACP_I2S_PIN_CONFIG__SHIFT 0x0 |
| #define ACP_AZALIA_I2S_SELECT__AZ_I2S_SELECT_MASK 0x1 |
| #define ACP_AZALIA_I2S_SELECT__AZ_I2S_SELECT__SHIFT 0x0 |
| #define ACP_CHIP_PKG_FOR_PAD_ISOLATION__external_fch_package_MASK 0x1 |
| #define ACP_CHIP_PKG_FOR_PAD_ISOLATION__external_fch_package__SHIFT 0x0 |
| #define ACP_AUDIO_PAD_PULLUP_PULLDOWN_CTRL__ACP_AUDIO_PAD_pullup_disable_MASK 0x7ff |
| #define ACP_AUDIO_PAD_PULLUP_PULLDOWN_CTRL__ACP_AUDIO_PAD_pullup_disable__SHIFT 0x0 |
| #define ACP_AUDIO_PAD_PULLUP_PULLDOWN_CTRL__ACP_AUDIO_PAD_pulldown_enable_MASK 0x7ff0000 |
| #define ACP_AUDIO_PAD_PULLUP_PULLDOWN_CTRL__ACP_AUDIO_PAD_pulldown_enable__SHIFT 0x10 |
| #define ACP_BT_UART_PAD_SEL__ACP_BT_UART_PAD_SEL_MASK 0x1 |
| #define ACP_BT_UART_PAD_SEL__ACP_BT_UART_PAD_SEL__SHIFT 0x0 |
| #define ACP_SCRATCH_REG_0__ACP_SCRATCH_REG_MASK 0xffffffff |
| #define ACP_SCRATCH_REG_0__ACP_SCRATCH_REG__SHIFT 0x0 |
| #define ACP_SCRATCH_REG_1__ACP_SCRATCH_REG_MASK 0xffffffff |
| #define ACP_SCRATCH_REG_1__ACP_SCRATCH_REG__SHIFT 0x0 |
| #define ACP_SCRATCH_REG_2__ACP_SCRATCH_REG_MASK 0xffffffff |
| #define ACP_SCRATCH_REG_2__ACP_SCRATCH_REG__SHIFT 0x0 |
| #define ACP_SCRATCH_REG_3__ACP_SCRATCH_REG_MASK 0xffffffff |
| #define ACP_SCRATCH_REG_3__ACP_SCRATCH_REG__SHIFT 0x0 |
| #define ACP_SCRATCH_REG_4__ACP_SCRATCH_REG_MASK 0xffffffff |
| #define ACP_SCRATCH_REG_4__ACP_SCRATCH_REG__SHIFT 0x0 |
| #define ACP_SCRATCH_REG_5__ACP_SCRATCH_REG_MASK 0xffffffff |
| #define ACP_SCRATCH_REG_5__ACP_SCRATCH_REG__SHIFT 0x0 |
| #define ACP_SCRATCH_REG_6__ACP_SCRATCH_REG_MASK 0xffffffff |
| #define ACP_SCRATCH_REG_6__ACP_SCRATCH_REG__SHIFT 0x0 |
| #define ACP_SCRATCH_REG_7__ACP_SCRATCH_REG_MASK 0xffffffff |
| #define ACP_SCRATCH_REG_7__ACP_SCRATCH_REG__SHIFT 0x0 |
| #define ACP_SCRATCH_REG_8__ACP_SCRATCH_REG_MASK 0xffffffff |
| #define ACP_SCRATCH_REG_8__ACP_SCRATCH_REG__SHIFT 0x0 |
| #define ACP_SCRATCH_REG_9__ACP_SCRATCH_REG_MASK 0xffffffff |
| #define ACP_SCRATCH_REG_9__ACP_SCRATCH_REG__SHIFT 0x0 |
| #define ACP_SCRATCH_REG_10__ACP_SCRATCH_REG_MASK 0xffffffff |
| #define ACP_SCRATCH_REG_10__ACP_SCRATCH_REG__SHIFT 0x0 |
| #define ACP_SCRATCH_REG_11__ACP_SCRATCH_REG_MASK 0xffffffff |
| #define ACP_SCRATCH_REG_11__ACP_SCRATCH_REG__SHIFT 0x0 |
| #define ACP_SCRATCH_REG_12__ACP_SCRATCH_REG_MASK 0xffffffff |
| #define ACP_SCRATCH_REG_12__ACP_SCRATCH_REG__SHIFT 0x0 |
| #define ACP_SCRATCH_REG_13__ACP_SCRATCH_REG_MASK 0xffffffff |
| #define ACP_SCRATCH_REG_13__ACP_SCRATCH_REG__SHIFT 0x0 |
| #define ACP_SCRATCH_REG_14__ACP_SCRATCH_REG_MASK 0xffffffff |
| #define ACP_SCRATCH_REG_14__ACP_SCRATCH_REG__SHIFT 0x0 |
| #define ACP_SCRATCH_REG_15__ACP_SCRATCH_REG_MASK 0xffffffff |
| #define ACP_SCRATCH_REG_15__ACP_SCRATCH_REG__SHIFT 0x0 |
| #define ACP_SCRATCH_REG_16__ACP_SCRATCH_REG_MASK 0xffffffff |
| #define ACP_SCRATCH_REG_16__ACP_SCRATCH_REG__SHIFT 0x0 |
| #define ACP_SCRATCH_REG_17__ACP_SCRATCH_REG_MASK 0xffffffff |
| #define ACP_SCRATCH_REG_17__ACP_SCRATCH_REG__SHIFT 0x0 |
| #define ACP_SCRATCH_REG_18__ACP_SCRATCH_REG_MASK 0xffffffff |
| #define ACP_SCRATCH_REG_18__ACP_SCRATCH_REG__SHIFT 0x0 |
| #define ACP_SCRATCH_REG_19__ACP_SCRATCH_REG_MASK 0xffffffff |
| #define ACP_SCRATCH_REG_19__ACP_SCRATCH_REG__SHIFT 0x0 |
| #define ACP_SCRATCH_REG_20__ACP_SCRATCH_REG_MASK 0xffffffff |
| #define ACP_SCRATCH_REG_20__ACP_SCRATCH_REG__SHIFT 0x0 |
| #define ACP_SCRATCH_REG_21__ACP_SCRATCH_REG_MASK 0xffffffff |
| #define ACP_SCRATCH_REG_21__ACP_SCRATCH_REG__SHIFT 0x0 |
| #define ACP_SCRATCH_REG_22__ACP_SCRATCH_REG_MASK 0xffffffff |
| #define ACP_SCRATCH_REG_22__ACP_SCRATCH_REG__SHIFT 0x0 |
| #define ACP_SCRATCH_REG_23__ACP_SCRATCH_REG_MASK 0xffffffff |
| #define ACP_SCRATCH_REG_23__ACP_SCRATCH_REG__SHIFT 0x0 |
| #define ACP_SCRATCH_REG_24__ACP_SCRATCH_REG_MASK 0xffffffff |
| #define ACP_SCRATCH_REG_24__ACP_SCRATCH_REG__SHIFT 0x0 |
| #define ACP_SCRATCH_REG_25__ACP_SCRATCH_REG_MASK 0xffffffff |
| #define ACP_SCRATCH_REG_25__ACP_SCRATCH_REG__SHIFT 0x0 |
| #define ACP_SCRATCH_REG_26__ACP_SCRATCH_REG_MASK 0xffffffff |
| #define ACP_SCRATCH_REG_26__ACP_SCRATCH_REG__SHIFT 0x0 |
| #define ACP_SCRATCH_REG_27__ACP_SCRATCH_REG_MASK 0xffffffff |
| #define ACP_SCRATCH_REG_27__ACP_SCRATCH_REG__SHIFT 0x0 |
| #define ACP_SCRATCH_REG_28__ACP_SCRATCH_REG_MASK 0xffffffff |
| #define ACP_SCRATCH_REG_28__ACP_SCRATCH_REG__SHIFT 0x0 |
| #define ACP_SCRATCH_REG_29__ACP_SCRATCH_REG_MASK 0xffffffff |
| #define ACP_SCRATCH_REG_29__ACP_SCRATCH_REG__SHIFT 0x0 |
| #define ACP_SCRATCH_REG_30__ACP_SCRATCH_REG_MASK 0xffffffff |
| #define ACP_SCRATCH_REG_30__ACP_SCRATCH_REG__SHIFT 0x0 |
| #define ACP_SCRATCH_REG_31__ACP_SCRATCH_REG_MASK 0xffffffff |
| #define ACP_SCRATCH_REG_31__ACP_SCRATCH_REG__SHIFT 0x0 |
| #define ACP_SCRATCH_REG_32__ACP_SCRATCH_REG_MASK 0xffffffff |
| #define ACP_SCRATCH_REG_32__ACP_SCRATCH_REG__SHIFT 0x0 |
| #define ACP_SCRATCH_REG_33__ACP_SCRATCH_REG_MASK 0xffffffff |
| #define ACP_SCRATCH_REG_33__ACP_SCRATCH_REG__SHIFT 0x0 |
| #define ACP_SCRATCH_REG_34__ACP_SCRATCH_REG_MASK 0xffffffff |
| #define ACP_SCRATCH_REG_34__ACP_SCRATCH_REG__SHIFT 0x0 |
| #define ACP_SCRATCH_REG_35__ACP_SCRATCH_REG_MASK 0xffffffff |
| #define ACP_SCRATCH_REG_35__ACP_SCRATCH_REG__SHIFT 0x0 |
| #define ACP_SCRATCH_REG_36__ACP_SCRATCH_REG_MASK 0xffffffff |
| #define ACP_SCRATCH_REG_36__ACP_SCRATCH_REG__SHIFT 0x0 |
| #define ACP_SCRATCH_REG_37__ACP_SCRATCH_REG_MASK 0xffffffff |
| #define ACP_SCRATCH_REG_37__ACP_SCRATCH_REG__SHIFT 0x0 |
| #define ACP_SCRATCH_REG_38__ACP_SCRATCH_REG_MASK 0xffffffff |
| #define ACP_SCRATCH_REG_38__ACP_SCRATCH_REG__SHIFT 0x0 |
| #define ACP_SCRATCH_REG_39__ACP_SCRATCH_REG_MASK 0xffffffff |
| #define ACP_SCRATCH_REG_39__ACP_SCRATCH_REG__SHIFT 0x0 |
| #define ACP_SCRATCH_REG_40__ACP_SCRATCH_REG_MASK 0xffffffff |
| #define ACP_SCRATCH_REG_40__ACP_SCRATCH_REG__SHIFT 0x0 |
| #define ACP_SCRATCH_REG_41__ACP_SCRATCH_REG_MASK 0xffffffff |
| #define ACP_SCRATCH_REG_41__ACP_SCRATCH_REG__SHIFT 0x0 |
| #define ACP_SCRATCH_REG_42__ACP_SCRATCH_REG_MASK 0xffffffff |
| #define ACP_SCRATCH_REG_42__ACP_SCRATCH_REG__SHIFT 0x0 |
| #define ACP_SCRATCH_REG_43__ACP_SCRATCH_REG_MASK 0xffffffff |
| #define ACP_SCRATCH_REG_43__ACP_SCRATCH_REG__SHIFT 0x0 |
| #define ACP_SCRATCH_REG_44__ACP_SCRATCH_REG_MASK 0xffffffff |
| #define ACP_SCRATCH_REG_44__ACP_SCRATCH_REG__SHIFT 0x0 |
| #define ACP_SCRATCH_REG_45__ACP_SCRATCH_REG_MASK 0xffffffff |
| #define ACP_SCRATCH_REG_45__ACP_SCRATCH_REG__SHIFT 0x0 |
| #define ACP_SCRATCH_REG_46__ACP_SCRATCH_REG_MASK 0xffffffff |
| #define ACP_SCRATCH_REG_46__ACP_SCRATCH_REG__SHIFT 0x0 |
| #define ACP_SCRATCH_REG_47__ACP_SCRATCH_REG_MASK 0xffffffff |
| #define ACP_SCRATCH_REG_47__ACP_SCRATCH_REG__SHIFT 0x0 |
| #define ACP_VOICE_WAKEUP_ENABLE__voice_wakeup_enable_MASK 0x1 |
| #define ACP_VOICE_WAKEUP_ENABLE__voice_wakeup_enable__SHIFT 0x0 |
| #define ACP_VOICE_WAKEUP_STATUS__voice_wakeup_status_MASK 0x1 |
| #define ACP_VOICE_WAKEUP_STATUS__voice_wakeup_status__SHIFT 0x0 |
| #define I2S_VOICE_WAKEUP_LOWER_THRESHOLD__i2s_voice_wakeup_lower_threshold_MASK 0xffffffff |
| #define I2S_VOICE_WAKEUP_LOWER_THRESHOLD__i2s_voice_wakeup_lower_threshold__SHIFT 0x0 |
| #define I2S_VOICE_WAKEUP_HIGHER_THRESHOLD__i2s_voice_wakeup_higher_threshold_MASK 0xffffffff |
| #define I2S_VOICE_WAKEUP_HIGHER_THRESHOLD__i2s_voice_wakeup_higher_threshold__SHIFT 0x0 |
| #define I2S_VOICE_WAKEUP_NO_OF_SAMPLES__i2s_voice_wakeup_no_of_samples_MASK 0xffff |
| #define I2S_VOICE_WAKEUP_NO_OF_SAMPLES__i2s_voice_wakeup_no_of_samples__SHIFT 0x0 |
| #define I2S_VOICE_WAKEUP_NO_OF_PEAKS__i2s_voice_wakeup_no_of_peaks_MASK 0xffff |
| #define I2S_VOICE_WAKEUP_NO_OF_PEAKS__i2s_voice_wakeup_no_of_peaks__SHIFT 0x0 |
| #define I2S_VOICE_WAKEUP_DURATION_OF_N_PEAKS__i2s_voice_wakeup_duration_of_n_peaks_MASK 0xffffffff |
| #define I2S_VOICE_WAKEUP_DURATION_OF_N_PEAKS__i2s_voice_wakeup_duration_of_n_peaks__SHIFT 0x0 |
| #define I2S_VOICE_WAKEUP_BITCLK_TOGGLE_DETECTION__i2s_voice_wakeup_bitclk_toggle_wakeup_en_MASK 0x1 |
| #define I2S_VOICE_WAKEUP_BITCLK_TOGGLE_DETECTION__i2s_voice_wakeup_bitclk_toggle_wakeup_en__SHIFT 0x0 |
| #define I2S_VOICE_WAKEUP_DATA_PATH_SWITCH__i2s_voice_wakeup_data_path_switch_req_MASK 0x1 |
| #define I2S_VOICE_WAKEUP_DATA_PATH_SWITCH__i2s_voice_wakeup_data_path_switch_req__SHIFT 0x0 |
| #define I2S_VOICE_WAKEUP_DATA_PATH_SWITCH__i2s_voice_wakeup_data_path_switch_ack_MASK 0x2 |
| #define I2S_VOICE_WAKEUP_DATA_PATH_SWITCH__i2s_voice_wakeup_data_path_switch_ack__SHIFT 0x1 |
| #define I2S_VOICE_WAKEUP_DATA_POINTER__i2s_voice_wakeup_data_pointer_MASK 0xffffffff |
| #define I2S_VOICE_WAKEUP_DATA_POINTER__i2s_voice_wakeup_data_pointer__SHIFT 0x0 |
| #define I2S_VOICE_WAKEUP_AUTH_MATCH__i2s_voice_wakeup_authentication_valid_MASK 0x1 |
| #define I2S_VOICE_WAKEUP_AUTH_MATCH__i2s_voice_wakeup_authentication_valid__SHIFT 0x0 |
| #define I2S_VOICE_WAKEUP_AUTH_MATCH__i2s_voice_wakeup_authentication_match_MASK 0x2 |
| #define I2S_VOICE_WAKEUP_AUTH_MATCH__i2s_voice_wakeup_authentication_match__SHIFT 0x1 |
| #define I2S_VOICE_WAKEUP_8KB_WRAP__i2s_voice_wakeup_8kb_wrap_MASK 0x1 |
| #define I2S_VOICE_WAKEUP_8KB_WRAP__i2s_voice_wakeup_8kb_wrap__SHIFT 0x0 |
| #define ACP_I2S_RECEIVED_BYTE_CNT_HIGH__i2s_mic_rx_byte_cnt_high_MASK 0xffffffff |
| #define ACP_I2S_RECEIVED_BYTE_CNT_HIGH__i2s_mic_rx_byte_cnt_high__SHIFT 0x0 |
| #define ACP_I2S_RECEIVED_BYTE_CNT_LOW__i2s_mic_rx_byte_cnt_low_MASK 0xffffffff |
| #define ACP_I2S_RECEIVED_BYTE_CNT_LOW__i2s_mic_rx_byte_cnt_low__SHIFT 0x0 |
| #define ACP_I2S_MICSP_TRANSMIT_BYTE_CNT_HIGH__i2s_micsp_tx_byte_cnt_high_MASK 0xffffffff |
| #define ACP_I2S_MICSP_TRANSMIT_BYTE_CNT_HIGH__i2s_micsp_tx_byte_cnt_high__SHIFT 0x0 |
| #define ACP_I2S_MICSP_TRANSMIT_BYTE_CNT_LOW__i2s_micsp_tx_byte_cnt_low_MASK 0xffffffff |
| #define ACP_I2S_MICSP_TRANSMIT_BYTE_CNT_LOW__i2s_micsp_tx_byte_cnt_low__SHIFT 0x0 |
| #define ACP_MEM_SHUT_DOWN_REQ_LO__ACP_ShutDownReq_RAML_MASK 0xffffffff |
| #define ACP_MEM_SHUT_DOWN_REQ_LO__ACP_ShutDownReq_RAML__SHIFT 0x0 |
| #define ACP_MEM_SHUT_DOWN_REQ_HI__ACP_ShutDownReq_RAMH_MASK 0xffff |
| #define ACP_MEM_SHUT_DOWN_REQ_HI__ACP_ShutDownReq_RAMH__SHIFT 0x0 |
| #define ACP_MEM_SHUT_DOWN_STS_LO__ACP_ShutDownSts_RAML_MASK 0xffffffff |
| #define ACP_MEM_SHUT_DOWN_STS_LO__ACP_ShutDownSts_RAML__SHIFT 0x0 |
| #define ACP_MEM_SHUT_DOWN_STS_HI__ACP_ShutDownSts_RAMH_MASK 0xffff |
| #define ACP_MEM_SHUT_DOWN_STS_HI__ACP_ShutDownSts_RAMH__SHIFT 0x0 |
| #define ACP_MEM_DEEP_SLEEP_REQ_LO__ACP_DeepSleepReq_RAML_MASK 0xffffffff |
| #define ACP_MEM_DEEP_SLEEP_REQ_LO__ACP_DeepSleepReq_RAML__SHIFT 0x0 |
| #define ACP_MEM_DEEP_SLEEP_REQ_HI__ACP_DeepSleepReq_RAMH_MASK 0xffff |
| #define ACP_MEM_DEEP_SLEEP_REQ_HI__ACP_DeepSleepReq_RAMH__SHIFT 0x0 |
| #define ACP_MEM_DEEP_SLEEP_STS_LO__ACP_DeepSleepSts_RAML_MASK 0xffffffff |
| #define ACP_MEM_DEEP_SLEEP_STS_LO__ACP_DeepSleepSts_RAML__SHIFT 0x0 |
| #define ACP_MEM_DEEP_SLEEP_STS_HI__ACP_DeepSleepSts_RAMH_MASK 0xffff |
| #define ACP_MEM_DEEP_SLEEP_STS_HI__ACP_DeepSleepSts_RAMH__SHIFT 0x0 |
| #define ACP_MEM_WAKEUP_FROM_SHUT_DOWN_LO__acp_mem_wakeup_from_shut_down_lo_MASK 0xffffffff |
| #define ACP_MEM_WAKEUP_FROM_SHUT_DOWN_LO__acp_mem_wakeup_from_shut_down_lo__SHIFT 0x0 |
| #define ACP_MEM_WAKEUP_FROM_SHUT_DOWN_HI__acp_mem_wakeup_from_shut_down_hi_MASK 0xffff |
| #define ACP_MEM_WAKEUP_FROM_SHUT_DOWN_HI__acp_mem_wakeup_from_shut_down_hi__SHIFT 0x0 |
| #define ACP_MEM_WAKEUP_FROM_SLEEP_LO__acp_mem_wakeup_from_sleep_lo_MASK 0xffffffff |
| #define ACP_MEM_WAKEUP_FROM_SLEEP_LO__acp_mem_wakeup_from_sleep_lo__SHIFT 0x0 |
| #define ACP_MEM_WAKEUP_FROM_SLEEP_HI__acp_mem_wakeup_from_sleep_hi_MASK 0xffff |
| #define ACP_MEM_WAKEUP_FROM_SLEEP_HI__acp_mem_wakeup_from_sleep_hi__SHIFT 0x0 |
| #define ACP_I2SSP_IER__I2SSP_IEN_MASK 0x1 |
| #define ACP_I2SSP_IER__I2SSP_IEN__SHIFT 0x0 |
| #define ACP_I2SSP_IRER__I2SSP_RXEN_MASK 0x1 |
| #define ACP_I2SSP_IRER__I2SSP_RXEN__SHIFT 0x0 |
| #define ACP_I2SSP_ITER__I2SSP_TXEN_MASK 0x1 |
| #define ACP_I2SSP_ITER__I2SSP_TXEN__SHIFT 0x0 |
| #define ACP_I2SSP_CER__I2SSP_CLKEN_MASK 0x1 |
| #define ACP_I2SSP_CER__I2SSP_CLKEN__SHIFT 0x0 |
| #define ACP_I2SSP_CCR__I2SSP_SCLKG_MASK 0x7 |
| #define ACP_I2SSP_CCR__I2SSP_SCLKG__SHIFT 0x0 |
| #define ACP_I2SSP_CCR__I2SSP_WSS_MASK 0x18 |
| #define ACP_I2SSP_CCR__I2SSP_WSS__SHIFT 0x3 |
| #define ACP_I2SSP_RXFFR__I2SSP_RXFFR_MASK 0x1 |
| #define ACP_I2SSP_RXFFR__I2SSP_RXFFR__SHIFT 0x0 |
| #define ACP_I2SSP_TXFFR__I2SSP_TXFFR_MASK 0x1 |
| #define ACP_I2SSP_TXFFR__I2SSP_TXFFR__SHIFT 0x0 |
| #define ACP_I2SSP_LRBR0__I2SSP_LRBR0_MASK 0xffffffff |
| #define ACP_I2SSP_LRBR0__I2SSP_LRBR0__SHIFT 0x0 |
| #define ACP_I2SSP_RRBR0__I2SSP_RRBR0_MASK 0xffffffff |
| #define ACP_I2SSP_RRBR0__I2SSP_RRBR0__SHIFT 0x0 |
| #define ACP_I2SSP_RER0__I2SSP_RXCHEN0_MASK 0x1 |
| #define ACP_I2SSP_RER0__I2SSP_RXCHEN0__SHIFT 0x0 |
| #define ACP_I2SSP_TER0__I2SSP_TXCHEN0_MASK 0x1 |
| #define ACP_I2SSP_TER0__I2SSP_TXCHEN0__SHIFT 0x0 |
| #define ACP_I2SSP_RCR0__I2SSP_WLEN_MASK 0x7 |
| #define ACP_I2SSP_RCR0__I2SSP_WLEN__SHIFT 0x0 |
| #define ACP_I2SSP_TCR0__I2SSP_WLEN_MASK 0x7 |
| #define ACP_I2SSP_TCR0__I2SSP_WLEN__SHIFT 0x0 |
| #define ACP_I2SSP_ISR0__I2SSP_RXDA_MASK 0x1 |
| #define ACP_I2SSP_ISR0__I2SSP_RXDA__SHIFT 0x0 |
| #define ACP_I2SSP_ISR0__I2SSP_RXFO_MASK 0x2 |
| #define ACP_I2SSP_ISR0__I2SSP_RXFO__SHIFT 0x1 |
| #define ACP_I2SSP_ISR0__I2SSP_TXFE_MASK 0x10 |
| #define ACP_I2SSP_ISR0__I2SSP_TXFE__SHIFT 0x4 |
| #define ACP_I2SSP_ISR0__I2SSP_TXFO_MASK 0x20 |
| #define ACP_I2SSP_ISR0__I2SSP_TXFO__SHIFT 0x5 |
| #define ACP_I2SSP_IMR0__I2SSP_RXDAM_MASK 0x1 |
| #define ACP_I2SSP_IMR0__I2SSP_RXDAM__SHIFT 0x0 |
| #define ACP_I2SSP_IMR0__I2SSP_RXFOM_MASK 0x2 |
| #define ACP_I2SSP_IMR0__I2SSP_RXFOM__SHIFT 0x1 |
| #define ACP_I2SSP_IMR0__I2SSP_TXFEM_MASK 0x10 |
| #define ACP_I2SSP_IMR0__I2SSP_TXFEM__SHIFT 0x4 |
| #define ACP_I2SSP_IMR0__I2SSP_TXFOM_MASK 0x20 |
| #define ACP_I2SSP_IMR0__I2SSP_TXFOM__SHIFT 0x5 |
| #define ACP_I2SSP_ROR0__I2SSP_RXCHO_MASK 0x1 |
| #define ACP_I2SSP_ROR0__I2SSP_RXCHO__SHIFT 0x0 |
| #define ACP_I2SSP_TOR0__I2SSP_TXCHO_MASK 0x1 |
| #define ACP_I2SSP_TOR0__I2SSP_TXCHO__SHIFT 0x0 |
| #define ACP_I2SSP_RFCR0__I2SSP_RXCHDT_MASK 0xf |
| #define ACP_I2SSP_RFCR0__I2SSP_RXCHDT__SHIFT 0x0 |
| #define ACP_I2SSP_TFCR0__I2SSP_TXCHET_MASK 0xf |
| #define ACP_I2SSP_TFCR0__I2SSP_TXCHET__SHIFT 0x0 |
| #define ACP_I2SSP_RFF0__I2SSP_RXCHFR_MASK 0x1 |
| #define ACP_I2SSP_RFF0__I2SSP_RXCHFR__SHIFT 0x0 |
| #define ACP_I2SSP_TFF0__I2SSP_TXCHFR_MASK 0x1 |
| #define ACP_I2SSP_TFF0__I2SSP_TXCHFR__SHIFT 0x0 |
| #define ACP_I2SSP_RXDMA__I2SSP_RXDMA_MASK 0xffffffff |
| #define ACP_I2SSP_RXDMA__I2SSP_RXDMA__SHIFT 0x0 |
| #define ACP_I2SSP_RRXDMA__I2SSP_RRXDMA_MASK 0x1 |
| #define ACP_I2SSP_RRXDMA__I2SSP_RRXDMA__SHIFT 0x0 |
| #define ACP_I2SSP_TXDMA__I2SSP_TXDMA_MASK 0xffffffff |
| #define ACP_I2SSP_TXDMA__I2SSP_TXDMA__SHIFT 0x0 |
| #define ACP_I2SSP_RTXDMA__I2SSP_RTXDMA_MASK 0x1 |
| #define ACP_I2SSP_RTXDMA__I2SSP_RTXDMA__SHIFT 0x0 |
| #define ACP_I2SSP_COMP_PARAM_2__I2SSP_RX_WPRDSIZE_0_MASK 0x7 |
| #define ACP_I2SSP_COMP_PARAM_2__I2SSP_RX_WPRDSIZE_0__SHIFT 0x0 |
| #define ACP_I2SSP_COMP_PARAM_2__I2SSP_RX_WPRDSIZE_1_MASK 0x38 |
| #define ACP_I2SSP_COMP_PARAM_2__I2SSP_RX_WPRDSIZE_1__SHIFT 0x3 |
| #define ACP_I2SSP_COMP_PARAM_2__I2SSP_RX_WPRDSIZE_2_MASK 0x380 |
| #define ACP_I2SSP_COMP_PARAM_2__I2SSP_RX_WPRDSIZE_2__SHIFT 0x7 |
| #define ACP_I2SSP_COMP_PARAM_2__I2SSP_RX_WPRDSIZE_3_MASK 0x1c00 |
| #define ACP_I2SSP_COMP_PARAM_2__I2SSP_RX_WPRDSIZE_3__SHIFT 0xa |
| #define ACP_I2SSP_COMP_PARAM_1__I2SSP_APB_DATA_WIDTH_MASK 0x3 |
| #define ACP_I2SSP_COMP_PARAM_1__I2SSP_APB_DATA_WIDTH__SHIFT 0x0 |
| #define ACP_I2SSP_COMP_PARAM_1__I2SSP_FIFO_DEPTH_GLOBAL_MASK 0xc |
| #define ACP_I2SSP_COMP_PARAM_1__I2SSP_FIFO_DEPTH_GLOBAL__SHIFT 0x2 |
| #define ACP_I2SSP_COMP_PARAM_1__I2SSP_MODE_EN_MASK 0x10 |
| #define ACP_I2SSP_COMP_PARAM_1__I2SSP_MODE_EN__SHIFT 0x4 |
| #define ACP_I2SSP_COMP_PARAM_1__I2SSP_TRANSMITTER_BLOCK_MASK 0x20 |
| #define ACP_I2SSP_COMP_PARAM_1__I2SSP_TRANSMITTER_BLOCK__SHIFT 0x5 |
| #define ACP_I2SSP_COMP_PARAM_1__I2SSP_RECEIVER_BLOCK_MASK 0x40 |
| #define ACP_I2SSP_COMP_PARAM_1__I2SSP_RECEIVER_BLOCK__SHIFT 0x6 |
| #define ACP_I2SSP_COMP_PARAM_1__I2SSP_RX_CHANNLES_MASK 0x180 |
| #define ACP_I2SSP_COMP_PARAM_1__I2SSP_RX_CHANNLES__SHIFT 0x7 |
| #define ACP_I2SSP_COMP_PARAM_1__I2SSP_TX_CHANNLES_MASK 0x600 |
| #define ACP_I2SSP_COMP_PARAM_1__I2SSP_TX_CHANNLES__SHIFT 0x9 |
| #define ACP_I2SSP_COMP_PARAM_1__I2SSP_TX_WORDSIZE_0_MASK 0x70000 |
| #define ACP_I2SSP_COMP_PARAM_1__I2SSP_TX_WORDSIZE_0__SHIFT 0x10 |
| #define ACP_I2SSP_COMP_PARAM_1__I2SSP_TX_WORDSIZE_1_MASK 0x380000 |
| #define ACP_I2SSP_COMP_PARAM_1__I2SSP_TX_WORDSIZE_1__SHIFT 0x13 |
| #define ACP_I2SSP_COMP_PARAM_1__I2SSP_TX_WORDSIZE_2_MASK 0x1c00000 |
| #define ACP_I2SSP_COMP_PARAM_1__I2SSP_TX_WORDSIZE_2__SHIFT 0x16 |
| #define ACP_I2SSP_COMP_PARAM_1__I2SSP_TX_WORDSIZE_3_MASK 0xe000000 |
| #define ACP_I2SSP_COMP_PARAM_1__I2SSP_TX_WORDSIZE_3__SHIFT 0x19 |
| #define ACP_I2SSP_COMP_VERSION__I2SSP_APB_DATA_WIDTH_MASK 0xffffffff |
| #define ACP_I2SSP_COMP_VERSION__I2SSP_APB_DATA_WIDTH__SHIFT 0x0 |
| #define ACP_I2SSP_COMP_TYPE__I2SSP_COMP_TYPE_MASK 0xffffffff |
| #define ACP_I2SSP_COMP_TYPE__I2SSP_COMP_TYPE__SHIFT 0x0 |
| #define ACP_I2SMICSP_IER__I2SMICSP_IEN_MASK 0x1 |
| #define ACP_I2SMICSP_IER__I2SMICSP_IEN__SHIFT 0x0 |
| #define ACP_I2SMICSP_IRER__I2SMICSP_RXEN_MASK 0x1 |
| #define ACP_I2SMICSP_IRER__I2SMICSP_RXEN__SHIFT 0x0 |
| #define ACP_I2SMICSP_ITER__I2SMICSP_TXEN_MASK 0x1 |
| #define ACP_I2SMICSP_ITER__I2SMICSP_TXEN__SHIFT 0x0 |
| #define ACP_I2SMICSP_CER__I2SMICSP_CLKEN_MASK 0x1 |
| #define ACP_I2SMICSP_CER__I2SMICSP_CLKEN__SHIFT 0x0 |
| #define ACP_I2SMICSP_CCR__I2SMICSP_SCLKG_MASK 0x7 |
| #define ACP_I2SMICSP_CCR__I2SMICSP_SCLKG__SHIFT 0x0 |
| #define ACP_I2SMICSP_CCR__I2SMICSP_WSS_MASK 0x18 |
| #define ACP_I2SMICSP_CCR__I2SMICSP_WSS__SHIFT 0x3 |
| #define ACP_I2SMICSP_RXFFR__I2SMICSP_RXFFR_MASK 0x1 |
| #define ACP_I2SMICSP_RXFFR__I2SMICSP_RXFFR__SHIFT 0x0 |
| #define ACP_I2SMICSP_TXFFR__I2SMICSP_TXFFR_MASK 0x1 |
| #define ACP_I2SMICSP_TXFFR__I2SMICSP_TXFFR__SHIFT 0x0 |
| #define ACP_I2SMICSP_LRBR0__I2SMICSP_LRBR0_MASK 0xffffffff |
| #define ACP_I2SMICSP_LRBR0__I2SMICSP_LRBR0__SHIFT 0x0 |
| #define ACP_I2SMICSP_RRBR0__I2SMICSP_RRBR0_MASK 0xffffffff |
| #define ACP_I2SMICSP_RRBR0__I2SMICSP_RRBR0__SHIFT 0x0 |
| #define ACP_I2SMICSP_RER0__I2SMICSP_RXCHEN0_MASK 0x1 |
| #define ACP_I2SMICSP_RER0__I2SMICSP_RXCHEN0__SHIFT 0x0 |
| #define ACP_I2SMICSP_TER0__I2SMICSP_TXCHEN0_MASK 0x1 |
| #define ACP_I2SMICSP_TER0__I2SMICSP_TXCHEN0__SHIFT 0x0 |
| #define ACP_I2SMICSP_RCR0__I2SMICSP_WLEN_MASK 0x7 |
| #define ACP_I2SMICSP_RCR0__I2SMICSP_WLEN__SHIFT 0x0 |
| #define ACP_I2SMICSP_TCR0__I2SMICSP_WLEN_MASK 0x7 |
| #define ACP_I2SMICSP_TCR0__I2SMICSP_WLEN__SHIFT 0x0 |
| #define ACP_I2SMICSP_ISR0__I2SMICSP_RXDA_MASK 0x1 |
| #define ACP_I2SMICSP_ISR0__I2SMICSP_RXDA__SHIFT 0x0 |
| #define ACP_I2SMICSP_ISR0__I2SMICSP_RXFO_MASK 0x2 |
| #define ACP_I2SMICSP_ISR0__I2SMICSP_RXFO__SHIFT 0x1 |
| #define ACP_I2SMICSP_ISR0__I2SMICSP_TXFE_MASK 0x10 |
| #define ACP_I2SMICSP_ISR0__I2SMICSP_TXFE__SHIFT 0x4 |
| #define ACP_I2SMICSP_ISR0__I2SMICSP_TXFO_MASK 0x20 |
| #define ACP_I2SMICSP_ISR0__I2SMICSP_TXFO__SHIFT 0x5 |
| #define ACP_I2SMICSP_IMR0__I2SMICSP_RXDAM_MASK 0x1 |
| #define ACP_I2SMICSP_IMR0__I2SMICSP_RXDAM__SHIFT 0x0 |
| #define ACP_I2SMICSP_IMR0__I2SMICSP_RXFOM_MASK 0x2 |
| #define ACP_I2SMICSP_IMR0__I2SMICSP_RXFOM__SHIFT 0x1 |
| #define ACP_I2SMICSP_IMR0__I2SMICSP_TXFEM_MASK 0x10 |
| #define ACP_I2SMICSP_IMR0__I2SMICSP_TXFEM__SHIFT 0x4 |
| #define ACP_I2SMICSP_IMR0__I2SMICSP_TXFOM_MASK 0x20 |
| #define ACP_I2SMICSP_IMR0__I2SMICSP_TXFOM__SHIFT 0x5 |
| #define ACP_I2SMICSP_ROR0__I2SMICSP_RXCHO_MASK 0x1 |
| #define ACP_I2SMICSP_ROR0__I2SMICSP_RXCHO__SHIFT 0x0 |
| #define ACP_I2SMICSP_TOR0__I2SMICSP_TXCHO_MASK 0x1 |
| #define ACP_I2SMICSP_TOR0__I2SMICSP_TXCHO__SHIFT 0x0 |
| #define ACP_I2SMICSP_RFCR0__I2SMICSP_RXCHDT_MASK 0xf |
| #define ACP_I2SMICSP_RFCR0__I2SMICSP_RXCHDT__SHIFT 0x0 |
| #define ACP_I2SMICSP_TFCR0__I2SMICSP_TXCHET_MASK 0xf |
| #define ACP_I2SMICSP_TFCR0__I2SMICSP_TXCHET__SHIFT 0x0 |
| #define ACP_I2SMICSP_RFF0__I2SMICSP_RXCHFR_MASK 0x1 |
| #define ACP_I2SMICSP_RFF0__I2SMICSP_RXCHFR__SHIFT 0x0 |
| #define ACP_I2SMICSP_TFF0__I2SMICSP_TXCHFR_MASK 0x1 |
| #define ACP_I2SMICSP_TFF0__I2SMICSP_TXCHFR__SHIFT 0x0 |
| #define ACP_I2SMICSP_LRBR1__I2SMICSP_LRBR1_MASK 0xffffffff |
| #define ACP_I2SMICSP_LRBR1__I2SMICSP_LRBR1__SHIFT 0x0 |
| #define ACP_I2SMICSP_RRBR1__I2SMICSP_RRBR1_MASK 0xffffffff |
| #define ACP_I2SMICSP_RRBR1__I2SMICSP_RRBR1__SHIFT 0x0 |
| #define ACP_I2SMICSP_RER1__I2SMICSP_RXCHEN1_MASK 0x1 |
| #define ACP_I2SMICSP_RER1__I2SMICSP_RXCHEN1__SHIFT 0x0 |
| #define ACP_I2SMICSP_TER1__I2SMICSP_TXCHEN1_MASK 0x1 |
| #define ACP_I2SMICSP_TER1__I2SMICSP_TXCHEN1__SHIFT 0x0 |
| #define ACP_I2SMICSP_RCR1__I2SMICSP_WLEN_MASK 0x7 |
| #define ACP_I2SMICSP_RCR1__I2SMICSP_WLEN__SHIFT 0x0 |
| #define ACP_I2SMICSP_TCR1__I2SMICSP_WLEN_MASK 0x7 |
| #define ACP_I2SMICSP_TCR1__I2SMICSP_WLEN__SHIFT 0x0 |
| #define ACP_I2SMICSP_ISR1__I2SMICSP_RXDA_MASK 0x1 |
| #define ACP_I2SMICSP_ISR1__I2SMICSP_RXDA__SHIFT 0x0 |
| #define ACP_I2SMICSP_ISR1__I2SMICSP_RXFO_MASK 0x2 |
| #define ACP_I2SMICSP_ISR1__I2SMICSP_RXFO__SHIFT 0x1 |
| #define ACP_I2SMICSP_ISR1__I2SMICSP_TXFE_MASK 0x10 |
| #define ACP_I2SMICSP_ISR1__I2SMICSP_TXFE__SHIFT 0x4 |
| #define ACP_I2SMICSP_ISR1__I2SMICSP_TXFO_MASK 0x20 |
| #define ACP_I2SMICSP_ISR1__I2SMICSP_TXFO__SHIFT 0x5 |
| #define ACP_I2SMICSP_IMR1__I2SMICSP_RXDAM_MASK 0x1 |
| #define ACP_I2SMICSP_IMR1__I2SMICSP_RXDAM__SHIFT 0x0 |
| #define ACP_I2SMICSP_IMR1__I2SMICSP_RXFOM_MASK 0x2 |
| #define ACP_I2SMICSP_IMR1__I2SMICSP_RXFOM__SHIFT 0x1 |
| #define ACP_I2SMICSP_IMR1__I2SMICSP_TXFEM_MASK 0x10 |
| #define ACP_I2SMICSP_IMR1__I2SMICSP_TXFEM__SHIFT 0x4 |
| #define ACP_I2SMICSP_IMR1__I2SMICSP_TXFOM_MASK 0x20 |
| #define ACP_I2SMICSP_IMR1__I2SMICSP_TXFOM__SHIFT 0x5 |
| #define ACP_I2SMICSP_ROR1__I2SMICSP_RXCHO_MASK 0x1 |
| #define ACP_I2SMICSP_ROR1__I2SMICSP_RXCHO__SHIFT 0x0 |
| #define ACP_I2SMICSP_TOR1__I2SMICSP_TXCHO_MASK 0x1 |
| #define ACP_I2SMICSP_TOR1__I2SMICSP_TXCHO__SHIFT 0x0 |
| #define ACP_I2SMICSP_RFCR1__I2SMICSP_RXCHDT_MASK 0xf |
| #define ACP_I2SMICSP_RFCR1__I2SMICSP_RXCHDT__SHIFT 0x0 |
| #define ACP_I2SMICSP_TFCR1__I2SMICSP_TXCHET_MASK 0xf |
| #define ACP_I2SMICSP_TFCR1__I2SMICSP_TXCHET__SHIFT 0x0 |
| #define ACP_I2SMICSP_RFF1__I2SMICSP_RXCHFR_MASK 0x1 |
| #define ACP_I2SMICSP_RFF1__I2SMICSP_RXCHFR__SHIFT 0x0 |
| #define ACP_I2SMICSP_TFF1__I2SMICSP_TXCHFR_MASK 0x1 |
| #define ACP_I2SMICSP_TFF1__I2SMICSP_TXCHFR__SHIFT 0x0 |
| #define ACP_I2SMICSP_RXDMA__I2SMICSP_RXDMA_MASK 0xffffffff |
| #define ACP_I2SMICSP_RXDMA__I2SMICSP_RXDMA__SHIFT 0x0 |
| #define ACP_I2SMICSP_RRXDMA__I2SMICSP_RRXDMA_MASK 0x1 |
| #define ACP_I2SMICSP_RRXDMA__I2SMICSP_RRXDMA__SHIFT 0x0 |
| #define ACP_I2SMICSP_TXDMA__I2SMICSP_TXDMA_MASK 0xffffffff |
| #define ACP_I2SMICSP_TXDMA__I2SMICSP_TXDMA__SHIFT 0x0 |
| #define ACP_I2SMICSP_RTXDMA__I2SMICSP_RTXDMA_MASK 0x1 |
| #define ACP_I2SMICSP_RTXDMA__I2SMICSP_RTXDMA__SHIFT 0x0 |
| #define ACP_I2SMICSP_COMP_PARAM_2__I2SMICSP_RX_WPRDSIZE_0_MASK 0x7 |
| #define ACP_I2SMICSP_COMP_PARAM_2__I2SMICSP_RX_WPRDSIZE_0__SHIFT 0x0 |
| #define ACP_I2SMICSP_COMP_PARAM_2__I2SMICSP_RX_WPRDSIZE_1_MASK 0x38 |
| #define ACP_I2SMICSP_COMP_PARAM_2__I2SMICSP_RX_WPRDSIZE_1__SHIFT 0x3 |
| #define ACP_I2SMICSP_COMP_PARAM_2__I2SMICSP_RX_WPRDSIZE_2_MASK 0x380 |
| #define ACP_I2SMICSP_COMP_PARAM_2__I2SMICSP_RX_WPRDSIZE_2__SHIFT 0x7 |
| #define ACP_I2SMICSP_COMP_PARAM_2__I2SMICSP_RX_WPRDSIZE_3_MASK 0x1c00 |
| #define ACP_I2SMICSP_COMP_PARAM_2__I2SMICSP_RX_WPRDSIZE_3__SHIFT 0xa |
| #define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_APB_DATA_WIDTH_MASK 0x3 |
| #define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_APB_DATA_WIDTH__SHIFT 0x0 |
| #define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_FIFO_DEPTH_GLOBAL_MASK 0xc |
| #define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_FIFO_DEPTH_GLOBAL__SHIFT 0x2 |
| #define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_MODE_EN_MASK 0x10 |
| #define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_MODE_EN__SHIFT 0x4 |
| #define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_TRANSMITTER_BLOCK_MASK 0x20 |
| #define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_TRANSMITTER_BLOCK__SHIFT 0x5 |
| #define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_RECEIVER_BLOCK_MASK 0x40 |
| #define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_RECEIVER_BLOCK__SHIFT 0x6 |
| #define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_RX_CHANNLES_MASK 0x180 |
| #define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_RX_CHANNLES__SHIFT 0x7 |
| #define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_TX_CHANNLES_MASK 0x600 |
| #define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_TX_CHANNLES__SHIFT 0x9 |
| #define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_TX_WORDSIZE_0_MASK 0x70000 |
| #define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_TX_WORDSIZE_0__SHIFT 0x10 |
| #define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_TX_WORDSIZE_1_MASK 0x380000 |
| #define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_TX_WORDSIZE_1__SHIFT 0x13 |
| #define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_TX_WORDSIZE_2_MASK 0x1c00000 |
| #define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_TX_WORDSIZE_2__SHIFT 0x16 |
| #define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_TX_WORDSIZE_3_MASK 0xe000000 |
| #define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_TX_WORDSIZE_3__SHIFT 0x19 |
| #define ACP_I2SMICSP_COMP_VERSION__I2SMICSP_APB_DATA_WIDTH_MASK 0xffffffff |
| #define ACP_I2SMICSP_COMP_VERSION__I2SMICSP_APB_DATA_WIDTH__SHIFT 0x0 |
| #define ACP_I2SMICSP_COMP_TYPE__I2SMICSP_COMP_TYPE_MASK 0xffffffff |
| #define ACP_I2SMICSP_COMP_TYPE__I2SMICSP_COMP_TYPE__SHIFT 0x0 |
| #define ACP_I2SBT_IER__I2SBT_IEN_MASK 0x1 |
| #define ACP_I2SBT_IER__I2SBT_IEN__SHIFT 0x0 |
| #define ACP_I2SBT_IRER__I2SBT_RXEN_MASK 0x1 |
| #define ACP_I2SBT_IRER__I2SBT_RXEN__SHIFT 0x0 |
| #define ACP_I2SBT_ITER__I2SBT_TXEN_MASK 0x1 |
| #define ACP_I2SBT_ITER__I2SBT_TXEN__SHIFT 0x0 |
| #define ACP_I2SBT_CER__I2SBT_CLKEN_MASK 0x1 |
| #define ACP_I2SBT_CER__I2SBT_CLKEN__SHIFT 0x0 |
| #define ACP_I2SBT_CCR__I2SBT_SCLKG_MASK 0x7 |
| #define ACP_I2SBT_CCR__I2SBT_SCLKG__SHIFT 0x0 |
| #define ACP_I2SBT_CCR__I2SBT_WSS_MASK 0x18 |
| #define ACP_I2SBT_CCR__I2SBT_WSS__SHIFT 0x3 |
| #define ACP_I2SBT_RXFFR__I2SBT_RXFFR_MASK 0x1 |
| #define ACP_I2SBT_RXFFR__I2SBT_RXFFR__SHIFT 0x0 |
| #define ACP_I2SBT_TXFFR__I2SBT_TXFFR_MASK 0x1 |
| #define ACP_I2SBT_TXFFR__I2SBT_TXFFR__SHIFT 0x0 |
| #define ACP_I2SBT_LRBR0__I2SBT_LRBR0_MASK 0xffffffff |
| #define ACP_I2SBT_LRBR0__I2SBT_LRBR0__SHIFT 0x0 |
| #define ACP_I2SBT_RRBR0__I2SBT_RRBR0_MASK 0xffffffff |
| #define ACP_I2SBT_RRBR0__I2SBT_RRBR0__SHIFT 0x0 |
| #define ACP_I2SBT_RER0__I2SBT_RXCHEN0_MASK 0x1 |
| #define ACP_I2SBT_RER0__I2SBT_RXCHEN0__SHIFT 0x0 |
| #define ACP_I2SBT_TER0__I2SBT_TXCHEN0_MASK 0x1 |
| #define ACP_I2SBT_TER0__I2SBT_TXCHEN0__SHIFT 0x0 |
| #define ACP_I2SBT_RCR0__I2SBT_WLEN_MASK 0x7 |
| #define ACP_I2SBT_RCR0__I2SBT_WLEN__SHIFT 0x0 |
| #define ACP_I2SBT_TCR0__I2SBT_WLEN_MASK 0x7 |
| #define ACP_I2SBT_TCR0__I2SBT_WLEN__SHIFT 0x0 |
| #define ACP_I2SBT_ISR0__I2SBT_RXDA_MASK 0x1 |
| #define ACP_I2SBT_ISR0__I2SBT_RXDA__SHIFT 0x0 |
| #define ACP_I2SBT_ISR0__I2SBT_RXFO_MASK 0x2 |
| #define ACP_I2SBT_ISR0__I2SBT_RXFO__SHIFT 0x1 |
| #define ACP_I2SBT_ISR0__I2SBT_TXFE_MASK 0x10 |
| #define ACP_I2SBT_ISR0__I2SBT_TXFE__SHIFT 0x4 |
| #define ACP_I2SBT_ISR0__I2SBT_TXFO_MASK 0x20 |
| #define ACP_I2SBT_ISR0__I2SBT_TXFO__SHIFT 0x5 |
| #define ACP_I2SBT_IMR0__I2SBT_RXDAM_MASK 0x1 |
| #define ACP_I2SBT_IMR0__I2SBT_RXDAM__SHIFT 0x0 |
| #define ACP_I2SBT_IMR0__I2SBT_RXFOM_MASK 0x2 |
| #define ACP_I2SBT_IMR0__I2SBT_RXFOM__SHIFT 0x1 |
| #define ACP_I2SBT_IMR0__I2SBT_TXFEM_MASK 0x10 |
| #define ACP_I2SBT_IMR0__I2SBT_TXFEM__SHIFT 0x4 |
| #define ACP_I2SBT_IMR0__I2SBT_TXFOM_MASK 0x20 |
| #define ACP_I2SBT_IMR0__I2SBT_TXFOM__SHIFT 0x5 |
| #define ACP_I2SBT_ROR0__I2SBT_RXCHO_MASK 0x1 |
| #define ACP_I2SBT_ROR0__I2SBT_RXCHO__SHIFT 0x0 |
| #define ACP_I2SBT_TOR0__I2SBT_TXCHO_MASK 0x1 |
| #define ACP_I2SBT_TOR0__I2SBT_TXCHO__SHIFT 0x0 |
| #define ACP_I2SBT_RFCR0__I2SBT_RXCHDT_MASK 0xf |
| #define ACP_I2SBT_RFCR0__I2SBT_RXCHDT__SHIFT 0x0 |
| #define ACP_I2SBT_TFCR0__I2SBT_TXCHET_MASK 0xf |
| #define ACP_I2SBT_TFCR0__I2SBT_TXCHET__SHIFT 0x0 |
| #define ACP_I2SBT_RFF0__I2SBT_RXCHFR_MASK 0x1 |
| #define ACP_I2SBT_RFF0__I2SBT_RXCHFR__SHIFT 0x0 |
| #define ACP_I2SBT_TFF0__I2SBT_TXCHFR_MASK 0x1 |
| #define ACP_I2SBT_TFF0__I2SBT_TXCHFR__SHIFT 0x0 |
| #define ACP_I2SBT_LRBR1__I2SBT_LRBR1_MASK 0xffffffff |
| #define ACP_I2SBT_LRBR1__I2SBT_LRBR1__SHIFT 0x0 |
| #define ACP_I2SBT_RRBR1__I2SBT_RRBR1_MASK 0xffffffff |
| #define ACP_I2SBT_RRBR1__I2SBT_RRBR1__SHIFT 0x0 |
| #define ACP_I2SBT_RER1__I2SBT_RXCHEN1_MASK 0x1 |
| #define ACP_I2SBT_RER1__I2SBT_RXCHEN1__SHIFT 0x0 |
| #define ACP_I2SBT_TER1__I2SBT_TXCHEN1_MASK 0x1 |
| #define ACP_I2SBT_TER1__I2SBT_TXCHEN1__SHIFT 0x0 |
| #define ACP_I2SBT_RCR1__I2SBT_WLEN_MASK 0x7 |
| #define ACP_I2SBT_RCR1__I2SBT_WLEN__SHIFT 0x0 |
| #define ACP_I2SBT_TCR1__I2SBT_WLEN_MASK 0x7 |
| #define ACP_I2SBT_TCR1__I2SBT_WLEN__SHIFT 0x0 |
| #define ACP_I2SBT_ISR1__I2SBT_RXDA_MASK 0x1 |
| #define ACP_I2SBT_ISR1__I2SBT_RXDA__SHIFT 0x0 |
| #define ACP_I2SBT_ISR1__I2SBT_RXFO_MASK 0x2 |
| #define ACP_I2SBT_ISR1__I2SBT_RXFO__SHIFT 0x1 |
| #define ACP_I2SBT_ISR1__I2SBT_TXFE_MASK 0x10 |
| #define ACP_I2SBT_ISR1__I2SBT_TXFE__SHIFT 0x4 |
| #define ACP_I2SBT_ISR1__I2SBT_TXFO_MASK 0x20 |
| #define ACP_I2SBT_ISR1__I2SBT_TXFO__SHIFT 0x5 |
| #define ACP_I2SBT_IMR1__I2SBT_RXDAM_MASK 0x1 |
| #define ACP_I2SBT_IMR1__I2SBT_RXDAM__SHIFT 0x0 |
| #define ACP_I2SBT_IMR1__I2SBT_RXFOM_MASK 0x2 |
| #define ACP_I2SBT_IMR1__I2SBT_RXFOM__SHIFT 0x1 |
| #define ACP_I2SBT_IMR1__I2SBT_TXFEM_MASK 0x10 |
| #define ACP_I2SBT_IMR1__I2SBT_TXFEM__SHIFT 0x4 |
| #define ACP_I2SBT_IMR1__I2SBT_TXFOM_MASK 0x20 |
| #define ACP_I2SBT_IMR1__I2SBT_TXFOM__SHIFT 0x5 |
| #define ACP_I2SBT_ROR1__I2SBT_RXCHO_MASK 0x1 |
| #define ACP_I2SBT_ROR1__I2SBT_RXCHO__SHIFT 0x0 |
| #define ACP_I2SBT_TOR1__I2SBT_TXCHO_MASK 0x1 |
| #define ACP_I2SBT_TOR1__I2SBT_TXCHO__SHIFT 0x0 |
| #define ACP_I2SBT_RFCR1__I2SBT_RXCHDT_MASK 0xf |
| #define ACP_I2SBT_RFCR1__I2SBT_RXCHDT__SHIFT 0x0 |
| #define ACP_I2SBT_TFCR1__I2SBT_TXCHET_MASK 0xf |
| #define ACP_I2SBT_TFCR1__I2SBT_TXCHET__SHIFT 0x0 |
| #define ACP_I2SBT_RFF1__I2SBT_RXCHFR_MASK 0x1 |
| #define ACP_I2SBT_RFF1__I2SBT_RXCHFR__SHIFT 0x0 |
| #define ACP_I2SBT_TFF1__I2SBT_TXCHFR_MASK 0x1 |
| #define ACP_I2SBT_TFF1__I2SBT_TXCHFR__SHIFT 0x0 |
| #define ACP_I2SBT_RXDMA__I2SBT_RXDMA_MASK 0xffffffff |
| #define ACP_I2SBT_RXDMA__I2SBT_RXDMA__SHIFT 0x0 |
| #define ACP_I2SBT_RRXDMA__I2SBT_RRXDMA_MASK 0x1 |
| #define ACP_I2SBT_RRXDMA__I2SBT_RRXDMA__SHIFT 0x0 |
| #define ACP_I2SBT_TXDMA__I2SBT_TXDMA_MASK 0xffffffff |
| #define ACP_I2SBT_TXDMA__I2SBT_TXDMA__SHIFT 0x0 |
| #define ACP_I2SBT_RTXDMA__I2SBT_RTXDMA_MASK 0x1 |
| #define ACP_I2SBT_RTXDMA__I2SBT_RTXDMA__SHIFT 0x0 |
| #define ACP_I2SBT_COMP_PARAM_2__I2SBT_RX_WPRDSIZE_0_MASK 0x7 |
| #define ACP_I2SBT_COMP_PARAM_2__I2SBT_RX_WPRDSIZE_0__SHIFT 0x0 |
| #define ACP_I2SBT_COMP_PARAM_2__I2SBT_RX_WPRDSIZE_1_MASK 0x38 |
| #define ACP_I2SBT_COMP_PARAM_2__I2SBT_RX_WPRDSIZE_1__SHIFT 0x3 |
| #define ACP_I2SBT_COMP_PARAM_2__I2SBT_RX_WPRDSIZE_2_MASK 0x380 |
| #define ACP_I2SBT_COMP_PARAM_2__I2SBT_RX_WPRDSIZE_2__SHIFT 0x7 |
| #define ACP_I2SBT_COMP_PARAM_2__I2SBT_RX_WPRDSIZE_3_MASK 0x1c00 |
| #define ACP_I2SBT_COMP_PARAM_2__I2SBT_RX_WPRDSIZE_3__SHIFT 0xa |
| #define ACP_I2SBT_COMP_PARAM_1__I2SBT_APB_DATA_WIDTH_MASK 0x3 |
| #define ACP_I2SBT_COMP_PARAM_1__I2SBT_APB_DATA_WIDTH__SHIFT 0x0 |
| #define ACP_I2SBT_COMP_PARAM_1__I2SBT_FIFO_DEPTH_GLOBAL_MASK 0xc |
| #define ACP_I2SBT_COMP_PARAM_1__I2SBT_FIFO_DEPTH_GLOBAL__SHIFT 0x2 |
| #define ACP_I2SBT_COMP_PARAM_1__I2SBT_MODE_EN_MASK 0x10 |
| #define ACP_I2SBT_COMP_PARAM_1__I2SBT_MODE_EN__SHIFT 0x4 |
| #define ACP_I2SBT_COMP_PARAM_1__I2SBT_TRANSMITTER_BLOCK_MASK 0x20 |
| #define ACP_I2SBT_COMP_PARAM_1__I2SBT_TRANSMITTER_BLOCK__SHIFT 0x5 |
| #define ACP_I2SBT_COMP_PARAM_1__I2SBT_RECEIVER_BLOCK_MASK 0x40 |
| #define ACP_I2SBT_COMP_PARAM_1__I2SBT_RECEIVER_BLOCK__SHIFT 0x6 |
| #define ACP_I2SBT_COMP_PARAM_1__I2SBT_RX_CHANNLES_MASK 0x180 |
| #define ACP_I2SBT_COMP_PARAM_1__I2SBT_RX_CHANNLES__SHIFT 0x7 |
| #define ACP_I2SBT_COMP_PARAM_1__I2SBT_TX_CHANNLES_MASK 0x600 |
| #define ACP_I2SBT_COMP_PARAM_1__I2SBT_TX_CHANNLES__SHIFT 0x9 |
| #define ACP_I2SBT_COMP_PARAM_1__I2SBT_TX_WORDSIZE_0_MASK 0x70000 |
| #define ACP_I2SBT_COMP_PARAM_1__I2SBT_TX_WORDSIZE_0__SHIFT 0x10 |
| #define ACP_I2SBT_COMP_PARAM_1__I2SBT_TX_WORDSIZE_1_MASK 0x380000 |
| #define ACP_I2SBT_COMP_PARAM_1__I2SBT_TX_WORDSIZE_1__SHIFT 0x13 |
| #define ACP_I2SBT_COMP_PARAM_1__I2SBT_TX_WORDSIZE_2_MASK 0x1c00000 |
| #define ACP_I2SBT_COMP_PARAM_1__I2SBT_TX_WORDSIZE_2__SHIFT 0x16 |
| #define ACP_I2SBT_COMP_PARAM_1__I2SBT_TX_WORDSIZE_3_MASK 0xe000000 |
| #define ACP_I2SBT_COMP_PARAM_1__I2SBT_TX_WORDSIZE_3__SHIFT 0x19 |
| #define ACP_I2SBT_COMP_VERSION__I2SBT_APB_DATA_WIDTH_MASK 0xffffffff |
| #define ACP_I2SBT_COMP_VERSION__I2SBT_APB_DATA_WIDTH__SHIFT 0x0 |
| #define ACP_I2SBT_COMP_TYPE__I2SBT_COMP_TYPE_MASK 0xffffffff |
| #define ACP_I2SBT_COMP_TYPE__I2SBT_COMP_TYPE__SHIFT 0x0 |
| |
| #endif /* ACP_2_2_SH_MASK_H */ |
