Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/microchip/microchip,mpfs-sys-controller.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Microchip PolarFire SoC (MPFS) MSS (microprocessor subsystem) system controller

maintainers:
  - Conor Dooley <conor.dooley@microchip.com>

description: |
  PolarFire SoC devices include a microcontroller acting as the system controller,
  which provides "services" to the main processor and to the FPGA fabric. These
  services include hardware rng, reprogramming of the FPGA and verification of the
  eNVM contents etc. More information on these services can be found online, at
  https://onlinedocs.microchip.com/pr/GUID-1409CF11-8EF9-4C24-A94E-70979A688632-en-US-1/index.html

  Communication with the system controller is done via a mailbox, of which the client
  portion is documented here.

properties:
  mboxes:
    maxItems: 1

  compatible:
    enum:
      - microchip,mpfs-sys-controller
      - microchip,pic64gx-sys-controller

  microchip,bitstream-flash:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      The SPI flash connected to the system controller's QSPI controller.
      The system controller may retrieve FPGA bitstreams from this flash to
      perform In-Application Programming (IAP) or during device initialisation
      for Auto Update. The MSS and system controller have separate QSPI
      controllers and this flash is connected to both. Software running in the
      MSS can write bitstreams to the flash.

required:
  - compatible
  - mboxes

additionalProperties: false

examples:
  - |
    syscontroller {
      compatible = "microchip,mpfs-sys-controller";
      mboxes = <&mbox 0>;
    };