| # SPDX-License-Identifier: GPL-2.0 |
| dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += \ |
| socfpga_arria5_socdk.dtb \ |
| socfpga_arria10_chameleonv3.dtb \ |
| socfpga_arria10_mercury_aa1_pe1_emmc.dtb \ |
| socfpga_arria10_mercury_aa1_pe1_qspi.dtb \ |
| socfpga_arria10_mercury_aa1_pe1_sdmmc.dtb \ |
| socfpga_arria10_mercury_aa1_pe3_emmc.dtb \ |
| socfpga_arria10_mercury_aa1_pe3_qspi.dtb \ |
| socfpga_arria10_mercury_aa1_pe3_sdmmc.dtb \ |
| socfpga_arria10_mercury_aa1_st1_emmc.dtb \ |
| socfpga_arria10_mercury_aa1_st1_qspi.dtb \ |
| socfpga_arria10_mercury_aa1_st1_sdmmc.dtb \ |
| socfpga_cyclone5_mercury_sa1_pe1_emmc.dtb \ |
| socfpga_cyclone5_mercury_sa1_pe1_qspi.dtb \ |
| socfpga_cyclone5_mercury_sa1_pe1_sdmmc.dtb \ |
| socfpga_cyclone5_mercury_sa1_pe3_emmc.dtb \ |
| socfpga_cyclone5_mercury_sa1_pe3_qspi.dtb \ |
| socfpga_cyclone5_mercury_sa1_pe3_sdmmc.dtb \ |
| socfpga_cyclone5_mercury_sa1_st1_emmc.dtb \ |
| socfpga_cyclone5_mercury_sa1_st1_qspi.dtb \ |
| socfpga_cyclone5_mercury_sa1_st1_sdmmc.dtb \ |
| socfpga_cyclone5_mercury_sa2_pe1_qspi.dtb \ |
| socfpga_cyclone5_mercury_sa2_pe1_sdmmc.dtb \ |
| socfpga_cyclone5_mercury_sa2_pe3_qspi.dtb \ |
| socfpga_cyclone5_mercury_sa2_pe3_sdmmc.dtb \ |
| socfpga_cyclone5_mercury_sa2_st1_qspi.dtb \ |
| socfpga_cyclone5_mercury_sa2_st1_sdmmc.dtb \ |
| socfpga_arria10_socdk_nand.dtb \ |
| socfpga_arria10_socdk_qspi.dtb \ |
| socfpga_arria10_socdk_sdmmc.dtb \ |
| socfpga_cyclone5_chameleon96.dtb \ |
| socfpga_cyclone5_mcvevk.dtb \ |
| socfpga_cyclone5_socdk.dtb \ |
| socfpga_cyclone5_de0_nano_soc.dtb \ |
| socfpga_cyclone5_de10nano.dtb \ |
| socfpga_cyclone5_sockit.dtb \ |
| socfpga_cyclone5_socrates.dtb \ |
| socfpga_cyclone5_sodia.dtb \ |
| socfpga_cyclone5_vining_fpga.dtb \ |
| socfpga_vt.dtb |
