arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1.dtsi

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright 2022 Google LLC
 */

#include "socfpga_arria10.dtsi"

/ {

	model = "Enclustra Mercury+ AA1";
	compatible = "enclustra,mercury-aa1",
		     "altr,socfpga-arria10", "altr,socfpga";

	aliases {
		ethernet0 = &gmac0;
		serial1 = &uart1;
		spi0 = &qspi;
	};

	memory@0 {
		name = "memory";
		device_type = "memory";
		reg = <0x0 0x80000000>; /* 2GB */
	};

	chosen {
		stdout-path = "serial1:115200n8";
	};

	/* Adjusted the i2c labels to use generic base-board dtsi files for
	 * Enclustra Arria10 and Cyclone5 SoMs.
	 *
	 * The set of i2c0 and i2c1 labels defined in socfpga_cyclone5.dtsi and in
	 * socfpga_arria10.dtsi do not allow for using the same base-board .dtsi
	 * fragments. Thus define generic labels here to match the correct i2c
	 * bus in a generic base-board .dtsi file.
	 */
	soc {
		i2c_encl: i2c@ffc02300 {
		};
		i2c_encl_fpga: i2c@ffc02200 {
		};
	};
};

&i2c_encl {
	status = "okay";
	i2c-sda-hold-time-ns = <300>;
	clock-frequency = <100000>;

	atsha204a: crypto@64 {
		compatible = "atmel,atsha204a";
		reg = <0x64>;
	};

	isl12022: rtc@6f {
		compatible = "isil,isl12022";
		reg = <0x6f>;
	};
};

&i2c_encl_fpga {
	i2c-sda-hold-time-ns = <300>;
	status = "disabled";
};

&gmac0 {
	status = "okay";
	phy-mode = "rgmii-id";
	phy-addr = <0xffffffff>; /* probe for phy addr */
	max-frame-size = <3800>;
	phy-handle = <&phy3>;

	/delete-property/ mac-address;

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "snps,dwmac-mdio";
		phy3: ethernet-phy@3 {
			reg = <3>;

			/* Add 2ns RX clock delay (1.2ns + 0.78ns)*/
			rxc-skew-ps = <1680>; /* 780ps */
			rxd0-skew-ps = <420>; /* 0ps */
			rxd1-skew-ps = <420>; /* 0ps */
			rxd2-skew-ps = <420>; /* 0ps */
			rxd3-skew-ps = <420>; /* 0ps */
			rxdv-skew-ps = <420>; /* 0ps */

			/* Add 1.38ns TX clock delay (0.96ns + 0.42ns)*/
			txc-skew-ps = <1860>; /* 960ps */
			txd0-skew-ps = <0>; /* -420ps */
			txd1-skew-ps = <0>; /* -420ps */
			txd2-skew-ps = <0>; /* -420ps */
			txd3-skew-ps = <0>; /* -420ps */
			txen-skew-ps = <0>; /* -420ps */
		};
	};
};

&gpio0 {
	status = "okay";
};

&gpio1 {
	status = "okay";
};

&gpio2 {
	status = "okay";
};

&uart0 {
	status = "disabled";
};

&uart1 {
	status = "okay";
};

/* Following mappings are taken from arria10 socdk dts */
&mmc {
	status = "okay";
	cap-sd-highspeed;
	broken-cd;
	bus-width = <4>;
	clk-phase-sd-hs = <0>, <135>;
};

&osc1 {
	clock-frequency = <33330000>;
};

&eccmgr {
	sdmmca-ecc@ff8c2c00 {
		compatible = "altr,socfpga-sdmmc-ecc";
		reg = <0xff8c2c00 0x400>;
		altr,ecc-parent = <&mmc>;
		interrupts = <15 IRQ_TYPE_LEVEL_HIGH>,
					 <47 IRQ_TYPE_LEVEL_HIGH>,
					 <16 IRQ_TYPE_LEVEL_HIGH>,
					 <48 IRQ_TYPE_LEVEL_HIGH>;
	};
};

&qspi {
	status = "okay";
	flash0: flash@0 {
		u-boot,dm-pre-reloc;
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "jedec,spi-nor";
		reg = <0>;

		spi-rx-bus-width = <4>;
		spi-tx-bus-width = <4>;
		spi-max-frequency = <10000000>;

		cdns,read-delay = <4>;
		cdns,tshsl-ns = <50>;
		cdns,tsd2d-ns = <50>;
		cdns,tchsh-ns = <4>;
		cdns,tslch-ns = <4>;

		partition@raw {
			label = "Flash Raw";
			reg = <0x0 0x4000000>;
		};
	};
};

&watchdog1 {
	status = "disabled";
};

&usb0 {
	status = "okay";
	dr_mode = "host";
};