arch/arm/boot/dts/st/stm32mp153.dtsi

// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
 * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
 * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
 */

#include "stm32mp151.dtsi"

/ {
	cpus {
		cpu1: cpu@1 {
			compatible = "arm,cortex-a7";
			clock-frequency = <650000000>;
			device_type = "cpu";
			reg = <1>;
		};
	};

	arm-pmu {
		interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-affinity = <&cpu0>, <&cpu1>;
	};

	timer {
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
	};
};

&cs_funnel {
	in-ports {
		port@2 {
			reg = <2>;
			funnel_in_port2: endpoint {
				remote-endpoint = <&etm1_out>;
			};
		};
	};
};

&dbg_bus {
	cs_cti_cpu1: cti@500d9000 {
		compatible = "arm,coresight-cti", "arm,primecell";
		reg = <0x500d9000 0x1000>;
		clocks = <&rcc CK_DBG>;
		clock-names = "apb_pclk";
		#address-cells = <1>;
		#size-cells = <0>;
		access-controllers = <&dbg_bus 0>;
		status = "disabled";

		trig-conns@0 {
			reg = <0>;
			arm,trig-in-sigs = <0 4 5>;
			arm,trig-in-types = <PE_DBGTRIGGER
					     GEN_IO
					     GEN_IO>;
			arm,trig-out-sigs = <0 7>;
			arm,trig-out-types = <PE_EDBGREQ
					      PE_DBGRESTART>;
			cpu = <&cpu1>;
		};

		trig-conns@2 {
			reg = <2>;
			arm,trig-in-sigs = <2 3 6>;
			arm,trig-in-types = <ETM_EXTOUT
					     ETM_EXTOUT
					     ETM_EXTOUT>;
			arm,trig-out-sigs = <1 2 3 4>;
			arm,trig-out-types = <ETM_EXTIN
					      ETM_EXTIN
					      ETM_EXTIN
					      ETM_EXTIN>;
			arm,cs-dev-assoc = <&cs_etm1>;
		};
	};

	cs_etm1: etm@500dd000 {
		compatible = "arm,coresight-etm3x", "arm,primecell";
		reg = <0x500dd000 0x1000>;
		cpu = <&cpu1>;
		clocks = <&rcc CK_DBG>, <&rcc CK_TRACE>;
		clock-names = "apb_pclk", "atclk";
		access-controllers = <&dbg_bus 0>;
		status = "disabled";

		out-ports {
			port {
				etm1_out: endpoint {
					remote-endpoint = <&funnel_in_port2>;
				};
			};
		};
	};
};

&etzpc {
	m_can1: can@4400e000 {
		compatible = "bosch,m_can";
		reg = <0x4400e000 0x400>, <0x44011000 0x1400>;
		reg-names = "m_can", "message_ram";
		interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "int0", "int1";
		clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
		clock-names = "hclk", "cclk";
		resets = <&rcc FDCAN_R>;
		bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>;
		access-controllers = <&etzpc 62>;
		status = "disabled";
	};

	m_can2: can@4400f000 {
		compatible = "bosch,m_can";
		reg = <0x4400f000 0x400>, <0x44011000 0x2800>;
		reg-names = "m_can", "message_ram";
		interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "int0", "int1";
		clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
		clock-names = "hclk", "cclk";
		resets = <&rcc FDCAN_R>;
		bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
		access-controllers = <&etzpc 62>;
		status = "disabled";
	};
};