| # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| %YAML 1.2 |
| --- |
| $id: http://devicetree.org/schemas/fpga/altr,socfpga-hps2fpga-bridge.yaml# |
| $schema: http://devicetree.org/meta-schemas/core.yaml# |
| |
| title: Altera FPGA/HPS Bridge |
| |
| maintainers: |
| - Xu Yilun <yilun.xu@intel.com> |
| |
| allOf: |
| - $ref: fpga-bridge.yaml# |
| |
| properties: |
| compatible: |
| enum: |
| - altr,socfpga-lwhps2fpga-bridge |
| - altr,socfpga-hps2fpga-bridge |
| - altr,socfpga-fpga2hps-bridge |
| |
| reg: |
| maxItems: 1 |
| |
| resets: |
| maxItems: 1 |
| |
| clocks: |
| maxItems: 1 |
| |
| required: |
| - compatible |
| - reg |
| - clocks |
| - resets |
| |
| unevaluatedProperties: false |
| |
| examples: |
| - | |
| #include <dt-bindings/reset/altr,rst-mgr.h> |
| |
| fpga-bridge@ff400000 { |
| compatible = "altr,socfpga-lwhps2fpga-bridge"; |
| reg = <0xff400000 0x100000>; |
| bridge-enable = <0>; |
| clocks = <&l4_main_clk>; |
| resets = <&rst LWHPS2FPGA_RESET>; |
| }; |