Documentation/devicetree/bindings/mtd/atmel-nand.txt - linux - Git at Google

 Atmel NAND flash controller bindings

 The NAND flash controller node should be defined under the EBI bus (see
 Documentation/devicetree/bindings/memory-controllers/atmel,ebi.txt).
 One or several NAND devices can be defined under this NAND controller.
 The NAND controller might be connected to an ECC engine.

 * NAND controller bindings:

 Required properties:
 - compatible: should be one of the following
 	"atmel,at91rm9200-nand-controller"
 	"atmel,at91sam9260-nand-controller"
 	"atmel,at91sam9261-nand-controller"
 	"atmel,at91sam9g45-nand-controller"
 	"atmel,sama5d3-nand-controller"
 	"microchip,sam9x60-nand-controller"
 - ranges: empty ranges property to forward EBI ranges definitions.
 - #address-cells: should be set to 2.
 - #size-cells: should be set to 1.
 - atmel,nfc-io: phandle to the NFC IO block. Only required for sama5d3
 		controllers.
 - atmel,nfc-sram: phandle to the NFC SRAM block. Only required for sama5d3
 		  controllers.

 Optional properties:
 - ecc-engine: phandle to the PMECC block. Only meaningful if the SoC embeds
 	      a PMECC engine.

 * NAND device/chip bindings:

 Required properties:
 - reg: describes the CS lines assigned to the NAND device. If the NAND device
        exposes multiple CS lines (multi-dies chips), your reg property will
        contain X tuples of 3 entries.
        1st entry: the CS line this NAND chip is connected to
        2nd entry: the base offset of the memory region assigned to this
 		  device (always 0)
        3rd entry: the memory region size (always 0x800000)

 Optional properties:
 - rb-gpios: the GPIO(s) used to check the Ready/Busy status of the NAND.
 - cs-gpios: the GPIO(s) used to control the CS line.
 - det-gpios: the GPIO used to detect if a Smartmedia Card is present.
 - atmel,rb: an integer identifying the native Ready/Busy pin. Only meaningful
 	    on sama5 SoCs.

 All generic properties are described in the generic yaml files under
 Documentation/devicetree/bindings/mtd/.

 * ECC engine (PMECC) bindings:

 Required properties:
 - compatible: should be one of the following
 	"atmel,at91sam9g45-pmecc"
 	"atmel,sama5d4-pmecc"
 	"atmel,sama5d2-pmecc"
 	"microchip,sam9x60-pmecc"
 	"microchip,sam9x7-pmecc", "atmel,at91sam9g45-pmecc"
 - reg: should contain 2 register ranges. The first one is pointing to the PMECC
        block, and the second one to the PMECC_ERRLOC block.

 * SAMA5 NFC I/O bindings:

 SAMA5 SoCs embed an advanced NAND controller logic to automate READ/WRITE page
 operations. This interface to this logic is placed in a separate I/O range and
 should thus have its own DT node.

 - compatible: should be "atmel,sama5d3-nfc-io", "syscon".
 - reg: should contain the I/O range used to interact with the NFC logic.

 Example:

 	nfc_io: nfc-io@70000000 {
 		compatible = "atmel,sama5d3-nfc-io", "syscon";
 		reg = <0x70000000 0x8000000>;
 	};

 	pmecc: ecc-engine@ffffc070 {
 		compatible = "atmel,at91sam9g45-pmecc";
                 reg = <0xffffc070 0x490>,
                       <0xffffc500 0x100>;
 	};

 	ebi: ebi@10000000 {
 		compatible = "atmel,sama5d3-ebi";
 		#address-cells = <2>;
 		#size-cells = <1>;
 		atmel,smc = <&hsmc>;
 		reg = <0x10000000 0x10000000
 		       0x40000000 0x30000000>;
 		ranges = <0x0 0x0 0x10000000 0x10000000
 			  0x1 0x0 0x40000000 0x10000000
 			  0x2 0x0 0x50000000 0x10000000
 			  0x3 0x0 0x60000000 0x10000000>;
 		clocks = <&mck>;

                 nand_controller: nand-controller {
 			compatible = "atmel,sama5d3-nand-controller";
 			atmel,nfc-sram = <&nfc_sram>;
 			atmel,nfc-io = <&nfc_io>;
 			ecc-engine = <&pmecc>;
 			#address-cells = <2>;
 			#size-cells = <1>;
 			ranges;

 			nand@3 {
 				reg = <0x3 0x0 0x800000>;
 				atmel,rb = <0>;

 				/*
 				 * Put generic NAND/MTD properties and
 				 * subnodes here.
 				 */
 			};
 		};
 	};

 -----------------------------------------------------------------------

 Deprecated bindings (should not be used in new device trees):

 Required properties:
 - compatible: The possible values are:
 	"atmel,at91rm9200-nand"
 	"atmel,sama5d2-nand"
 	"atmel,sama5d4-nand"
 - reg : should specify localbus address and size used for the chip,
 	and hardware ECC controller if available.
 	If the hardware ECC is PMECC, it should contain address and size for
 	PMECC and PMECC Error Location controller.
 	The PMECC lookup table address and size in ROM is optional. If not
 	specified, driver will build it in runtime.
 - atmel,nand-addr-offset : offset for the address latch.
 - atmel,nand-cmd-offset : offset for the command latch.
 - #address-cells, #size-cells : Must be present if the device has sub-nodes
   representing partitions.

 - gpios : specifies the gpio pins to control the NAND device. detect is an
   optional gpio and may be set to 0 if not present.

 Optional properties:
 - atmel,nand-has-dma : boolean to support dma transfer for nand read/write.
 - nand-ecc-mode : String, operation mode of the NAND ecc mode, soft by default.
   Supported values are: "none", "soft", "hw", "hw_syndrome", "hw_oob_first",
   "soft_bch".
 - atmel,has-pmecc : boolean to enable Programmable Multibit ECC hardware,
   capable of BCH encoding and decoding, on devices where it is present.
 - atmel,pmecc-cap : error correct capability for Programmable Multibit ECC
   Controller. Supported values are: 2, 4, 8, 12, 24. If the compatible string
   is "atmel,sama5d2-nand", 32 is also valid.
 - atmel,pmecc-sector-size : sector size for ECC computation. Supported values
   are: 512, 1024.
 - atmel,pmecc-lookup-table-offset : includes two offsets of lookup table in ROM
   for different sector size. First one is for sector size 512, the next is for
   sector size 1024. If not specified, driver will build the table in runtime.
 - nand-bus-width : 8 or 16 bus width if not present 8
 - nand-on-flash-bbt: boolean to enable on flash bbt option if not present false

 Nand Flash Controller(NFC) is an optional sub-node
 Required properties:
 - compatible : "atmel,sama5d3-nfc".
 - reg : should specify the address and size used for NFC command registers,
         NFC registers and NFC SRAM. NFC SRAM address and size can be absent
         if don't want to use it.
 - clocks: phandle to the peripheral clock
 Optional properties:
 - atmel,write-by-sram: boolean to enable NFC write by SRAM.

 Examples:
 nand0: nand@40000000,0 {
 	compatible = "atmel,at91rm9200-nand";
 	#address-cells = <1>;
 	#size-cells = <1>;
 	reg = <0x40000000 0x10000000
 	       0xffffe800 0x200
 	      >;
 	atmel,nand-addr-offset = <21>;	/* ale */
 	atmel,nand-cmd-offset = <22>;	/* cle */
 	nand-on-flash-bbt;
 	nand-ecc-mode = "soft";
 	gpios = <&pioC 13 0	/* rdy */
 		 &pioC 14 0 	/* nce */
 		 0		/* cd */
 		>;
 	partition@0 {
 		...
 	};
 };

 /* for PMECC supported chips */
 nand0: nand@40000000 {
 	compatible = "atmel,at91rm9200-nand";
 	#address-cells = <1>;
 	#size-cells = <1>;
 	reg = < 0x40000000 0x10000000	/* bus addr & size */
 		0xffffe000 0x00000600	/* PMECC addr & size */
 		0xffffe600 0x00000200	/* PMECC ERRLOC addr & size */
 		0x00100000 0x00100000	/* ROM addr & size */
 		>;
 	atmel,nand-addr-offset = <21>;	/* ale */
 	atmel,nand-cmd-offset = <22>;	/* cle */
 	nand-on-flash-bbt;
 	nand-ecc-mode = "hw";
 	atmel,has-pmecc;	/* enable PMECC */
 	atmel,pmecc-cap = <2>;
 	atmel,pmecc-sector-size = <512>;
 	atmel,pmecc-lookup-table-offset = <0x8000 0x10000>;
 	gpios = <&pioD 5 0	/* rdy */
 		 &pioD 4 0	/* nce */
 		 0		/* cd */
 		>;
 	partition@0 {
 		...
 	};
 };

 /* for NFC supported chips */
 nand0: nand@40000000 {
 	compatible = "atmel,at91rm9200-nand";
 	#address-cells = <1>;
 	#size-cells = <1>;
 	ranges;
         ...
         nfc@70000000 {
 		compatible = "atmel,sama5d3-nfc";
 		#address-cells = <1>;
 		#size-cells = <1>;
 		clocks = <&hsmc_clk>
 		reg = <
 			0x70000000 0x10000000	/* NFC Command Registers */
 			0xffffc000 0x00000070	/* NFC HSMC regs */
 			0x00200000 0x00100000	/* NFC SRAM banks */
 		>;
 	};
 };
	Atmel NAND flash controller bindings

	The NAND flash controller node should be defined under the EBI bus (see
	Documentation/devicetree/bindings/memory-controllers/atmel,ebi.txt).
	One or several NAND devices can be defined under this NAND controller.
	The NAND controller might be connected to an ECC engine.

	* NAND controller bindings:

	Required properties:
	- compatible: should be one of the following
	"atmel,at91rm9200-nand-controller"
	"atmel,at91sam9260-nand-controller"
	"atmel,at91sam9261-nand-controller"
	"atmel,at91sam9g45-nand-controller"
	"atmel,sama5d3-nand-controller"
	"microchip,sam9x60-nand-controller"
	- ranges: empty ranges property to forward EBI ranges definitions.
	- #address-cells: should be set to 2.
	- #size-cells: should be set to 1.
	- atmel,nfc-io: phandle to the NFC IO block. Only required for sama5d3
	controllers.
	- atmel,nfc-sram: phandle to the NFC SRAM block. Only required for sama5d3
	controllers.

	Optional properties:
	- ecc-engine: phandle to the PMECC block. Only meaningful if the SoC embeds
	a PMECC engine.

	* NAND device/chip bindings:

	Required properties:
	- reg: describes the CS lines assigned to the NAND device. If the NAND device
	exposes multiple CS lines (multi-dies chips), your reg property will
	contain X tuples of 3 entries.
	1st entry: the CS line this NAND chip is connected to
	2nd entry: the base offset of the memory region assigned to this
	device (always 0)
	3rd entry: the memory region size (always 0x800000)

	Optional properties:
	- rb-gpios: the GPIO(s) used to check the Ready/Busy status of the NAND.
	- cs-gpios: the GPIO(s) used to control the CS line.
	- det-gpios: the GPIO used to detect if a Smartmedia Card is present.
	- atmel,rb: an integer identifying the native Ready/Busy pin. Only meaningful
	on sama5 SoCs.

	All generic properties are described in the generic yaml files under
	Documentation/devicetree/bindings/mtd/.

	* ECC engine (PMECC) bindings:

	Required properties:
	- compatible: should be one of the following
	"atmel,at91sam9g45-pmecc"
	"atmel,sama5d4-pmecc"
	"atmel,sama5d2-pmecc"
	"microchip,sam9x60-pmecc"
	"microchip,sam9x7-pmecc", "atmel,at91sam9g45-pmecc"
	- reg: should contain 2 register ranges. The first one is pointing to the PMECC
	block, and the second one to the PMECC_ERRLOC block.

	* SAMA5 NFC I/O bindings:

	SAMA5 SoCs embed an advanced NAND controller logic to automate READ/WRITE page
	operations. This interface to this logic is placed in a separate I/O range and
	should thus have its own DT node.

	- compatible: should be "atmel,sama5d3-nfc-io", "syscon".
	- reg: should contain the I/O range used to interact with the NFC logic.

	Example:

	nfc_io: nfc-io@70000000 {
	compatible = "atmel,sama5d3-nfc-io", "syscon";
	reg = <0x70000000 0x8000000>;
	};

	pmecc: ecc-engine@ffffc070 {
	compatible = "atmel,at91sam9g45-pmecc";
	reg = <0xffffc070 0x490>,
	<0xffffc500 0x100>;
	};

	ebi: ebi@10000000 {
	compatible = "atmel,sama5d3-ebi";
	#address-cells = <2>;
	#size-cells = <1>;
	atmel,smc = <&hsmc>;
	reg = <0x10000000 0x10000000
	0x40000000 0x30000000>;
	ranges = <0x0 0x0 0x10000000 0x10000000
	0x1 0x0 0x40000000 0x10000000
	0x2 0x0 0x50000000 0x10000000
	0x3 0x0 0x60000000 0x10000000>;
	clocks = <&mck>;

	nand_controller: nand-controller {
	compatible = "atmel,sama5d3-nand-controller";
	atmel,nfc-sram = <&nfc_sram>;
	atmel,nfc-io = <&nfc_io>;
	ecc-engine = <&pmecc>;
	#address-cells = <2>;
	#size-cells = <1>;
	ranges;

	nand@3 {
	reg = <0x3 0x0 0x800000>;
	atmel,rb = <0>;

	/*
	* Put generic NAND/MTD properties and
	* subnodes here.
	*/
	};
	};
	};

	-----------------------------------------------------------------------

	Deprecated bindings (should not be used in new device trees):

	Required properties:
	- compatible: The possible values are:
	"atmel,at91rm9200-nand"
	"atmel,sama5d2-nand"
	"atmel,sama5d4-nand"
	- reg : should specify localbus address and size used for the chip,
	and hardware ECC controller if available.
	If the hardware ECC is PMECC, it should contain address and size for
	PMECC and PMECC Error Location controller.
	The PMECC lookup table address and size in ROM is optional. If not
	specified, driver will build it in runtime.
	- atmel,nand-addr-offset : offset for the address latch.
	- atmel,nand-cmd-offset : offset for the command latch.
	- #address-cells, #size-cells : Must be present if the device has sub-nodes
	representing partitions.

	- gpios : specifies the gpio pins to control the NAND device. detect is an
	optional gpio and may be set to 0 if not present.

	Optional properties:
	- atmel,nand-has-dma : boolean to support dma transfer for nand read/write.
	- nand-ecc-mode : String, operation mode of the NAND ecc mode, soft by default.
	Supported values are: "none", "soft", "hw", "hw_syndrome", "hw_oob_first",
	"soft_bch".
	- atmel,has-pmecc : boolean to enable Programmable Multibit ECC hardware,
	capable of BCH encoding and decoding, on devices where it is present.
	- atmel,pmecc-cap : error correct capability for Programmable Multibit ECC
	Controller. Supported values are: 2, 4, 8, 12, 24. If the compatible string
	is "atmel,sama5d2-nand", 32 is also valid.
	- atmel,pmecc-sector-size : sector size for ECC computation. Supported values
	are: 512, 1024.
	- atmel,pmecc-lookup-table-offset : includes two offsets of lookup table in ROM
	for different sector size. First one is for sector size 512, the next is for
	sector size 1024. If not specified, driver will build the table in runtime.
	- nand-bus-width : 8 or 16 bus width if not present 8
	- nand-on-flash-bbt: boolean to enable on flash bbt option if not present false

	Nand Flash Controller(NFC) is an optional sub-node
	Required properties:
	- compatible : "atmel,sama5d3-nfc".
	- reg : should specify the address and size used for NFC command registers,
	NFC registers and NFC SRAM. NFC SRAM address and size can be absent
	if don't want to use it.
	- clocks: phandle to the peripheral clock
	Optional properties:
	- atmel,write-by-sram: boolean to enable NFC write by SRAM.

	Examples:
	nand0: nand@40000000,0 {
	compatible = "atmel,at91rm9200-nand";
	#address-cells = <1>;
	#size-cells = <1>;
	reg = <0x40000000 0x10000000
	0xffffe800 0x200
	>;
	atmel,nand-addr-offset = <21>; /* ale */
	atmel,nand-cmd-offset = <22>; /* cle */
	nand-on-flash-bbt;
	nand-ecc-mode = "soft";
	gpios = <&pioC 13 0 /* rdy */
	&pioC 14 0 /* nce */
	0 /* cd */
	>;
	partition@0 {
	...
	};
	};

	/* for PMECC supported chips */
	nand0: nand@40000000 {
	compatible = "atmel,at91rm9200-nand";
	#address-cells = <1>;
	#size-cells = <1>;
	reg = < 0x40000000 0x10000000 /* bus addr & size */
	0xffffe000 0x00000600 /* PMECC addr & size */
	0xffffe600 0x00000200 /* PMECC ERRLOC addr & size */
	0x00100000 0x00100000 /* ROM addr & size */
	>;
	atmel,nand-addr-offset = <21>; /* ale */
	atmel,nand-cmd-offset = <22>; /* cle */
	nand-on-flash-bbt;
	nand-ecc-mode = "hw";
	atmel,has-pmecc; /* enable PMECC */
	atmel,pmecc-cap = <2>;
	atmel,pmecc-sector-size = <512>;
	atmel,pmecc-lookup-table-offset = <0x8000 0x10000>;
	gpios = <&pioD 5 0 /* rdy */
	&pioD 4 0 /* nce */
	0 /* cd */
	>;
	partition@0 {
	...
	};
	};

	/* for NFC supported chips */
	nand0: nand@40000000 {
	compatible = "atmel,at91rm9200-nand";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;
	...
	nfc@70000000 {
	compatible = "atmel,sama5d3-nfc";
	#address-cells = <1>;
	#size-cells = <1>;
	clocks = <&hsmc_clk>
	reg = <
	0x70000000 0x10000000 /* NFC Command Registers */
	0xffffc000 0x00000070 /* NFC HSMC regs */
	0x00200000 0x00100000 /* NFC SRAM banks */
	>;
	};
	};