| # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) |
| %YAML 1.2 |
| --- |
| $id: http://devicetree.org/schemas/sound/snps,designware-i2s.yaml# |
| $schema: http://devicetree.org/meta-schemas/core.yaml# |
| |
| title: DesignWare I2S controller |
| |
| maintainers: |
| - Jose Abreu <joabreu@synopsys.com> |
| |
| properties: |
| compatible: |
| oneOf: |
| - items: |
| - const: canaan,k210-i2s |
| - const: snps,designware-i2s |
| - enum: |
| - snps,designware-i2s |
| - starfive,jh7110-i2stx0 |
| - starfive,jh7110-i2stx1 |
| - starfive,jh7110-i2srx |
| |
| reg: |
| maxItems: 1 |
| |
| interrupts: |
| description: | |
| The interrupt line number for the I2S controller. Add this |
| parameter if the I2S controller that you are using does not |
| support DMA. |
| maxItems: 1 |
| |
| clocks: |
| items: |
| - description: Sampling rate reference clock |
| - description: APB clock |
| - description: Audio master clock |
| - description: Inner audio master clock source |
| - description: External audio master clock source |
| - description: Bit clock |
| - description: Left/right channel clock |
| - description: External bit clock |
| - description: External left/right channel clock |
| minItems: 1 |
| |
| clock-names: |
| items: |
| - const: i2sclk |
| - const: apb |
| - const: mclk |
| - const: mclk_inner |
| - const: mclk_ext |
| - const: bclk |
| - const: lrck |
| - const: bclk_ext |
| - const: lrck_ext |
| minItems: 1 |
| |
| resets: |
| items: |
| - description: Optional controller resets |
| - description: controller reset of Sampling rate |
| minItems: 1 |
| |
| dmas: |
| items: |
| - description: TX DMA Channel |
| - description: RX DMA Channel |
| minItems: 1 |
| |
| dma-names: |
| items: |
| - const: tx |
| - const: rx |
| minItems: 1 |
| |
| starfive,syscon: |
| $ref: /schemas/types.yaml#/definitions/phandle-array |
| items: |
| - items: |
| - description: phandle to System Register Controller sys_syscon node. |
| - description: I2S-rx enabled control offset of SYS_SYSCONSAIF__SYSCFG register. |
| - description: I2S-rx enabled control mask |
| description: |
| The phandle to System Register Controller syscon node and the I2S-rx(ADC) |
| enabled control offset and mask of SYS_SYSCONSAIF__SYSCFG register. |
| |
| allOf: |
| - $ref: dai-common.yaml# |
| - if: |
| properties: |
| compatible: |
| contains: |
| const: canaan,k210-i2s |
| then: |
| properties: |
| "#sound-dai-cells": |
| const: 1 |
| else: |
| properties: |
| "#sound-dai-cells": |
| const: 0 |
| - if: |
| properties: |
| compatible: |
| contains: |
| const: snps,designware-i2s |
| then: |
| properties: |
| clocks: |
| maxItems: 1 |
| clock-names: |
| maxItems: 1 |
| resets: |
| maxItems: 1 |
| else: |
| properties: |
| resets: |
| minItems: 2 |
| maxItems: 2 |
| - if: |
| properties: |
| compatible: |
| contains: |
| const: starfive,jh7110-i2stx0 |
| then: |
| properties: |
| clocks: |
| minItems: 5 |
| maxItems: 5 |
| clock-names: |
| minItems: 5 |
| maxItems: 5 |
| required: |
| - resets |
| - if: |
| properties: |
| compatible: |
| contains: |
| const: starfive,jh7110-i2stx1 |
| then: |
| properties: |
| clocks: |
| minItems: 9 |
| maxItems: 9 |
| clock-names: |
| minItems: 9 |
| maxItems: 9 |
| required: |
| - resets |
| - if: |
| properties: |
| compatible: |
| contains: |
| const: starfive,jh7110-i2srx |
| then: |
| properties: |
| clocks: |
| minItems: 9 |
| maxItems: 9 |
| clock-names: |
| minItems: 9 |
| maxItems: 9 |
| required: |
| - resets |
| - starfive,syscon |
| else: |
| properties: |
| starfive,syscon: false |
| |
| required: |
| - compatible |
| - reg |
| - clocks |
| - clock-names |
| |
| oneOf: |
| - required: |
| - dmas |
| - dma-names |
| - required: |
| - interrupts |
| |
| unevaluatedProperties: false |
| |
| examples: |
| - | |
| soc_i2s: i2s@7ff90000 { |
| compatible = "snps,designware-i2s"; |
| reg = <0x7ff90000 0x1000>; |
| clocks = <&scpi_i2sclk 0>; |
| clock-names = "i2sclk"; |
| #sound-dai-cells = <0>; |
| dmas = <&dma0 5>; |
| dma-names = "tx"; |
| }; |