| # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| # Copyright (C) 2022-2023 Amlogic, Inc. All rights reserved |
| %YAML 1.2 |
| --- |
| $id: http://devicetree.org/schemas/clock/amlogic,c3-peripherals-clkc.yaml# |
| $schema: http://devicetree.org/meta-schemas/core.yaml# |
| |
| title: Amlogic C3 series Peripheral Clock Controller |
| |
| maintainers: |
| - Neil Armstrong <neil.armstrong@linaro.org> |
| - Jerome Brunet <jbrunet@baylibre.com> |
| - Xianwei Zhao <xianwei.zhao@amlogic.com> |
| - Chuan Liu <chuan.liu@amlogic.com> |
| |
| properties: |
| compatible: |
| const: amlogic,c3-peripherals-clkc |
| |
| reg: |
| maxItems: 1 |
| |
| clocks: |
| minItems: 16 |
| items: |
| - description: input oscillator (usually at 24MHz) |
| - description: input oscillators multiplexer |
| - description: input fix pll |
| - description: input fclk div 2 |
| - description: input fclk div 2p5 |
| - description: input fclk div 3 |
| - description: input fclk div 4 |
| - description: input fclk div 5 |
| - description: input fclk div 7 |
| - description: input gp0 pll |
| - description: input gp1 pll |
| - description: input hifi pll |
| - description: input sys clk |
| - description: input axi clk |
| - description: input sys pll div 16 |
| - description: input cpu clk div 16 |
| - description: input pad clock for rtc clk (optional) |
| |
| clock-names: |
| minItems: 16 |
| items: |
| - const: xtal_24m |
| - const: oscin |
| - const: fix |
| - const: fdiv2 |
| - const: fdiv2p5 |
| - const: fdiv3 |
| - const: fdiv4 |
| - const: fdiv5 |
| - const: fdiv7 |
| - const: gp0 |
| - const: gp1 |
| - const: hifi |
| - const: sysclk |
| - const: axiclk |
| - const: sysplldiv16 |
| - const: cpudiv16 |
| - const: pad_osc |
| |
| "#clock-cells": |
| const: 1 |
| |
| required: |
| - compatible |
| - reg |
| - clocks |
| - clock-names |
| - "#clock-cells" |
| |
| additionalProperties: false |
| |
| examples: |
| - | |
| apb { |
| #address-cells = <2>; |
| #size-cells = <2>; |
| |
| clock-controller@0 { |
| compatible = "amlogic,c3-peripherals-clkc"; |
| reg = <0x0 0x0 0x0 0x49c>; |
| #clock-cells = <1>; |
| clocks = <&xtal_24m>, |
| <&scmi_clk 8>, |
| <&scmi_clk 12>, |
| <&clkc_pll 3>, |
| <&clkc_pll 5>, |
| <&clkc_pll 7>, |
| <&clkc_pll 9>, |
| <&clkc_pll 11>, |
| <&clkc_pll 13>, |
| <&clkc_pll 15>, |
| <&scmi_clk 13>, |
| <&clkc_pll 17>, |
| <&scmi_clk 9>, |
| <&scmi_clk 10>, |
| <&scmi_clk 14>, |
| <&scmi_clk 15>; |
| clock-names = "xtal_24m", |
| "oscin", |
| "fix", |
| "fdiv2", |
| "fdiv2p5", |
| "fdiv3", |
| "fdiv4", |
| "fdiv5", |
| "fdiv7", |
| "gp0", |
| "gp1", |
| "hifi", |
| "sysclk", |
| "axiclk", |
| "sysplldiv16", |
| "cpudiv16"; |
| }; |
| }; |
