Documentation/devicetree/bindings/pci/starfive,jh7110-pcie.yaml

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/starfive,jh7110-pcie.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: StarFive JH7110 PCIe host controller

maintainers:
  - Kevin Xie <kevin.xie@starfivetech.com>

allOf:
  - $ref: plda,xpressrich3-axi-common.yaml#

properties:
  compatible:
    const: starfive,jh7110-pcie

  clocks:
    items:
      - description: NOC bus clock
      - description: Transport layer clock
      - description: AXI MST0 clock
      - description: APB clock

  clock-names:
    items:
      - const: noc
      - const: tl
      - const: axi_mst0
      - const: apb

  resets:
    items:
      - description: AXI MST0 reset
      - description: AXI SLAVE0 reset
      - description: AXI SLAVE reset
      - description: PCIE BRIDGE reset
      - description: PCIE CORE reset
      - description: PCIE APB reset

  reset-names:
    items:
      - const: mst0
      - const: slv0
      - const: slv
      - const: brg
      - const: core
      - const: apb

  starfive,stg-syscon:
    $ref: /schemas/types.yaml#/definitions/phandle-array
    description:
      The phandle to System Register Controller syscon node.

  perst-gpios:
    description: GPIO controlled connection to PERST# signal
    maxItems: 1

  phys:
    description:
      Specified PHY is attached to PCIe controller.
    maxItems: 1

required:
  - clocks
  - resets
  - starfive,stg-syscon

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/gpio/gpio.h>
    soc {
        #address-cells = <2>;
        #size-cells = <2>;

        pcie@940000000 {
            compatible = "starfive,jh7110-pcie";
            reg = <0x9 0x40000000 0x0 0x10000000>,
                  <0x0 0x2b000000 0x0 0x1000000>;
            reg-names = "cfg", "apb";
            #address-cells = <3>;
            #size-cells = <2>;
            #interrupt-cells = <1>;
            device_type = "pci";
            ranges = <0x82000000  0x0 0x30000000  0x0 0x30000000 0x0 0x08000000>,
                     <0xc3000000  0x9 0x00000000  0x9 0x00000000 0x0 0x40000000>;
            starfive,stg-syscon = <&stg_syscon>;
            bus-range = <0x0 0xff>;
            interrupt-parent = <&plic>;
            interrupts = <56>;
            interrupt-map-mask = <0x0 0x0 0x0 0x7>;
            interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc0 0x1>,
                            <0x0 0x0 0x0 0x2 &pcie_intc0 0x2>,
                            <0x0 0x0 0x0 0x3 &pcie_intc0 0x3>,
                            <0x0 0x0 0x0 0x4 &pcie_intc0 0x4>;
            msi-controller;
            clocks = <&syscrg 86>,
                     <&stgcrg 10>,
                     <&stgcrg 8>,
                     <&stgcrg 9>;
            clock-names = "noc", "tl", "axi_mst0", "apb";
            resets = <&stgcrg 11>,
                     <&stgcrg 12>,
                     <&stgcrg 13>,
                     <&stgcrg 14>,
                     <&stgcrg 15>,
                     <&stgcrg 16>;
            perst-gpios = <&gpios 26 GPIO_ACTIVE_LOW>;
            phys = <&pciephy0>;

            pcie_intc0: interrupt-controller {
                #address-cells = <0>;
                #interrupt-cells = <1>;
                interrupt-controller;
            };
        };
    };