Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/xlnx,nwl-pcie.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Xilinx NWL PCIe Root Port Bridge

maintainers:
  - Thippeswamy Havalige <thippeswamy.havalige@amd.com>

allOf:
  - $ref: /schemas/pci/pci-host-bridge.yaml#
  - $ref: /schemas/interrupt-controller/msi-controller.yaml#

properties:
  compatible:
    const: xlnx,nwl-pcie-2.11

  reg:
    items:
      - description: PCIe bridge registers location.
      - description: PCIe Controller registers location.
      - description: PCIe Configuration space region.

  reg-names:
    items:
      - const: breg
      - const: pcireg
      - const: cfg

  interrupts:
    items:
      - description: interrupt asserted when miscellaneous interrupt is received
      - description: unused interrupt(dummy)
      - description: interrupt asserted when a legacy interrupt is received
      - description: msi1 interrupt asserted when an MSI is received
      - description: msi0 interrupt asserted when an MSI is received

  interrupt-names:
    items:
      - const: misc
      - const: dummy
      - const: intx
      - const: msi1
      - const: msi0

  interrupt-map-mask:
    items:
      - const: 0
      - const: 0
      - const: 0
      - const: 7

  "#interrupt-cells":
    const: 1

  msi-parent:
    description: MSI controller the device is capable of using.

  interrupt-map:
    maxItems: 4

  phys:
    minItems: 1
    maxItems: 4
    description: One phy per logical lane, in order

  power-domains:
    maxItems: 1

  iommus:
    maxItems: 1

  dma-coherent:
    description: optional, only needed if DMA operations are coherent.

  clocks:
    maxItems: 1
    description: optional, input clock specifier.

  legacy-interrupt-controller:
    description: Interrupt controller node for handling legacy PCI interrupts.
    type: object
    properties:
      "#address-cells":
        const: 0

      "#interrupt-cells":
        const: 1

      interrupt-controller: true

    required:
      - "#address-cells"
      - "#interrupt-cells"
      - interrupt-controller

    additionalProperties: false

required:
  - compatible
  - reg
  - reg-names
  - interrupts
  - "#interrupt-cells"
  - interrupt-map
  - interrupt-map-mask
  - msi-controller
  - power-domains

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/interrupt-controller/irq.h>
    #include <dt-bindings/phy/phy.h>
    #include <dt-bindings/power/xlnx-zynqmp-power.h>
    soc {
        #address-cells = <2>;
        #size-cells = <2>;
        nwl_pcie: pcie@fd0e0000 {
            compatible = "xlnx,nwl-pcie-2.11";
            reg = <0x0 0xfd0e0000 0x0 0x1000>,
                  <0x0 0xfd480000 0x0 0x1000>,
                  <0x80 0x00000000 0x0 0x10000000>;
            reg-names = "breg", "pcireg", "cfg";
            ranges = <0x02000000 0x0 0xe0000000 0x0 0xe0000000 0x0 0x10000000>,
                     <0x43000000 0x00000006 0x0 0x00000006 0x0 0x00000002 0x0>;
            #address-cells = <3>;
            #size-cells = <2>;
            #interrupt-cells = <1>;
            msi-controller;
            device_type = "pci";
            interrupt-parent = <&gic>;
            interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 116 IRQ_TYPE_EDGE_RISING>,
                         <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 115 IRQ_TYPE_EDGE_RISING>,
                         <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
            interrupt-names = "misc", "dummy", "intx", "msi1", "msi0";
            interrupt-map-mask = <0x0 0x0 0x0 0x7>;
            interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,
                            <0x0 0x0 0x0 0x2 &pcie_intc 0x2>,
                            <0x0 0x0 0x0 0x3 &pcie_intc 0x3>,
                            <0x0 0x0 0x0 0x4 &pcie_intc 0x4>;
            msi-parent = <&nwl_pcie>;
            phys = <&psgtr 0 PHY_TYPE_PCIE 0 0>;
            power-domains = <&zynqmp_firmware PD_PCIE>;
            iommus = <&smmu 0x4d0>;
            pcie_intc: legacy-interrupt-controller {
                interrupt-controller;
                #address-cells = <0>;
                #interrupt-cells = <1>;
            };
        };
    };