Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,cpm1-tsa.yaml

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,cpm1-tsa.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: PowerQUICC CPM Time-slot assigner (TSA) controller

maintainers:
  - Herve Codina <herve.codina@bootlin.com>

description:
  The TSA is the time-slot assigner that can be found on some PowerQUICC SoC.
  Its purpose is to route some TDM time-slots to other internal serial
  controllers.

properties:
  compatible:
    items:
      - enum:
          - fsl,mpc885-tsa
          - fsl,mpc866-tsa
      - const: fsl,cpm1-tsa

  reg:
    items:
      - description: SI (Serial Interface) register base
      - description: SI RAM base

  reg-names:
    items:
      - const: si_regs
      - const: si_ram

  '#address-cells':
    const: 1

  '#size-cells':
    const: 0

patternProperties:
  '^tdm@[0-1]$':
    description:
      The TDM managed by this controller
    type: object

    additionalProperties: false

    properties:
      reg:
        minimum: 0
        maximum: 1
        description:
          The TDM number for this TDM, 0 for TDMa and 1 for TDMb

      fsl,common-rxtx-pins:
        $ref: /schemas/types.yaml#/definitions/flag
        description:
          The hardware can use four dedicated pins for Tx clock, Tx sync, Rx
          clock and Rx sync or use only two pins, Tx/Rx clock and Tx/Rx sync.
          Without the 'fsl,common-rxtx-pins' property, the four pins are used.
          With the 'fsl,common-rxtx-pins' property, two pins are used.

      clocks:
        minItems: 2
        items:
          - description: External clock connected to L1RSYNC pin
          - description: External clock connected to L1RCLK pin
          - description: External clock connected to L1TSYNC pin
          - description: External clock connected to L1TCLK pin

      clock-names:
        minItems: 2
        items:
          - const: l1rsync
          - const: l1rclk
          - const: l1tsync
          - const: l1tclk

      fsl,rx-frame-sync-delay-bits:
        enum: [0, 1, 2, 3]
        default: 0
        description: |
          Receive frame sync delay in number of bits.
          Indicates the delay between the Rx sync and the first bit of the Rx
          frame. 0 for no bit delay. 1, 2 or 3 for 1, 2 or 3 bits delay.

      fsl,tx-frame-sync-delay-bits:
        enum: [0, 1, 2, 3]
        default: 0
        description: |
          Transmit frame sync delay in number of bits.
          Indicates the delay between the Tx sync and the first bit of the Tx
          frame. 0 for no bit delay. 1, 2 or 3 for 1, 2 or 3 bits delay.

      fsl,clock-falling-edge:
        $ref: /schemas/types.yaml#/definitions/flag
        description:
          Data is sent on falling edge of the clock (and received on the rising
          edge). If 'clock-falling-edge' is not present, data is sent on the
          rising edge (and received on the falling edge).

      fsl,fsync-rising-edge:
        $ref: /schemas/types.yaml#/definitions/flag
        description:
          Frame sync pulses are sampled with the rising edge of the channel
          clock. If 'fsync-rising-edge' is not present, pulses are sampled with
          the falling edge.

      fsl,double-speed-clock:
        $ref: /schemas/types.yaml#/definitions/flag
        description:
          The channel clock is twice the data rate.

    patternProperties:
      '^fsl,[rt]x-ts-routes$':
        $ref: /schemas/types.yaml#/definitions/uint32-matrix
        description: |
          A list of tuple that indicates the Tx or Rx time-slots routes.
        items:
          items:
            - description:
                The number of time-slots
              minimum: 1
              maximum: 64
            - description: |
                The source (Tx) or destination (Rx) serial interface
                (dt-bindings/soc/cpm1-fsl,tsa.h defines these values)
                 - 0: No destination
                 - 1: SCC2
                 - 2: SCC3
                 - 3: SCC4
                 - 4: SMC1
                 - 5: SMC2
              enum: [0, 1, 2, 3, 4, 5]
        minItems: 1
        maxItems: 64

    allOf:
      # If fsl,common-rxtx-pins is present, only 2 clocks are needed.
      # Else, the 4 clocks must be present.
      - if:
          required:
            - fsl,common-rxtx-pins
        then:
          properties:
            clocks:
              maxItems: 2
            clock-names:
              maxItems: 2
        else:
          properties:
            clocks:
              minItems: 4
            clock-names:
              minItems: 4

    required:
      - reg
      - clocks
      - clock-names

required:
  - compatible
  - reg
  - reg-names
  - '#address-cells'
  - '#size-cells'

additionalProperties: false

examples:
  - |
    #include <dt-bindings/soc/cpm1-fsl,tsa.h>

    tsa@ae0 {
        compatible = "fsl,mpc885-tsa", "fsl,cpm1-tsa";
        reg = <0xae0 0x10>,
              <0xc00 0x200>;
        reg-names = "si_regs", "si_ram";

        #address-cells = <1>;
        #size-cells = <0>;

        tdm@0 {
            /* TDMa */
            reg = <0>;

            clocks = <&clk_l1rsynca>, <&clk_l1rclka>;
            clock-names = "l1rsync", "l1rclk";

            fsl,common-rxtx-pins;
            fsl,fsync-rising-edge;

            fsl,tx-ts-routes = <2 0>,             /* TS 0..1 */
                           <24 FSL_CPM_TSA_SCC4>, /* TS 2..25 */
                           <1 0>,                 /* TS 26 */
                           <5 FSL_CPM_TSA_SCC3>;  /* TS 27..31 */

            fsl,rx-ts-routes = <2 0>,             /* TS 0..1 */
                           <24 FSL_CPM_TSA_SCC4>, /* 2..25 */
                           <1 0>,                 /* TS 26 */
                           <5 FSL_CPM_TSA_SCC3>;  /* TS 27..31 */
        };
    };