| # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| %YAML 1.2 |
| --- |
| $id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qe.yaml# |
| $schema: http://devicetree.org/meta-schemas/core.yaml# |
| |
| title: Freescale QUICC Engine module (QE) |
| |
| maintainers: |
| - Frank Li <Frank.Li@nxp.com> |
| |
| description: | |
| This represents qe module that is installed on PowerQUICC II Pro. |
| |
| NOTE: This is an interim binding; it should be updated to fit |
| in with the CPM binding later in this document. |
| |
| Basically, it is a bus of devices, that could act more or less |
| as a complete entity (UCC, USB etc ). All of them should be siblings on |
| the "root" qe node, using the common properties from there. |
| The description below applies to the qe of MPC8360 and |
| more nodes and properties would be extended in the future. |
| |
| properties: |
| compatible: |
| items: |
| - const: fsl,qe |
| - const: simple-bus |
| |
| reg: |
| maxItems: 1 |
| |
| ranges: |
| maxItems: 1 |
| |
| model: |
| $ref: /schemas/types.yaml#/definitions/string |
| enum: [QE, CPM, CPM2] |
| |
| bus-frequency: |
| $ref: /schemas/types.yaml#/definitions/uint32 |
| description: the clock frequency for QUICC Engine. |
| |
| fsl,qe-num-riscs: |
| $ref: /schemas/types.yaml#/definitions/uint32 |
| description: define how many RISC engines the QE has. |
| |
| fsl,qe-snums: |
| $ref: /schemas/types.yaml#/definitions/uint8-array |
| maxItems: 28 |
| description: |
| defining the array of serial number (SNUM) values for the virtual |
| threads. |
| |
| fsl,firmware-phandle: |
| $ref: /schemas/types.yaml#/definitions/phandle |
| description: | |
| required only if there is no fsl,qe-firmware child node |
| |
| Points to a firmware node (see "QE Firmware Node" below) |
| that contains the firmware that should be uploaded for this QE. |
| The compatible property for the firmware node should say, |
| "fsl,qe-firmware". |
| |
| brg-frequency: |
| $ref: /schemas/types.yaml#/definitions/uint32 |
| description: |
| the internal clock source frequency for baud-rate |
| generators in Hz. |
| |
| fsl,qe-num-snums: |
| $ref: /schemas/types.yaml#/definitions/uint32 |
| deprecated: true |
| description: | |
| define how many serial number(SNUM) the QE can use |
| for the threads. Use fsl,qe-snums instead to not only specify the |
| number of snums, but also their values. |
| |
| patternProperties: |
| '^muram@[a-f0-9]+$': |
| $ref: fsl,qe-muram.yaml |
| |
| '^interrupt-controller@[a-f0-9]+$': |
| $ref: fsl,qe-ic.yaml |
| |
| '^si@[a-f0-9]+$': |
| $ref: fsl,qe-si.yaml |
| |
| '^siram@[a-f0-9]+$': |
| $ref: fsl,qe-siram.yaml |
| |
| required: |
| - compatible |
| - reg |
| - bus-frequency |
| |
| allOf: |
| - $ref: /schemas/simple-bus.yaml# |
| |
| unevaluatedProperties: false |
| |
| examples: |
| - | |
| qe-bus@e0100000 { |
| compatible = "fsl,qe", "simple-bus"; |
| reg = <0xe0100000 0x480>; |
| ranges = <0 0xe0100000 0x00100000>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| brg-frequency = <0>; |
| bus-frequency = <0x179a7b00>; |
| fsl,qe-snums = /bits/ 8 < |
| 0x04 0x05 0x0c 0x0d 0x14 0x15 0x1c 0x1d |
| 0x24 0x25 0x2c 0x2d 0x34 0x35 0x88 0x89 |
| 0x98 0x99 0xa8 0xa9 0xb8 0xb9 0xc8 0xc9 |
| 0xd8 0xd9 0xe8 0xe9>; |
| |
| interrupt-controller@80 { |
| compatible = "fsl,qe-ic"; |
| reg = <0x80 0x80>; |
| #interrupt-cells = <1>; |
| interrupt-controller; |
| interrupts = <95 2 0 0 94 2 0 0>; |
| }; |
| |
| si@700 { |
| compatible = "fsl,t1040-qe-si"; |
| reg = <0x700 0x80>; |
| }; |
| |
| siram@1000 { |
| compatible = "fsl,t1040-qe-siram"; |
| reg = <0x1000 0x800>; |
| }; |
| |
| muram@10000 { |
| compatible = "fsl,qe-muram", "fsl,cpm-muram"; |
| ranges = <0 0x00010000 0x0000c000>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| data-only@0{ |
| compatible = "fsl,qe-muram-data", |
| "fsl,cpm-muram-data"; |
| reg = <0 0xc000>; |
| }; |
| }; |
| }; |