| // SPDX-License-Identifier: GPL-2.0 |
| /* |
| * Samsung Exynos850 SoC device tree source |
| * |
| * Copyright (C) 2018 Samsung Electronics Co., Ltd. |
| * Copyright (C) 2021 Linaro Ltd. |
| * |
| * Samsung Exynos850 SoC device nodes are listed in this file. |
| * Exynos850 based board files can include this file and provide |
| * values for board specific bindings. |
| */ |
| |
| #include <dt-bindings/clock/exynos850.h> |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| #include <dt-bindings/soc/samsung,exynos-usi.h> |
| |
| / { |
| /* Also known under engineering name Exynos3830 */ |
| compatible = "samsung,exynos850"; |
| #address-cells = <2>; |
| #size-cells = <1>; |
| |
| interrupt-parent = <&gic>; |
| |
| aliases { |
| pinctrl0 = &pinctrl_alive; |
| pinctrl1 = &pinctrl_cmgp; |
| pinctrl2 = &pinctrl_aud; |
| pinctrl3 = &pinctrl_hsi; |
| pinctrl4 = &pinctrl_core; |
| pinctrl5 = &pinctrl_peri; |
| }; |
| |
| arm-pmu { |
| compatible = "arm,cortex-a55-pmu"; |
| interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>, |
| <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; |
| }; |
| |
| /* Main system clock (XTCXO); external, must be 26 MHz */ |
| oscclk: clock-oscclk { |
| compatible = "fixed-clock"; |
| clock-output-names = "oscclk"; |
| #clock-cells = <0>; |
| }; |
| |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| cpu-map { |
| cluster0 { |
| core0 { |
| cpu = <&cpu0>; |
| }; |
| core1 { |
| cpu = <&cpu1>; |
| }; |
| core2 { |
| cpu = <&cpu2>; |
| }; |
| core3 { |
| cpu = <&cpu3>; |
| }; |
| }; |
| |
| cluster1 { |
| core0 { |
| cpu = <&cpu4>; |
| }; |
| core1 { |
| cpu = <&cpu5>; |
| }; |
| core2 { |
| cpu = <&cpu6>; |
| }; |
| core3 { |
| cpu = <&cpu7>; |
| }; |
| }; |
| }; |
| |
| cpu0: cpu@0 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a55"; |
| reg = <0x0>; |
| enable-method = "psci"; |
| }; |
| cpu1: cpu@1 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a55"; |
| reg = <0x1>; |
| enable-method = "psci"; |
| }; |
| cpu2: cpu@2 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a55"; |
| reg = <0x2>; |
| enable-method = "psci"; |
| }; |
| cpu3: cpu@3 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a55"; |
| reg = <0x3>; |
| enable-method = "psci"; |
| }; |
| cpu4: cpu@100 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a55"; |
| reg = <0x100>; |
| enable-method = "psci"; |
| }; |
| cpu5: cpu@101 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a55"; |
| reg = <0x101>; |
| enable-method = "psci"; |
| }; |
| cpu6: cpu@102 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a55"; |
| reg = <0x102>; |
| enable-method = "psci"; |
| }; |
| cpu7: cpu@103 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a55"; |
| reg = <0x103>; |
| enable-method = "psci"; |
| }; |
| }; |
| |
| psci { |
| compatible = "arm,psci-1.0"; |
| method = "smc"; |
| }; |
| |
| timer { |
| compatible = "arm,armv8-timer"; |
| /* Hypervisor Virtual Timer interrupt is not wired to GIC */ |
| interrupts = |
| <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, |
| <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, |
| <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, |
| <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; |
| }; |
| |
| soc: soc@0 { |
| compatible = "simple-bus"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0x0 0x0 0x20000000>; |
| |
| chipid@10000000 { |
| compatible = "samsung,exynos850-chipid"; |
| reg = <0x10000000 0x100>; |
| }; |
| |
| timer@10040000 { |
| compatible = "samsung,exynos850-mct", |
| "samsung,exynos4210-mct"; |
| reg = <0x10040000 0x800>; |
| interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&oscclk>, <&cmu_peri CLK_GOUT_MCT_PCLK>; |
| clock-names = "fin_pll", "mct"; |
| }; |
| |
| gic: interrupt-controller@12a01000 { |
| compatible = "arm,gic-400"; |
| #interrupt-cells = <3>; |
| #address-cells = <0>; |
| reg = <0x12a01000 0x1000>, |
| <0x12a02000 0x2000>, |
| <0x12a04000 0x2000>, |
| <0x12a06000 0x2000>; |
| interrupt-controller; |
| interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | |
| IRQ_TYPE_LEVEL_HIGH)>; |
| }; |
| |
| pmu_system_controller: system-controller@11860000 { |
| compatible = "samsung,exynos850-pmu", "syscon"; |
| reg = <0x11860000 0x10000>; |
| clocks = <&cmu_apm CLK_GOUT_PMU_ALIVE_PCLK>; |
| |
| reboot: syscon-reboot { |
| compatible = "syscon-reboot"; |
| regmap = <&pmu_system_controller>; |
| offset = <0x3a00>; /* SYSTEM_CONFIGURATION */ |
| mask = <0x2>; /* SWRESET_SYSTEM */ |
| value = <0x2>; /* reset value */ |
| }; |
| }; |
| |
| watchdog_cl0: watchdog@10050000 { |
| compatible = "samsung,exynos850-wdt"; |
| reg = <0x10050000 0x100>; |
| interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cmu_peri CLK_GOUT_WDT0_PCLK>, <&oscclk>; |
| clock-names = "watchdog", "watchdog_src"; |
| samsung,syscon-phandle = <&pmu_system_controller>; |
| samsung,cluster-index = <0>; |
| status = "disabled"; |
| }; |
| |
| watchdog_cl1: watchdog@10060000 { |
| compatible = "samsung,exynos850-wdt"; |
| reg = <0x10060000 0x100>; |
| interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cmu_peri CLK_GOUT_WDT1_PCLK>, <&oscclk>; |
| clock-names = "watchdog", "watchdog_src"; |
| samsung,syscon-phandle = <&pmu_system_controller>; |
| samsung,cluster-index = <1>; |
| status = "disabled"; |
| }; |
| |
| cmu_peri: clock-controller@10030000 { |
| compatible = "samsung,exynos850-cmu-peri"; |
| reg = <0x10030000 0x8000>; |
| #clock-cells = <1>; |
| |
| clocks = <&oscclk>, <&cmu_top CLK_DOUT_PERI_BUS>, |
| <&cmu_top CLK_DOUT_PERI_UART>, |
| <&cmu_top CLK_DOUT_PERI_IP>; |
| clock-names = "oscclk", "dout_peri_bus", |
| "dout_peri_uart", "dout_peri_ip"; |
| }; |
| |
| cmu_g3d: clock-controller@11400000 { |
| compatible = "samsung,exynos850-cmu-g3d"; |
| reg = <0x11400000 0x8000>; |
| #clock-cells = <1>; |
| |
| clocks = <&oscclk>, <&cmu_top CLK_DOUT_G3D_SWITCH>; |
| clock-names = "oscclk", "dout_g3d_switch"; |
| }; |
| |
| cmu_apm: clock-controller@11800000 { |
| compatible = "samsung,exynos850-cmu-apm"; |
| reg = <0x11800000 0x8000>; |
| #clock-cells = <1>; |
| |
| clocks = <&oscclk>, <&cmu_top CLK_DOUT_CLKCMU_APM_BUS>; |
| clock-names = "oscclk", "dout_clkcmu_apm_bus"; |
| }; |
| |
| cmu_cmgp: clock-controller@11c00000 { |
| compatible = "samsung,exynos850-cmu-cmgp"; |
| reg = <0x11c00000 0x8000>; |
| #clock-cells = <1>; |
| |
| clocks = <&oscclk>, <&cmu_apm CLK_GOUT_CLKCMU_CMGP_BUS>; |
| clock-names = "oscclk", "gout_clkcmu_cmgp_bus"; |
| }; |
| |
| cmu_core: clock-controller@12000000 { |
| compatible = "samsung,exynos850-cmu-core"; |
| reg = <0x12000000 0x8000>; |
| #clock-cells = <1>; |
| |
| clocks = <&oscclk>, <&cmu_top CLK_DOUT_CORE_BUS>, |
| <&cmu_top CLK_DOUT_CORE_CCI>, |
| <&cmu_top CLK_DOUT_CORE_MMC_EMBD>, |
| <&cmu_top CLK_DOUT_CORE_SSS>; |
| clock-names = "oscclk", "dout_core_bus", |
| "dout_core_cci", "dout_core_mmc_embd", |
| "dout_core_sss"; |
| }; |
| |
| cmu_top: clock-controller@120e0000 { |
| compatible = "samsung,exynos850-cmu-top"; |
| reg = <0x120e0000 0x8000>; |
| #clock-cells = <1>; |
| |
| clocks = <&oscclk>; |
| clock-names = "oscclk"; |
| }; |
| |
| cmu_mfcmscl: clock-controller@12c00000 { |
| compatible = "samsung,exynos850-cmu-mfcmscl"; |
| reg = <0x12c00000 0x8000>; |
| #clock-cells = <1>; |
| |
| clocks = <&oscclk>, |
| <&cmu_top CLK_DOUT_MFCMSCL_MFC>, |
| <&cmu_top CLK_DOUT_MFCMSCL_M2M>, |
| <&cmu_top CLK_DOUT_MFCMSCL_MCSC>, |
| <&cmu_top CLK_DOUT_MFCMSCL_JPEG>; |
| clock-names = "oscclk", "dout_mfcmscl_mfc", |
| "dout_mfcmscl_m2m", "dout_mfcmscl_mcsc", |
| "dout_mfcmscl_jpeg"; |
| }; |
| |
| cmu_dpu: clock-controller@13000000 { |
| compatible = "samsung,exynos850-cmu-dpu"; |
| reg = <0x13000000 0x8000>; |
| #clock-cells = <1>; |
| |
| clocks = <&oscclk>, <&cmu_top CLK_DOUT_DPU>; |
| clock-names = "oscclk", "dout_dpu"; |
| }; |
| |
| cmu_hsi: clock-controller@13400000 { |
| compatible = "samsung,exynos850-cmu-hsi"; |
| reg = <0x13400000 0x8000>; |
| #clock-cells = <1>; |
| |
| clocks = <&oscclk>, |
| <&cmu_top CLK_DOUT_HSI_BUS>, |
| <&cmu_top CLK_DOUT_HSI_MMC_CARD>, |
| <&cmu_top CLK_DOUT_HSI_USB20DRD>; |
| clock-names = "oscclk", "dout_hsi_bus", |
| "dout_hsi_mmc_card", "dout_hsi_usb20drd"; |
| }; |
| |
| cmu_is: clock-controller@14500000 { |
| compatible = "samsung,exynos850-cmu-is"; |
| reg = <0x14500000 0x8000>; |
| #clock-cells = <1>; |
| |
| clocks = <&oscclk>, |
| <&cmu_top CLK_DOUT_IS_BUS>, |
| <&cmu_top CLK_DOUT_IS_ITP>, |
| <&cmu_top CLK_DOUT_IS_VRA>, |
| <&cmu_top CLK_DOUT_IS_GDC>; |
| clock-names = "oscclk", "dout_is_bus", "dout_is_itp", |
| "dout_is_vra", "dout_is_gdc"; |
| }; |
| |
| cmu_aud: clock-controller@14a00000 { |
| compatible = "samsung,exynos850-cmu-aud"; |
| reg = <0x14a00000 0x8000>; |
| #clock-cells = <1>; |
| |
| clocks = <&oscclk>, <&cmu_top CLK_DOUT_AUD>; |
| clock-names = "oscclk", "dout_aud"; |
| }; |
| |
| pinctrl_alive: pinctrl@11850000 { |
| compatible = "samsung,exynos850-pinctrl"; |
| reg = <0x11850000 0x1000>; |
| |
| wakeup-interrupt-controller { |
| compatible = "samsung,exynos850-wakeup-eint"; |
| }; |
| }; |
| |
| pinctrl_cmgp: pinctrl@11c30000 { |
| compatible = "samsung,exynos850-pinctrl"; |
| reg = <0x11c30000 0x1000>; |
| |
| wakeup-interrupt-controller { |
| compatible = "samsung,exynos850-wakeup-eint"; |
| }; |
| }; |
| |
| pinctrl_core: pinctrl@12070000 { |
| compatible = "samsung,exynos850-pinctrl"; |
| reg = <0x12070000 0x1000>; |
| interrupts = <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| pinctrl_hsi: pinctrl@13430000 { |
| compatible = "samsung,exynos850-pinctrl"; |
| reg = <0x13430000 0x1000>; |
| interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| pinctrl_peri: pinctrl@139b0000 { |
| compatible = "samsung,exynos850-pinctrl"; |
| reg = <0x139b0000 0x1000>; |
| interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| pinctrl_aud: pinctrl@14a60000 { |
| compatible = "samsung,exynos850-pinctrl"; |
| reg = <0x14a60000 0x1000>; |
| }; |
| |
| rtc: rtc@11a30000 { |
| compatible = "samsung,s3c6410-rtc"; |
| reg = <0x11a30000 0x100>; |
| interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cmu_apm CLK_GOUT_RTC_PCLK>; |
| clock-names = "rtc"; |
| status = "disabled"; |
| }; |
| |
| mmc_0: mmc@12100000 { |
| compatible = "samsung,exynos7-dw-mshc-smu"; |
| reg = <0x12100000 0x2000>; |
| interrupts = <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&cmu_core CLK_GOUT_MMC_EMBD_ACLK>, |
| <&cmu_core CLK_GOUT_MMC_EMBD_SDCLKIN>; |
| clock-names = "biu", "ciu"; |
| fifo-depth = <0x40>; |
| status = "disabled"; |
| }; |
| |
| i2c_0: i2c@13830000 { |
| compatible = "samsung,s3c2440-i2c"; |
| reg = <0x13830000 0x100>; |
| interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&i2c0_pins>; |
| clocks = <&cmu_peri CLK_GOUT_I2C0_PCLK>; |
| clock-names = "i2c"; |
| status = "disabled"; |
| }; |
| |
| i2c_1: i2c@13840000 { |
| compatible = "samsung,s3c2440-i2c"; |
| reg = <0x13840000 0x100>; |
| interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&i2c1_pins>; |
| clocks = <&cmu_peri CLK_GOUT_I2C1_PCLK>; |
| clock-names = "i2c"; |
| status = "disabled"; |
| }; |
| |
| i2c_2: i2c@13850000 { |
| compatible = "samsung,s3c2440-i2c"; |
| reg = <0x13850000 0x100>; |
| interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&i2c2_pins>; |
| clocks = <&cmu_peri CLK_GOUT_I2C2_PCLK>; |
| clock-names = "i2c"; |
| status = "disabled"; |
| }; |
| |
| i2c_3: i2c@13860000 { |
| compatible = "samsung,s3c2440-i2c"; |
| reg = <0x13860000 0x100>; |
| interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&i2c3_pins>; |
| clocks = <&cmu_peri CLK_GOUT_I2C3_PCLK>; |
| clock-names = "i2c"; |
| status = "disabled"; |
| }; |
| |
| i2c_4: i2c@13870000 { |
| compatible = "samsung,s3c2440-i2c"; |
| reg = <0x13870000 0x100>; |
| interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&i2c4_pins>; |
| clocks = <&cmu_peri CLK_GOUT_I2C4_PCLK>; |
| clock-names = "i2c"; |
| status = "disabled"; |
| }; |
| |
| /* I2C_5 (also called CAM_PMIC_I2C in TRM) */ |
| i2c_5: i2c@13880000 { |
| compatible = "samsung,s3c2440-i2c"; |
| reg = <0x13880000 0x100>; |
| interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&i2c5_pins>; |
| clocks = <&cmu_peri CLK_GOUT_I2C5_PCLK>; |
| clock-names = "i2c"; |
| status = "disabled"; |
| }; |
| |
| /* I2C_6 (also called MOTOR_I2C in TRM) */ |
| i2c_6: i2c@13890000 { |
| compatible = "samsung,s3c2440-i2c"; |
| reg = <0x13890000 0x100>; |
| interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&i2c6_pins>; |
| clocks = <&cmu_peri CLK_GOUT_I2C6_PCLK>; |
| clock-names = "i2c"; |
| status = "disabled"; |
| }; |
| |
| sysmmu_mfcmscl: sysmmu@12c50000 { |
| compatible = "samsung,exynos-sysmmu"; |
| reg = <0x12c50000 0x9000>; |
| interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; |
| clock-names = "sysmmu"; |
| clocks = <&cmu_mfcmscl CLK_GOUT_MFCMSCL_SYSMMU_CLK>; |
| #iommu-cells = <0>; |
| }; |
| |
| sysmmu_dpu: sysmmu@130c0000 { |
| compatible = "samsung,exynos-sysmmu"; |
| reg = <0x130c0000 0x9000>; |
| interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; |
| clock-names = "sysmmu"; |
| clocks = <&cmu_dpu CLK_GOUT_DPU_SMMU_CLK>; |
| #iommu-cells = <0>; |
| }; |
| |
| sysmmu_is0: sysmmu@14550000 { |
| compatible = "samsung,exynos-sysmmu"; |
| reg = <0x14550000 0x9000>; |
| interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; |
| clock-names = "sysmmu"; |
| clocks = <&cmu_is CLK_GOUT_IS_SYSMMU_IS0_CLK>; |
| #iommu-cells = <0>; |
| }; |
| |
| sysmmu_is1: sysmmu@14570000 { |
| compatible = "samsung,exynos-sysmmu"; |
| reg = <0x14570000 0x9000>; |
| interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; |
| clock-names = "sysmmu"; |
| clocks = <&cmu_is CLK_GOUT_IS_SYSMMU_IS1_CLK>; |
| #iommu-cells = <0>; |
| }; |
| |
| sysmmu_aud: sysmmu@14850000 { |
| compatible = "samsung,exynos-sysmmu"; |
| reg = <0x14850000 0x9000>; |
| interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; |
| clock-names = "sysmmu"; |
| clocks = <&cmu_aud CLK_GOUT_AUD_SYSMMU_CLK>; |
| #iommu-cells = <0>; |
| }; |
| |
| sysreg_peri: syscon@10020000 { |
| compatible = "samsung,exynos850-peri-sysreg", |
| "samsung,exynos850-sysreg", "syscon"; |
| reg = <0x10020000 0x10000>; |
| clocks = <&cmu_peri CLK_GOUT_SYSREG_PERI_PCLK>; |
| }; |
| |
| sysreg_cmgp: syscon@11c20000 { |
| compatible = "samsung,exynos850-cmgp-sysreg", |
| "samsung,exynos850-sysreg", "syscon"; |
| reg = <0x11c20000 0x10000>; |
| clocks = <&cmu_cmgp CLK_GOUT_SYSREG_CMGP_PCLK>; |
| }; |
| |
| usi_uart: usi@138200c0 { |
| compatible = "samsung,exynos850-usi"; |
| reg = <0x138200c0 0x20>; |
| samsung,sysreg = <&sysreg_peri 0x1010>; |
| samsung,mode = <USI_V2_UART>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges; |
| clocks = <&cmu_peri CLK_GOUT_UART_PCLK>, |
| <&cmu_peri CLK_GOUT_UART_IPCLK>; |
| clock-names = "pclk", "ipclk"; |
| status = "disabled"; |
| |
| serial_0: serial@13820000 { |
| compatible = "samsung,exynos850-uart"; |
| reg = <0x13820000 0xc0>; |
| interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&uart0_pins>; |
| clocks = <&cmu_peri CLK_GOUT_UART_PCLK>, |
| <&cmu_peri CLK_GOUT_UART_IPCLK>; |
| clock-names = "uart", "clk_uart_baud0"; |
| status = "disabled"; |
| }; |
| }; |
| |
| usi_hsi2c_0: usi@138a00c0 { |
| compatible = "samsung,exynos850-usi"; |
| reg = <0x138a00c0 0x20>; |
| samsung,sysreg = <&sysreg_peri 0x1020>; |
| samsung,mode = <USI_V2_I2C>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges; |
| clocks = <&cmu_peri CLK_GOUT_HSI2C0_PCLK>, |
| <&cmu_peri CLK_GOUT_HSI2C0_IPCLK>; |
| clock-names = "pclk", "ipclk"; |
| status = "disabled"; |
| |
| hsi2c_0: i2c@138a0000 { |
| compatible = "samsung,exynosautov9-hsi2c"; |
| reg = <0x138a0000 0xc0>; |
| interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&hsi2c0_pins>; |
| clocks = <&cmu_peri CLK_GOUT_HSI2C0_IPCLK>, |
| <&cmu_peri CLK_GOUT_HSI2C0_PCLK>; |
| clock-names = "hsi2c", "hsi2c_pclk"; |
| status = "disabled"; |
| }; |
| }; |
| |
| usi_hsi2c_1: usi@138b00c0 { |
| compatible = "samsung,exynos850-usi"; |
| reg = <0x138b00c0 0x20>; |
| samsung,sysreg = <&sysreg_peri 0x1030>; |
| samsung,mode = <USI_V2_I2C>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges; |
| clocks = <&cmu_peri CLK_GOUT_HSI2C1_PCLK>, |
| <&cmu_peri CLK_GOUT_HSI2C1_IPCLK>; |
| clock-names = "pclk", "ipclk"; |
| status = "disabled"; |
| |
| hsi2c_1: i2c@138b0000 { |
| compatible = "samsung,exynosautov9-hsi2c"; |
| reg = <0x138b0000 0xc0>; |
| interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&hsi2c1_pins>; |
| clocks = <&cmu_peri CLK_GOUT_HSI2C1_IPCLK>, |
| <&cmu_peri CLK_GOUT_HSI2C1_PCLK>; |
| clock-names = "hsi2c", "hsi2c_pclk"; |
| status = "disabled"; |
| }; |
| }; |
| |
| usi_hsi2c_2: usi@138c00c0 { |
| compatible = "samsung,exynos850-usi"; |
| reg = <0x138c00c0 0x20>; |
| samsung,sysreg = <&sysreg_peri 0x1040>; |
| samsung,mode = <USI_V2_I2C>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges; |
| clocks = <&cmu_peri CLK_GOUT_HSI2C2_PCLK>, |
| <&cmu_peri CLK_GOUT_HSI2C2_IPCLK>; |
| clock-names = "pclk", "ipclk"; |
| status = "disabled"; |
| |
| hsi2c_2: i2c@138c0000 { |
| compatible = "samsung,exynosautov9-hsi2c"; |
| reg = <0x138c0000 0xc0>; |
| interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&hsi2c2_pins>; |
| clocks = <&cmu_peri CLK_GOUT_HSI2C2_IPCLK>, |
| <&cmu_peri CLK_GOUT_HSI2C2_PCLK>; |
| clock-names = "hsi2c", "hsi2c_pclk"; |
| status = "disabled"; |
| }; |
| }; |
| |
| usi_spi_0: usi@139400c0 { |
| compatible = "samsung,exynos850-usi"; |
| reg = <0x139400c0 0x20>; |
| samsung,sysreg = <&sysreg_peri 0x1050>; |
| samsung,mode = <USI_V2_SPI>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges; |
| clocks = <&cmu_peri CLK_GOUT_SPI0_PCLK>, |
| <&cmu_peri CLK_GOUT_SPI0_IPCLK>; |
| clock-names = "pclk", "ipclk"; |
| status = "disabled"; |
| }; |
| |
| usi_cmgp0: usi@11d000c0 { |
| compatible = "samsung,exynos850-usi"; |
| reg = <0x11d000c0 0x20>; |
| samsung,sysreg = <&sysreg_cmgp 0x2000>; |
| samsung,mode = <USI_V2_I2C>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges; |
| clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI0_PCLK>, |
| <&cmu_cmgp CLK_GOUT_CMGP_USI0_IPCLK>; |
| clock-names = "pclk", "ipclk"; |
| status = "disabled"; |
| |
| hsi2c_3: i2c@11d00000 { |
| compatible = "samsung,exynosautov9-hsi2c"; |
| reg = <0x11d00000 0xc0>; |
| interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&hsi2c3_pins>; |
| clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI0_IPCLK>, |
| <&cmu_cmgp CLK_GOUT_CMGP_USI0_PCLK>; |
| clock-names = "hsi2c", "hsi2c_pclk"; |
| status = "disabled"; |
| }; |
| |
| serial_1: serial@11d00000 { |
| compatible = "samsung,exynos850-uart"; |
| reg = <0x11d00000 0xc0>; |
| interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&uart1_single_pins>; |
| clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI0_PCLK>, |
| <&cmu_cmgp CLK_GOUT_CMGP_USI0_IPCLK>; |
| clock-names = "uart", "clk_uart_baud0"; |
| status = "disabled"; |
| }; |
| }; |
| |
| usi_cmgp1: usi@11d200c0 { |
| compatible = "samsung,exynos850-usi"; |
| reg = <0x11d200c0 0x20>; |
| samsung,sysreg = <&sysreg_cmgp 0x2010>; |
| samsung,mode = <USI_V2_I2C>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges; |
| clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI1_PCLK>, |
| <&cmu_cmgp CLK_GOUT_CMGP_USI1_IPCLK>; |
| clock-names = "pclk", "ipclk"; |
| status = "disabled"; |
| |
| hsi2c_4: i2c@11d20000 { |
| compatible = "samsung,exynosautov9-hsi2c"; |
| reg = <0x11d20000 0xc0>; |
| interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&hsi2c4_pins>; |
| clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI1_IPCLK>, |
| <&cmu_cmgp CLK_GOUT_CMGP_USI1_PCLK>; |
| clock-names = "hsi2c", "hsi2c_pclk"; |
| status = "disabled"; |
| }; |
| |
| serial_2: serial@11d20000 { |
| compatible = "samsung,exynos850-uart"; |
| reg = <0x11d20000 0xc0>; |
| interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&uart2_single_pins>; |
| clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI1_PCLK>, |
| <&cmu_cmgp CLK_GOUT_CMGP_USI1_IPCLK>; |
| clock-names = "uart", "clk_uart_baud0"; |
| status = "disabled"; |
| }; |
| }; |
| }; |
| }; |
| |
| #include "exynos850-pinctrl.dtsi" |
