Documentation/devicetree/bindings/crypto/inside-secure-safexcel.txt

Inside Secure SafeXcel cryptographic engine

Required properties:
- compatible: Should be "inside-secure,safexcel-eip197b",
	      "inside-secure,safexcel-eip197d" or
              "inside-secure,safexcel-eip97ies".
- reg: Base physical address of the engine and length of memory mapped region.
- interrupts: Interrupt numbers for the rings and engine.
- interrupt-names: Should be "ring0", "ring1", "ring2", "ring3", "eip", "mem".

Optional properties:
- clocks: Reference to the crypto engine clocks, the second clock is
          needed for the Armada 7K/8K SoCs.
- clock-names: mandatory if there is a second clock, in this case the
               name must be "core" for the first clock and "reg" for
               the second one.

Backward compatibility:
Two compatibles are kept for backward compatibility, but shouldn't be used for
new submissions:
- "inside-secure,safexcel-eip197" is equivalent to
  "inside-secure,safexcel-eip197b".
- "inside-secure,safexcel-eip97" is equivalent to
  "inside-secure,safexcel-eip97ies".

Example:

	crypto: crypto@800000 {
		compatible = "inside-secure,safexcel-eip197b";
		reg = <0x800000 0x200000>;
		interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "mem", "ring0", "ring1", "ring2", "ring3",
				  "eip";
		clocks = <&cpm_syscon0 1 26>;
	};