| // SPDX-License-Identifier: GPL-2.0-only |
| /* |
| * Copyright (C) 2013 Newflow Ltd - http://www.newflow.co.uk/ |
| */ |
| /dts-v1/; |
| |
| #include "am33xx.dtsi" |
| |
| / { |
| model = "Newflow AM335x NanoBone"; |
| compatible = "ti,am33xx"; |
| |
| cpus { |
| cpu@0 { |
| cpu0-supply = <&dcdc2_reg>; |
| }; |
| }; |
| |
| memory@80000000 { |
| device_type = "memory"; |
| reg = <0x80000000 0x10000000>; /* 256 MB */ |
| }; |
| |
| leds { |
| compatible = "gpio-leds"; |
| |
| led0 { |
| label = "nanobone:green:usr1"; |
| gpios = <&gpio1 5 0>; |
| default-state = "off"; |
| }; |
| }; |
| }; |
| |
| &am33xx_pinmux { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&misc_pins>; |
| |
| misc_pins: misc_pins { |
| pinctrl-single,pins = < |
| AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_OUTPUT, MUX_MODE7) /* spi0_cs0.gpio0_5 */ |
| >; |
| }; |
| |
| gpmc_pins: gpmc_pins { |
| pinctrl-single,pins = < |
| AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE0) |
| AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE0) |
| AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE0) |
| AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE0) |
| AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE0) |
| AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE0) |
| AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE0) |
| AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE0) |
| AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_INPUT_PULLUP, MUX_MODE0) |
| AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_INPUT_PULLUP, MUX_MODE0) |
| AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_INPUT_PULLUP, MUX_MODE0) |
| AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_INPUT_PULLUP, MUX_MODE0) |
| AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT_PULLUP, MUX_MODE0) |
| AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLUP, MUX_MODE0) |
| AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLUP, MUX_MODE0) |
| AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLUP, MUX_MODE0) |
| |
| AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE0) |
| AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT, MUX_MODE0) |
| AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_OUTPUT, MUX_MODE0) |
| AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_OUTPUT, MUX_MODE0) |
| AM33XX_PADCONF(AM335X_PIN_GPMC_CSN3, PIN_OUTPUT, MUX_MODE0) |
| |
| AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE0) |
| AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT, MUX_MODE0) |
| AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE0) |
| AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT, MUX_MODE0) |
| |
| AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE1) /* lcd_data1.gpmc_a1 */ |
| AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE1) /* lcd_data2.gpmc_a2 */ |
| AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE1) /* lcd_data3.gpmc_a3 */ |
| AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE1) /* lcd_data4.gpmc_a4 */ |
| AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE1) /* lcd_data5.gpmc_a5 */ |
| AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE1) /* lcd_data6.gpmc_a6 */ |
| AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE1) /* lcd_data7.gpmc_a7 */ |
| |
| AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT, MUX_MODE1) /* lcd_vsync.gpmc_a8 */ |
| AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT, MUX_MODE1) /* lcd_hsync.gpmc_a9 */ |
| AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE1) /* lcd_pclk.gpmc_a10 */ |
| >; |
| }; |
| |
| i2c0_pins: i2c0_pins { |
| pinctrl-single,pins = < |
| AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLDOWN, MUX_MODE0) |
| AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLDOWN, MUX_MODE0) |
| >; |
| }; |
| |
| uart0_pins: uart0_pins { |
| pinctrl-single,pins = < |
| AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) |
| AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT, MUX_MODE0) |
| >; |
| }; |
| |
| uart1_pins: uart1_pins { |
| pinctrl-single,pins = < |
| AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_OUTPUT, MUX_MODE7) |
| AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT, MUX_MODE7) |
| AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0) |
| AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT, MUX_MODE0) |
| >; |
| }; |
| |
| uart2_pins: uart2_pins { |
| pinctrl-single,pins = < |
| AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_INPUT_PULLUP, MUX_MODE7) /* lcd_data8.gpio2[14] */ |
| AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE7) /* lcd_data9.gpio2[15] */ |
| AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT, MUX_MODE1) /* spi0_sclk.uart2_rxd */ |
| AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_OUTPUT, MUX_MODE1) /* spi0_d0.uart2_txd */ |
| >; |
| }; |
| |
| uart3_pins: uart3_pins { |
| pinctrl-single,pins = < |
| AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_INPUT_PULLUP, MUX_MODE6) /* lcd_data10.uart3_ctsn */ |
| AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE6) /* lcd_data11.uart3_rtsn */ |
| AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE1) /* spi0_cs1.uart3_rxd */ |
| AM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, PIN_OUTPUT, MUX_MODE1) /* ecap0_in_pwm0_out.uart3_txd */ |
| >; |
| }; |
| |
| uart4_pins: uart4_pins { |
| pinctrl-single,pins = < |
| AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_INPUT_PULLUP, MUX_MODE6) /* lcd_data12.uart4_ctsn */ |
| AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE6) /* lcd_data13.uart4_rtsn */ |
| AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT, MUX_MODE1) /* uart0_ctsn.uart4_rxd */ |
| AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_OUTPUT, MUX_MODE1) /* uart0_rtsn.uart4_txd */ |
| >; |
| }; |
| |
| uart5_pins: uart5_pins { |
| pinctrl-single,pins = < |
| AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_INPUT, MUX_MODE4) /* lcd_data14.uart5_rxd */ |
| AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_OUTPUT, MUX_MODE3) /* rmiii1_refclk.uart5_txd */ |
| >; |
| }; |
| |
| mmc1_pins: mmc1_pins { |
| pinctrl-single,pins = < |
| AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) |
| AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) |
| AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) |
| AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) |
| AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) /* mmc0_clk.mmc0_clk */ |
| AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) /* mmc0_cmd.mmc0_cmd */ |
| AM33XX_PADCONF(AM335X_PIN_EMU1, PIN_INPUT_PULLUP, MUX_MODE7) /* emu1.gpio3[8] */ |
| AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_INPUT_PULLUP, MUX_MODE7) /* mcasp0_aclkr.gpio3[18] */ |
| >; |
| }; |
| }; |
| |
| &uart0 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&uart0_pins>; |
| status = "okay"; |
| }; |
| |
| &uart1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&uart1_pins>; |
| status = "okay"; |
| rts-gpio = <&gpio0 13 GPIO_ACTIVE_HIGH>; |
| rs485-rts-active-high; |
| rs485-rx-during-tx; |
| rs485-rts-delay = <1 1>; |
| linux,rs485-enabled-at-boot-time; |
| }; |
| |
| &uart2 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&uart2_pins>; |
| status = "okay"; |
| rts-gpio = <&gpio2 15 GPIO_ACTIVE_HIGH>; |
| rs485-rts-active-high; |
| rs485-rts-delay = <1 1>; |
| linux,rs485-enabled-at-boot-time; |
| }; |
| |
| &uart3 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&uart3_pins>; |
| status = "okay"; |
| }; |
| |
| &uart4 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&uart4_pins>; |
| status = "okay"; |
| }; |
| |
| &uart5 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&uart5_pins>; |
| status = "okay"; |
| }; |
| |
| &i2c0 { |
| status = "okay"; |
| pinctrl-names = "default"; |
| clock-frequency = <400000>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&i2c0_pins>; |
| |
| gpio@20 { |
| compatible = "microchip,mcp23017"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x20>; |
| }; |
| |
| tps: tps@24 { |
| reg = <0x24>; |
| }; |
| |
| eeprom@53 { |
| compatible = "microchip,24c02", "atmel,24c02"; |
| reg = <0x53>; |
| pagesize = <8>; |
| }; |
| |
| rtc@68 { |
| compatible = "dallas,ds1307"; |
| reg = <0x68>; |
| }; |
| }; |
| |
| &elm { |
| status = "okay"; |
| }; |
| |
| &gpmc { |
| compatible = "ti,am3352-gpmc"; |
| ti,hwmods = "gpmc"; |
| status = "okay"; |
| gpmc,num-waitpins = <2>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&gpmc_pins>; |
| |
| #address-cells = <2>; |
| #size-cells = <1>; |
| ranges = <0 0 0x08000000 0x08000000>, /* CS0: NOR 128M */ |
| <1 0 0x1c000000 0x01000000>; /* CS1: FRAM 16M */ |
| |
| nor@0,0 { |
| reg = <0 0x00000000 0x08000000>; |
| compatible = "cfi-flash"; |
| linux,mtd-name = "spansion,s29gl010p11t"; |
| bank-width = <2>; |
| |
| gpmc,mux-add-data = <2>; |
| |
| gpmc,sync-clk-ps = <0>; |
| gpmc,cs-on-ns = <0>; |
| gpmc,cs-rd-off-ns = <160>; |
| gpmc,cs-wr-off-ns = <160>; |
| gpmc,adv-on-ns = <10>; |
| gpmc,adv-rd-off-ns = <30>; |
| gpmc,adv-wr-off-ns = <30>; |
| gpmc,oe-on-ns = <40>; |
| gpmc,oe-off-ns = <160>; |
| gpmc,we-on-ns = <40>; |
| gpmc,we-off-ns = <160>; |
| gpmc,rd-cycle-ns = <160>; |
| gpmc,wr-cycle-ns = <160>; |
| gpmc,access-ns = <150>; |
| gpmc,page-burst-access-ns = <10>; |
| gpmc,cycle2cycle-samecsen; |
| gpmc,cycle2cycle-delay-ns = <20>; |
| gpmc,wr-data-mux-bus-ns = <70>; |
| gpmc,wr-access-ns = <80>; |
| |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| /* |
| MTD partition table |
| =================== |
| +------------+-->0x00000000-> U-Boot start |
| | | |
| | |-->0x000BFFFF-> U-Boot end |
| | |-->0x000C0000-> ENV1 start |
| | | |
| | |-->0x000DFFFF-> ENV1 end |
| | |-->0x000E0000-> ENV2 start |
| | | |
| | |-->0x000FFFFF-> ENV2 end |
| | |-->0x00100000-> Kernel start |
| | | |
| | |-->0x004FFFFF-> Kernel end |
| | |-->0x00500000-> File system start |
| | | |
| | |-->0x01FFFFFF-> File system end |
| | |-->0x02000000-> User data start |
| | | |
| | |-->0x03FFFFFF-> User data end |
| | |-->0x04000000-> Data storage start |
| | | |
| +------------+-->0x08000000-> NOR end (Free end) |
| */ |
| partition@0 { |
| label = "boot"; |
| reg = <0x00000000 0x000c0000>; /* 768KB */ |
| }; |
| |
| partition@1 { |
| label = "env1"; |
| reg = <0x000c0000 0x00020000>; /* 128KB */ |
| }; |
| |
| partition@2 { |
| label = "env2"; |
| reg = <0x000e0000 0x00020000>; /* 128KB */ |
| }; |
| |
| partition@3 { |
| label = "kernel"; |
| reg = <0x00100000 0x00400000>; /* 4MB */ |
| }; |
| |
| partition@4 { |
| label = "rootfs"; |
| reg = <0x00500000 0x01b00000>; /* 27MB */ |
| }; |
| |
| partition@5 { |
| label = "user"; |
| reg = <0x02000000 0x02000000>; /* 32MB */ |
| }; |
| |
| partition@6 { |
| label = "data"; |
| reg = <0x04000000 0x04000000>; /* 64MB */ |
| }; |
| }; |
| |
| fram@1,0 { |
| reg = <1 0x00000000 0x01000000>; |
| bank-width = <2>; |
| |
| gpmc,mux-add-data = <2>; |
| |
| gpmc,sync-clk-ps = <0>; |
| gpmc,cs-on-ns = <0>; |
| gpmc,cs-rd-off-ns = <160>; |
| gpmc,cs-wr-off-ns = <160>; |
| gpmc,adv-on-ns = <10>; |
| gpmc,adv-rd-off-ns = <20>; |
| gpmc,adv-wr-off-ns = <20>; |
| gpmc,oe-on-ns = <30>; |
| gpmc,oe-off-ns = <150>; |
| gpmc,we-on-ns = <30>; |
| gpmc,we-off-ns = <150>; |
| gpmc,rd-cycle-ns = <160>; |
| gpmc,wr-cycle-ns = <160>; |
| gpmc,access-ns = <130>; |
| gpmc,page-burst-access-ns = <10>; |
| gpmc,cycle2cycle-samecsen; |
| gpmc,cycle2cycle-diffcsen; |
| gpmc,cycle2cycle-delay-ns = <10>; |
| gpmc,wr-data-mux-bus-ns = <30>; |
| gpmc,wr-access-ns = <0>; |
| }; |
| }; |
| |
| &mac { |
| dual_emac; |
| status = "okay"; |
| }; |
| |
| &davinci_mdio { |
| status = "okay"; |
| |
| ethphy0: ethernet-phy@0 { |
| reg = <0>; |
| }; |
| |
| ethphy1: ethernet-phy@1 { |
| reg = <1>; |
| }; |
| }; |
| |
| &cpsw_emac0 { |
| phy-handle = <ðphy0>; |
| phy-mode = "mii"; |
| dual_emac_res_vlan = <1>; |
| }; |
| |
| &cpsw_emac1 { |
| phy-handle = <ðphy1>; |
| phy-mode = "mii"; |
| dual_emac_res_vlan = <2>; |
| }; |
| |
| &mmc1 { |
| status = "okay"; |
| vmmc-supply = <&ldo4_reg>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&mmc1_pins>; |
| bus-width = <4>; |
| cd-gpios = <&gpio3 8 0>; |
| wp-gpios = <&gpio3 18 0>; |
| }; |
| |
| #include "tps65217.dtsi" |
| |
| &tps { |
| regulators { |
| dcdc1_reg: regulator@0 { |
| /* +1.5V voltage with ±4% tolerance */ |
| regulator-min-microvolt = <1450000>; |
| regulator-max-microvolt = <1550000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| dcdc2_reg: regulator@1 { |
| /* VDD_MPU voltage limits 0.95V - 1.1V with ±4% tolerance */ |
| regulator-name = "vdd_mpu"; |
| regulator-min-microvolt = <915000>; |
| regulator-max-microvolt = <1140000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| dcdc3_reg: regulator@2 { |
| /* VDD_CORE voltage limits 0.95V - 1.1V with ±4% tolerance */ |
| regulator-name = "vdd_core"; |
| regulator-min-microvolt = <915000>; |
| regulator-max-microvolt = <1140000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| ldo1_reg: regulator@3 { |
| /* +1.8V voltage with ±4% tolerance */ |
| regulator-min-microvolt = <1750000>; |
| regulator-max-microvolt = <1870000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| ldo2_reg: regulator@4 { |
| /* +3.3V voltage with ±4% tolerance */ |
| regulator-min-microvolt = <3175000>; |
| regulator-max-microvolt = <3430000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| ldo3_reg: regulator@5 { |
| /* +1.8V voltage with ±4% tolerance */ |
| regulator-min-microvolt = <1750000>; |
| regulator-max-microvolt = <1870000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| ldo4_reg: regulator@6 { |
| /* +3.3V voltage with ±4% tolerance */ |
| regulator-min-microvolt = <3175000>; |
| regulator-max-microvolt = <3430000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| }; |
| }; |
