| // SPDX-License-Identifier: GPL-2.0 |
| /* |
| * Device tree for Winterland IceBoard |
| * |
| * https://mcgillcosmology.com |
| * https://threespeedlogic.com |
| * |
| * This is an ARM + FPGA instrumentation board used at telescopes in |
| * Antarctica (the South Pole Telescope), Chile (POLARBEAR), and at the DRAO |
| * observatory in British Columbia (CHIME). |
| * |
| * Copyright (c) 2019 Three-Speed Logic, Inc. <gsmecher@threespeedlogic.com> |
| */ |
| |
| /dts-v1/; |
| |
| #include "dm814x.dtsi" |
| #include <dt-bindings/interrupt-controller/irq.h> |
| |
| / { |
| model = "Winterland IceBoard"; |
| compatible = "ti,dm8148", "ti,dm814"; |
| |
| chosen { |
| stdout-path = "serial1:115200n8"; |
| bootargs = "earlycon"; |
| }; |
| |
| memory@80000000 { |
| device_type = "memory"; |
| reg = <0x80000000 0x40000000>; /* 1 GB */ |
| }; |
| |
| vmmcsd_fixed: fixedregulator0 { |
| compatible = "regulator-fixed"; |
| regulator-name = "vmmcsd_fixed"; |
| regulator-min-microvolt = <3300000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-always-on; |
| }; |
| }; |
| |
| /* The MAC provides internal delay for the transmit path ONLY, which is enabled |
| * provided no -id/-txid/-rxid suffix is provided to "phy-mode". |
| * |
| * The receive path is delayed at the PHY. The recommended register settings |
| * are 0xf0 for the control bits, and 0x7777 for the data bits. However, the |
| * conversion code in the kernel lies: the PHY's registers are 120 ps per tap, |
| * and the kernel assumes 200 ps per tap. So we have fudged the numbers here to |
| * obtain the correct register settings. |
| */ |
| &mac { dual_emac = <1>; }; |
| &cpsw_emac0 { |
| phy-handle = <ðphy0>; |
| phy-mode = "rgmii"; |
| dual_emac_res_vlan = <1>; |
| }; |
| &cpsw_emac1 { |
| phy-handle = <ðphy1>; |
| phy-mode = "rgmii"; |
| dual_emac_res_vlan = <2>; |
| }; |
| |
| &davinci_mdio { |
| ethphy0: ethernet-phy@0 { |
| reg = <0x2>; |
| |
| rxc-skew-ps = <3000>; |
| rxdv-skew-ps = <0>; |
| |
| rxd3-skew-ps = <0>; |
| rxd2-skew-ps = <0>; |
| rxd1-skew-ps = <0>; |
| rxd0-skew-ps = <0>; |
| |
| phy-reset-gpios = <&gpio2 8 GPIO_ACTIVE_LOW>; |
| }; |
| |
| ethphy1: ethernet-phy@1 { |
| reg = <0x1>; |
| |
| rxc-skew-ps = <3000>; |
| rxdv-skew-ps = <0>; |
| |
| rxd3-skew-ps = <0>; |
| rxd2-skew-ps = <0>; |
| rxd1-skew-ps = <0>; |
| rxd0-skew-ps = <0>; |
| |
| phy-reset-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; |
| }; |
| }; |
| |
| &mmc1 { status = "disabled"; }; |
| &mmc2 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&mmc2_pins>; |
| vmmc-supply = <&vmmcsd_fixed>; |
| bus-width = <4>; |
| }; |
| &mmc3 { status = "disabled"; }; |
| |
| &i2c1 { |
| /* Most I2C activity happens through this port, with the sole exception |
| * of the backplane. Since there are multiply assigned addresses, the |
| * "i2c-mux-idle-disconnect" is important. |
| */ |
| |
| pca9548@70 { |
| compatible = "nxp,pca9548"; |
| reg = <0x70>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| i2c-mux-idle-disconnect; |
| |
| i2c@0 { |
| /* FMC A */ |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0>; |
| }; |
| |
| i2c@1 { |
| /* FMC B */ |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <1>; |
| }; |
| |
| i2c@2 { |
| /* QSFP A */ |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <2>; |
| }; |
| |
| i2c@3 { |
| /* QSFP B */ |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <3>; |
| }; |
| |
| i2c@4 { |
| /* SFP */ |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <4>; |
| }; |
| |
| i2c@5 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <5>; |
| |
| ina230@40 { compatible = "ti,ina230"; reg = <0x40>; shunt-resistor = <5000>; }; |
| ina230@41 { compatible = "ti,ina230"; reg = <0x41>; shunt-resistor = <5000>; }; |
| ina230@42 { compatible = "ti,ina230"; reg = <0x42>; shunt-resistor = <5000>; }; |
| |
| ina230@44 { compatible = "ti,ina230"; reg = <0x44>; shunt-resistor = <5000>; }; |
| ina230@45 { compatible = "ti,ina230"; reg = <0x45>; shunt-resistor = <5000>; }; |
| ina230@46 { compatible = "ti,ina230"; reg = <0x46>; shunt-resistor = <5000>; }; |
| |
| ina230@47 { compatible = "ti,ina230"; reg = <0x47>; shunt-resistor = <5500>; }; |
| ina230@48 { compatible = "ti,ina230"; reg = <0x48>; shunt-resistor = <2360>; }; |
| ina230@49 { compatible = "ti,ina230"; reg = <0x49>; shunt-resistor = <2360>; }; |
| ina230@43 { compatible = "ti,ina230"; reg = <0x43>; shunt-resistor = <2360>; }; |
| ina230@4b { compatible = "ti,ina230"; reg = <0x4b>; shunt-resistor = <5500>; }; |
| ina230@4c { compatible = "ti,ina230"; reg = <0x4c>; shunt-resistor = <2360>; }; |
| ina230@4d { compatible = "ti,ina230"; reg = <0x4d>; shunt-resistor = <770>; }; |
| ina230@4e { compatible = "ti,ina230"; reg = <0x4e>; shunt-resistor = <770>; }; |
| ina230@4f { compatible = "ti,ina230"; reg = <0x4f>; shunt-resistor = <770>; }; |
| }; |
| |
| i2c@6 { |
| /* Backplane */ |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <6>; |
| }; |
| |
| i2c@7 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <7>; |
| |
| u41: pca9575@20 { |
| compatible = "nxp,pca9575"; |
| reg = <0x20>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| |
| gpio-line-names = |
| "FMCA_EN_12V0", "FMCA_EN_3V3", "FMCA_EN_VADJ", "FMCA_PG_M2C", |
| "FMCA_PG_C2M", "FMCA_PRSNT_M2C_L", "FMCA_CLK_DIR", "SFP_LOS", |
| "FMCB_EN_12V0", "FMCB_EN_3V3", "FMCB_EN_VADJ", "FMCB_PG_M2C", |
| "FMCB_PG_C2M", "FMCB_PRSNT_M2C_L", "FMCB_CLK_DIR", "SFP_ModPrsL"; |
| reset_gpios = <&gpio2 11 GPIO_ACTIVE_LOW>; |
| }; |
| |
| u42: pca9575@21 { |
| compatible = "nxp,pca9575"; |
| reg = <0x21>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| gpio-line-names = |
| "QSFPA_ModPrsL", "QSFPA_IntL", "QSFPA_ResetL", "QSFPA_ModSelL", |
| "QSFPA_LPMode", "QSFPB_ModPrsL", "QSFPB_IntL", "QSFPB_ResetL", |
| "SFP_TxFault", "SFP_TxDisable", "SFP_RS0", "SFP_RS1", |
| "QSFPB_ModSelL", "QSFPB_LPMode", "SEL_SFP", "ARM_MR"; |
| reset_gpios = <&gpio2 11 GPIO_ACTIVE_LOW>; |
| }; |
| |
| u48: pca9575@22 { |
| compatible = "nxp,pca9575"; |
| reg=<0x22>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| |
| sw-gpios = <&u48 0 0>, <&u48 1 0>, <&u48 2 0>, <&u48 3 0>, |
| <&u48 4 0>, <&u48 5 0>, <&u48 6 0>, <&u48 7 0>; |
| led-gpios = <&u48 7 0>, <&u48 6 0>, <&u48 5 0>, <&u48 4 0>, |
| <&u48 3 0>, <&u48 2 0>, <&u48 1 0>, <&u48 0 0>; |
| |
| gpio-line-names = |
| "GP_SW1", "GP_SW2", "GP_SW3", "GP_SW4", |
| "GP_SW5", "GP_SW6", "GP_SW7", "GP_SW8", |
| "GP_LED8", "GP_LED7", "GP_LED6", "GP_LED5", |
| "GP_LED4", "GP_LED3", "GP_LED2", "GP_LED1"; |
| reset_gpios = <&gpio2 11 GPIO_ACTIVE_LOW>; |
| }; |
| |
| u59: pca9575@23 { |
| compatible = "nxp,pca9575"; |
| reg=<0x23>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| gpio-line-names = |
| "GP_LED9", "GP_LED10", "GP_LED11", "GP_LED12", |
| "GTX1V8PowerFault", "PHYAPowerFault", "PHYBPowerFault", "ArmPowerFault", |
| "BP_SLOW_GPIO0", "BP_SLOW_GPIO1", "BP_SLOW_GPIO2", "BP_SLOW_GPIO3", |
| "BP_SLOW_GPIO4", "BP_SLOW_GPIO5", "__unused_u59_p16", "__unused_u59_p17"; |
| reset_gpios = <&gpio2 11 GPIO_ACTIVE_LOW>; |
| }; |
| |
| tmp100@48 { compatible = "ti,tmp100"; reg = <0x48>; }; |
| tmp100@4a { compatible = "ti,tmp100"; reg = <0x4a>; }; |
| tmp100@4b { compatible = "ti,tmp100"; reg = <0x4b>; }; |
| tmp100@4c { compatible = "ti,tmp100"; reg = <0x4c>; }; |
| |
| /* EEPROM bank and serial number are treated as separate devices */ |
| at24c01@57 { compatible = "atmel,24c01"; reg = <0x57>; }; |
| at24cs01@5f { compatible = "atmel,24cs01"; reg = <0x5f>; }; |
| }; |
| }; |
| }; |
| |
| &i2c2 { |
| pca9548@71 { |
| compatible = "nxp,pca9548"; |
| reg = <0x71>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| i2c@6 { |
| /* Backplane */ |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <6>; |
| multi-master; |
| |
| /* All backplanes should have this -- it's how we know they're there. */ |
| at24c08@54 { compatible="atmel,24c08"; reg=<0x54>; }; |
| at24cs08@5c { compatible="atmel,24cs08"; reg=<0x5c>; }; |
| |
| /* 16 slot backplane */ |
| tmp421@4d { compatible="ti,tmp421"; reg=<0x4d>; }; |
| tmp421@4e { compatible="ti,tmp421"; reg=<0x4e>; }; |
| ina230@40 { compatible = "ti,ina230"; reg = <0x40>; shunt-resistor = <2360>; }; |
| amc6821@18 { compatible = "ti,amc6821"; reg = <0x18>; }; |
| |
| /* Single slot backplane */ |
| }; |
| }; |
| }; |
| |
| &pincntl { |
| mmc2_pins: pinmux_mmc2_pins { |
| pinctrl-single,pins = < |
| DM814X_IOPAD(0x0800, PIN_INPUT | 0x1) /* SD1_CLK */ |
| DM814X_IOPAD(0x0804, PIN_INPUT_PULLUP | 0x1) /* SD1_CMD */ |
| DM814X_IOPAD(0x0808, PIN_INPUT_PULLUP | 0x1) /* SD1_DAT[0] */ |
| DM814X_IOPAD(0x080c, PIN_INPUT_PULLUP | 0x1) /* SD1_DAT[1] */ |
| DM814X_IOPAD(0x0810, PIN_INPUT_PULLUP | 0x1) /* SD1_DAT[2] */ |
| DM814X_IOPAD(0x0814, PIN_INPUT_PULLUP | 0x1) /* SD1_DAT[3] */ |
| DM814X_IOPAD(0x0924, PIN_INPUT_PULLUP | 0x40) /* SD1_POW */ |
| DM814X_IOPAD(0x0928, PIN_INPUT | 0x40) /* SD1_SDWP */ |
| DM814X_IOPAD(0x093C, PIN_INPUT | 0x2) /* SD1_SDCD */ |
| >; |
| }; |
| |
| usb0_pins: pinmux_usb0_pins { |
| pinctrl-single,pins = < |
| DM814X_IOPAD(0x0c34, PIN_OUTPUT | 0x1) /* USB0_DRVVBUS */ |
| >; |
| }; |
| |
| usb1_pins: pinmux_usb1_pins { |
| pinctrl-single,pins = < |
| DM814X_IOPAD(0x0834, PIN_OUTPUT | 0x80) /* USB1_DRVVBUS */ |
| >; |
| }; |
| |
| gpio1_pins: pinmux_gpio1_pins { |
| pinctrl-single,pins = < |
| DM814X_IOPAD(0x081c, PIN_OUTPUT | 0x80) /* PROGRAM_B */ |
| DM814X_IOPAD(0x0820, PIN_INPUT | 0x80) /* INIT_B */ |
| DM814X_IOPAD(0x0824, PIN_INPUT | 0x80) /* DONE */ |
| |
| DM814X_IOPAD(0x0838, PIN_INPUT_PULLUP | 0x80) /* FMCA_TMS */ |
| DM814X_IOPAD(0x083c, PIN_INPUT_PULLUP | 0x80) /* FMCA_TCK */ |
| DM814X_IOPAD(0x0898, PIN_INPUT_PULLUP | 0x80) /* FMCA_TDO */ |
| DM814X_IOPAD(0x089c, PIN_INPUT_PULLUP | 0x80) /* FMCA_TDI */ |
| DM814X_IOPAD(0x08ac, PIN_INPUT_PULLUP | 0x80) /* FMCA_TRST */ |
| |
| DM814X_IOPAD(0x08b0, PIN_INPUT_PULLUP | 0x80) /* FMCB_TMS */ |
| DM814X_IOPAD(0x0a88, PIN_INPUT_PULLUP | 0x80) /* FMCB_TCK */ |
| DM814X_IOPAD(0x0a8c, PIN_INPUT_PULLUP | 0x80) /* FMCB_TDO */ |
| DM814X_IOPAD(0x08bc, PIN_INPUT_PULLUP | 0x80) /* FMCB_TDI */ |
| DM814X_IOPAD(0x0a94, PIN_INPUT_PULLUP | 0x80) /* FMCB_TRST */ |
| |
| DM814X_IOPAD(0x08d4, PIN_INPUT_PULLUP | 0x80) /* FPGA_TMS */ |
| DM814X_IOPAD(0x0aa8, PIN_INPUT_PULLUP | 0x80) /* FPGA_TCK */ |
| DM814X_IOPAD(0x0adc, PIN_INPUT_PULLUP | 0x80) /* FPGA_TDO */ |
| DM814X_IOPAD(0x0ab0, PIN_INPUT_PULLUP | 0x80) /* FPGA_TDI */ |
| >; |
| }; |
| |
| gpio2_pins: pinmux_gpio2_pins { |
| pinctrl-single,pins = < |
| DM814X_IOPAD(0x090c, PIN_INPUT_PULLUP | 0x80) /* PHY A IRQ */ |
| DM814X_IOPAD(0x0910, PIN_INPUT_PULLUP | 0x80) /* PHY A RESET */ |
| DM814X_IOPAD(0x08f4, PIN_INPUT_PULLUP | 0x80) /* PHY B IRQ */ |
| DM814X_IOPAD(0x08f8, PIN_INPUT_PULLUP | 0x80) /* PHY B RESET */ |
| |
| //DM814X_IOPAD(0x0a14, PIN_INPUT_PULLUP | 0x80) /* ARM IRQ */ |
| //DM814X_IOPAD(0x0900, PIN_INPUT | 0x80) /* GPIO IRQ */ |
| DM814X_IOPAD(0x0a2c, PIN_INPUT_PULLUP | 0x80) /* GPIO RESET */ |
| >; |
| }; |
| |
| gpio4_pins: pinmux_gpio4_pins { |
| pinctrl-single,pins = < |
| /* The PLL doesn't react well to the SPI controller reset, so |
| * we force the CS lines to pull up as GPIOs until we're ready. |
| * See https://e2e.ti.com/support/processors/f/791/t/276011?Linux-support-for-AM3874-DM8148-in-Arago-linux-omap3 |
| */ |
| DM814X_IOPAD(0x0b3c, PIN_INPUT_PULLUP | 0x80) /* BP_ARM_GPIO0 */ |
| DM814X_IOPAD(0x0b40, PIN_INPUT_PULLUP | 0x80) /* BP_ARM_GPIO1 */ |
| DM814X_IOPAD(0x0b44, PIN_INPUT_PULLUP | 0x80) /* BP_ARM_GPIO2 */ |
| DM814X_IOPAD(0x0b48, PIN_INPUT_PULLUP | 0x80) /* BP_ARM_GPIO3 */ |
| DM814X_IOPAD(0x0b4c, PIN_INPUT_PULLUP | 0x80) /* BP_ARM_GPIO4 */ |
| DM814X_IOPAD(0x0b50, PIN_INPUT_PULLUP | 0x80) /* BP_ARM_GPIO5 */ |
| >; |
| }; |
| |
| spi2_pins: pinmux_spi2_pins { |
| pinctrl-single,pins = < |
| DM814X_IOPAD(0x0950, PIN_INPUT_PULLUP | 0x80) /* PLL SPI CS1 as GPIO */ |
| DM814X_IOPAD(0x0818, PIN_INPUT_PULLUP | 0x80) /* PLL SPI CS2 as GPIO */ |
| >; |
| }; |
| |
| spi4_pins: pinmux_spi4_pins { |
| pinctrl-single,pins = < |
| DM814X_IOPAD(0x0a7c, 0x20) |
| DM814X_IOPAD(0x0b74, 0x20) |
| DM814X_IOPAD(0x0b78, PIN_OUTPUT | 0x20) |
| DM814X_IOPAD(0x0b7c, PIN_OUTPUT_PULLDOWN | 0x20) |
| DM814X_IOPAD(0x0b80, PIN_INPUT | 0x20) |
| >; |
| }; |
| }; |
| |
| &gpio1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&gpio1_pins>; |
| gpio-line-names = |
| "", "PROGRAM_B", "INIT_B", "DONE", /* 0-3 */ |
| "", "", "", "", /* 4-7 */ |
| "FMCA_TMS", "FMCA_TCK", "FMCA_TDO", "FMCA_TDI", /* 8-11 */ |
| "", "", "", "FMCA_TRST", /* 12-15 */ |
| "FMCB_TMS", "FMCB_TCK", "FMCB_TDO", "FMCB_TDI", /* 16-19 */ |
| "FMCB_TRST", "", "", "", /* 20-23 */ |
| "FPGA_TMS", "FPGA_TCK", "FPGA_TDO", "FPGA_TDI", /* 24-27 */ |
| "", "", "", ""; /* 28-31 */ |
| }; |
| |
| &gpio2 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&gpio2_pins>; |
| gpio-line-names = |
| "PHYA_IRQ_N", "PHYA_RESET_N", "", "", /* 0-3 */ |
| "", "", "", "PHYB_IRQ_N", /* 4-7 */ |
| "PHYB_RESET_N", "ARM_IRQ", "GPIO_IRQ", ""; /* 8-11 */ |
| }; |
| |
| &gpio3 { |
| pinctrl-names = "default"; |
| /*pinctrl-0 = <&gpio3_pins>;*/ |
| gpio-line-names = |
| "", "", "ARMClkSel0", "", /* 0-3 */ |
| "EnFPGARef", "", "", "ARMClkSel1"; /* 4-7 */ |
| }; |
| |
| &gpio4 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&gpio4_pins>; |
| gpio-line-names = |
| "BP_ARM_GPIO0", "BP_ARM_GPIO1", "BP_ARM_GPIO2", "BP_ARM_GPIO3", |
| "BP_ARM_GPIO4", "BP_ARM_GPIO5"; |
| }; |
| |
| &usb0 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&usb0_pins>; |
| dr_mode = "host"; |
| }; |
| |
| &usb1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&usb1_pins>; |
| dr_mode = "host"; |
| }; |
| |
| &mcspi1 { |
| s25fl256@0 { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| compatible = "jedec,spi-nor"; |
| reg = <0>; |
| spi-max-frequency = <40000000>; |
| |
| fsbl@0 { |
| /* 256 kB */ |
| label = "U-Boot-min"; |
| reg = <0 0x40000>; |
| }; |
| ssbl@1 { |
| /* 512 kB */ |
| label = "U-Boot"; |
| reg = <0x40000 0x80000>; |
| }; |
| bootenv@2 { |
| /* 256 kB */ |
| label = "U-Boot Env"; |
| reg = <0xc0000 0x40000>; |
| }; |
| kernel@3 { |
| /* 4 MB */ |
| label = "Kernel"; |
| reg = <0x100000 0x400000>; |
| }; |
| ipmi@4 { |
| label = "IPMI FRU"; |
| reg = <0x500000 0x40000>; |
| }; |
| fs@5 { |
| label = "File System"; |
| reg = <0x540000 0x1ac0000>; |
| }; |
| }; |
| }; |
| |
| &mcspi3 { |
| /* DMA event numbers stolen from MCASP */ |
| dmas = <&edma_xbar 8 0 16 &edma_xbar 9 0 17 |
| &edma_xbar 10 0 18 &edma_xbar 11 0 19>; |
| dma-names = "tx0", "rx0", "tx1", "rx1"; |
| }; |
| |
| &mcspi4 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&spi4_pins>; |
| |
| /* DMA event numbers stolen from MCASP, MCBSP */ |
| dmas = <&edma_xbar 12 0 20 &edma_xbar 13 0 21>; |
| dma-names = "tx0", "rx0"; |
| }; |
