Documentation/devicetree/bindings/clock/mediatek,mtmips-sysc.yaml

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/mediatek,mtmips-sysc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: MTMIPS SoCs System Controller

maintainers:
  - Sergio Paracuellos <sergio.paracuellos@gmail.com>

description: |
  MediaTek MIPS and Ralink SoCs provides a system controller to allow
  to access to system control registers. These registers include clock
  and reset related ones so this node is both clock and reset provider
  for the rest of the world.

  These SoCs have an XTAL from where the cpu clock is
  provided as well as derived clocks for the bus and the peripherals.

properties:
  compatible:
    items:
      - enum:
          - ralink,mt7620-sysc
          - ralink,mt7628-sysc
          - ralink,mt7688-sysc
          - ralink,rt2880-sysc
          - ralink,rt3050-sysc
          - ralink,rt3052-sysc
          - ralink,rt3352-sysc
          - ralink,rt3883-sysc
          - ralink,rt5350-sysc
      - const: syscon

  reg:
    maxItems: 1

  '#clock-cells':
    description:
      The first cell indicates the clock number.
    const: 1

  '#reset-cells':
    description:
      The first cell indicates the reset bit within the register.
    const: 1

required:
  - compatible
  - reg
  - '#clock-cells'
  - '#reset-cells'

additionalProperties: false

examples:
  - |
    syscon@0 {
      compatible = "ralink,rt5350-sysc", "syscon";
      reg = <0x0 0x100>;
      #clock-cells = <1>;
      #reset-cells = <1>;
    };