| # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause |
| %YAML 1.2 |
| --- |
| $id: http://devicetree.org/schemas/clock/starfive,jh7110-voutcrg.yaml# |
| $schema: http://devicetree.org/meta-schemas/core.yaml# |
| |
| title: StarFive JH7110 Video-Output Clock and Reset Generator |
| |
| maintainers: |
| - Xingyu Wu <xingyu.wu@starfivetech.com> |
| |
| properties: |
| compatible: |
| const: starfive,jh7110-voutcrg |
| |
| reg: |
| maxItems: 1 |
| |
| clocks: |
| items: |
| - description: Vout Top core |
| - description: Vout Top Ahb |
| - description: Vout Top Axi |
| - description: Vout Top HDMI MCLK |
| - description: I2STX0 BCLK |
| - description: external HDMI pixel |
| |
| clock-names: |
| items: |
| - const: vout_src |
| - const: vout_top_ahb |
| - const: vout_top_axi |
| - const: vout_top_hdmitx0_mclk |
| - const: i2stx0_bclk |
| - const: hdmitx0_pixelclk |
| |
| resets: |
| maxItems: 1 |
| description: Vout Top core |
| |
| '#clock-cells': |
| const: 1 |
| description: |
| See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices. |
| |
| '#reset-cells': |
| const: 1 |
| description: |
| See <dt-bindings/reset/starfive,jh7110-crg.h> for valid indices. |
| |
| power-domains: |
| maxItems: 1 |
| description: |
| Vout domain power |
| |
| required: |
| - compatible |
| - reg |
| - clocks |
| - clock-names |
| - resets |
| - '#clock-cells' |
| - '#reset-cells' |
| - power-domains |
| |
| additionalProperties: false |
| |
| examples: |
| - | |
| #include <dt-bindings/clock/starfive,jh7110-crg.h> |
| #include <dt-bindings/power/starfive,jh7110-pmu.h> |
| #include <dt-bindings/reset/starfive,jh7110-crg.h> |
| |
| voutcrg: clock-controller@295C0000 { |
| compatible = "starfive,jh7110-voutcrg"; |
| reg = <0x295C0000 0x10000>; |
| clocks = <&syscrg JH7110_SYSCLK_VOUT_SRC>, |
| <&syscrg JH7110_SYSCLK_VOUT_TOP_AHB>, |
| <&syscrg JH7110_SYSCLK_VOUT_TOP_AXI>, |
| <&syscrg JH7110_SYSCLK_VOUT_TOP_HDMITX0_MCLK>, |
| <&syscrg JH7110_SYSCLK_I2STX0_BCLK>, |
| <&hdmitx0_pixelclk>; |
| clock-names = "vout_src", "vout_top_ahb", |
| "vout_top_axi", "vout_top_hdmitx0_mclk", |
| "i2stx0_bclk", "hdmitx0_pixelclk"; |
| resets = <&syscrg JH7110_SYSRST_VOUT_TOP_SRC>; |
| #clock-cells = <1>; |
| #reset-cells = <1>; |
| power-domains = <&pwrc JH7110_PD_VOUT>; |
| }; |
