| # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| # Copyright (C) Sunplus Co., Ltd. 2021 |
| %YAML 1.2 |
| --- |
| $id: http://devicetree.org/schemas/interrupt-controller/sunplus,sp7021-intc.yaml# |
| $schema: http://devicetree.org/meta-schemas/core.yaml# |
| |
| title: Sunplus SP7021 SoC Interrupt Controller |
| |
| maintainers: |
| - Qin Jian <qinjian@cqplus1.com> |
| |
| properties: |
| compatible: |
| items: |
| - const: sunplus,sp7021-intc |
| |
| reg: |
| maxItems: 2 |
| description: |
| Specifies base physical address(s) and size of the controller regs. |
| The 1st region include type/polarity/priority/mask regs. |
| The 2nd region include clear/masked_ext0/masked_ext1/group regs. |
| |
| interrupt-controller: true |
| |
| "#interrupt-cells": |
| const: 2 |
| description: |
| The first cell is the IRQ number, the second cell is the trigger |
| type as defined in interrupt.txt in this directory. |
| |
| interrupts: |
| maxItems: 2 |
| description: |
| EXT_INT0 & EXT_INT1, 2 interrupts references to primary interrupt |
| controller. |
| |
| required: |
| - compatible |
| - reg |
| - interrupt-controller |
| - "#interrupt-cells" |
| - interrupts |
| |
| additionalProperties: false |
| |
| examples: |
| - | |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| |
| intc: interrupt-controller@9c000780 { |
| compatible = "sunplus,sp7021-intc"; |
| reg = <0x9c000780 0x80>, <0x9c000a80 0x80>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| interrupt-parent = <&gic>; |
| interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, /* EXT_INT0 */ |
| <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; /* EXT_INT1 */ |
| }; |
| |
| ... |
