| # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) |
| |
| %YAML 1.2 |
| --- |
| $id: http://devicetree.org/schemas/media/qcom,sm8250-camss.yaml# |
| $schema: http://devicetree.org/meta-schemas/core.yaml# |
| |
| title: Qualcomm CAMSS ISP |
| |
| maintainers: |
| - Robert Foss <robert.foss@linaro.org> |
| |
| description: | |
| The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms. |
| |
| properties: |
| compatible: |
| const: qcom,sm8250-camss |
| |
| clocks: |
| minItems: 37 |
| maxItems: 37 |
| |
| clock-names: |
| items: |
| - const: cam_ahb_clk |
| - const: cam_hf_axi |
| - const: cam_sf_axi |
| - const: camnoc_axi |
| - const: camnoc_axi_src |
| - const: core_ahb |
| - const: cpas_ahb |
| - const: csiphy0 |
| - const: csiphy0_timer |
| - const: csiphy1 |
| - const: csiphy1_timer |
| - const: csiphy2 |
| - const: csiphy2_timer |
| - const: csiphy3 |
| - const: csiphy3_timer |
| - const: csiphy4 |
| - const: csiphy4_timer |
| - const: csiphy5 |
| - const: csiphy5_timer |
| - const: slow_ahb_src |
| - const: vfe0_ahb |
| - const: vfe0_axi |
| - const: vfe0 |
| - const: vfe0_cphy_rx |
| - const: vfe0_csid |
| - const: vfe0_areg |
| - const: vfe1_ahb |
| - const: vfe1_axi |
| - const: vfe1 |
| - const: vfe1_cphy_rx |
| - const: vfe1_csid |
| - const: vfe1_areg |
| - const: vfe_lite_ahb |
| - const: vfe_lite_axi |
| - const: vfe_lite |
| - const: vfe_lite_cphy_rx |
| - const: vfe_lite_csid |
| |
| interrupts: |
| minItems: 14 |
| maxItems: 14 |
| |
| interrupt-names: |
| items: |
| - const: csiphy0 |
| - const: csiphy1 |
| - const: csiphy2 |
| - const: csiphy3 |
| - const: csiphy4 |
| - const: csiphy5 |
| - const: csid0 |
| - const: csid1 |
| - const: csid2 |
| - const: csid3 |
| - const: vfe0 |
| - const: vfe1 |
| - const: vfe_lite0 |
| - const: vfe_lite1 |
| |
| iommus: |
| minItems: 8 |
| maxItems: 8 |
| |
| interconnects: |
| minItems: 4 |
| maxItems: 4 |
| |
| interconnect-names: |
| items: |
| - const: cam_ahb |
| - const: cam_hf_0_mnoc |
| - const: cam_sf_0_mnoc |
| - const: cam_sf_icp_mnoc |
| |
| power-domains: |
| items: |
| - description: IFE0 GDSC - Image Front End, Global Distributed Switch Controller. |
| - description: IFE1 GDSC - Image Front End, Global Distributed Switch Controller. |
| - description: Titan GDSC - Titan ISP Block, Global Distributed Switch Controller. |
| |
| ports: |
| $ref: /schemas/graph.yaml#/properties/ports |
| |
| description: |
| CSI input ports. |
| |
| properties: |
| port@0: |
| $ref: /schemas/graph.yaml#/$defs/port-base |
| unevaluatedProperties: false |
| description: |
| Input port for receiving CSI data. |
| |
| properties: |
| endpoint: |
| $ref: video-interfaces.yaml# |
| unevaluatedProperties: false |
| |
| properties: |
| clock-lanes: |
| maxItems: 1 |
| |
| data-lanes: |
| minItems: 1 |
| maxItems: 4 |
| |
| required: |
| - clock-lanes |
| - data-lanes |
| |
| port@1: |
| $ref: /schemas/graph.yaml#/$defs/port-base |
| unevaluatedProperties: false |
| description: |
| Input port for receiving CSI data. |
| |
| properties: |
| endpoint: |
| $ref: video-interfaces.yaml# |
| unevaluatedProperties: false |
| |
| properties: |
| clock-lanes: |
| maxItems: 1 |
| |
| data-lanes: |
| minItems: 1 |
| maxItems: 4 |
| |
| required: |
| - clock-lanes |
| - data-lanes |
| |
| port@2: |
| $ref: /schemas/graph.yaml#/$defs/port-base |
| unevaluatedProperties: false |
| description: |
| Input port for receiving CSI data. |
| |
| properties: |
| endpoint: |
| $ref: video-interfaces.yaml# |
| unevaluatedProperties: false |
| |
| properties: |
| clock-lanes: |
| maxItems: 1 |
| |
| data-lanes: |
| minItems: 1 |
| maxItems: 4 |
| |
| required: |
| - clock-lanes |
| - data-lanes |
| |
| port@3: |
| $ref: /schemas/graph.yaml#/$defs/port-base |
| unevaluatedProperties: false |
| description: |
| Input port for receiving CSI data. |
| |
| properties: |
| endpoint: |
| $ref: video-interfaces.yaml# |
| unevaluatedProperties: false |
| |
| properties: |
| clock-lanes: |
| maxItems: 1 |
| |
| data-lanes: |
| minItems: 1 |
| maxItems: 4 |
| |
| required: |
| - clock-lanes |
| - data-lanes |
| |
| port@4: |
| $ref: /schemas/graph.yaml#/$defs/port-base |
| unevaluatedProperties: false |
| description: |
| Input port for receiving CSI data. |
| |
| properties: |
| endpoint: |
| $ref: video-interfaces.yaml# |
| unevaluatedProperties: false |
| |
| properties: |
| clock-lanes: |
| maxItems: 1 |
| |
| data-lanes: |
| minItems: 1 |
| maxItems: 4 |
| |
| required: |
| - clock-lanes |
| - data-lanes |
| |
| port@5: |
| $ref: /schemas/graph.yaml#/$defs/port-base |
| unevaluatedProperties: false |
| description: |
| Input port for receiving CSI data. |
| |
| properties: |
| endpoint: |
| $ref: video-interfaces.yaml# |
| unevaluatedProperties: false |
| |
| properties: |
| clock-lanes: |
| maxItems: 1 |
| |
| data-lanes: |
| minItems: 1 |
| maxItems: 4 |
| |
| required: |
| - clock-lanes |
| - data-lanes |
| |
| reg: |
| minItems: 10 |
| maxItems: 10 |
| |
| reg-names: |
| items: |
| - const: csiphy0 |
| - const: csiphy1 |
| - const: csiphy2 |
| - const: csiphy3 |
| - const: csiphy4 |
| - const: csiphy5 |
| - const: vfe0 |
| - const: vfe1 |
| - const: vfe_lite0 |
| - const: vfe_lite1 |
| |
| vdda-phy-supply: |
| description: |
| Phandle to a regulator supply to PHY core block. |
| |
| vdda-pll-supply: |
| description: |
| Phandle to 1.8V regulator supply to PHY refclk pll block. |
| |
| required: |
| - clock-names |
| - clocks |
| - compatible |
| - interconnects |
| - interconnect-names |
| - interrupts |
| - interrupt-names |
| - iommus |
| - power-domains |
| - reg |
| - reg-names |
| - vdda-phy-supply |
| - vdda-pll-supply |
| |
| additionalProperties: false |
| |
| examples: |
| - | |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| #include <dt-bindings/clock/qcom,camcc-sm8250.h> |
| #include <dt-bindings/interconnect/qcom,sm8250.h> |
| #include <dt-bindings/clock/qcom,gcc-sm8250.h> |
| #include <dt-bindings/power/qcom-rpmpd.h> |
| |
| soc { |
| #address-cells = <2>; |
| #size-cells = <2>; |
| |
| camss: camss@ac6a000 { |
| compatible = "qcom,sm8250-camss"; |
| |
| reg = <0 0xac6a000 0 0x2000>, |
| <0 0xac6c000 0 0x2000>, |
| <0 0xac6e000 0 0x1000>, |
| <0 0xac70000 0 0x1000>, |
| <0 0xac72000 0 0x1000>, |
| <0 0xac74000 0 0x1000>, |
| <0 0xacb4000 0 0xd000>, |
| <0 0xacc3000 0 0xd000>, |
| <0 0xacd9000 0 0x2200>, |
| <0 0xacdb200 0 0x2200>; |
| reg-names = "csiphy0", |
| "csiphy1", |
| "csiphy2", |
| "csiphy3", |
| "csiphy4", |
| "csiphy5", |
| "vfe0", |
| "vfe1", |
| "vfe_lite0", |
| "vfe_lite1"; |
| |
| vdda-phy-supply = <&vreg_l5a_0p88>; |
| vdda-pll-supply = <&vreg_l9a_1p2>; |
| |
| interrupts = <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "csiphy0", |
| "csiphy1", |
| "csiphy2", |
| "csiphy3", |
| "csiphy4", |
| "csiphy5", |
| "csid0", |
| "csid1", |
| "csid2", |
| "csid3", |
| "vfe0", |
| "vfe1", |
| "vfe_lite0", |
| "vfe_lite1"; |
| |
| power-domains = <&camcc IFE_0_GDSC>, |
| <&camcc IFE_1_GDSC>, |
| <&camcc TITAN_TOP_GDSC>; |
| |
| clocks = <&gcc GCC_CAMERA_AHB_CLK>, |
| <&gcc GCC_CAMERA_HF_AXI_CLK>, |
| <&gcc GCC_CAMERA_SF_AXI_CLK>, |
| <&camcc CAM_CC_CAMNOC_AXI_CLK>, |
| <&camcc CAM_CC_CAMNOC_AXI_CLK_SRC>, |
| <&camcc CAM_CC_CORE_AHB_CLK>, |
| <&camcc CAM_CC_CPAS_AHB_CLK>, |
| <&camcc CAM_CC_CSIPHY0_CLK>, |
| <&camcc CAM_CC_CSI0PHYTIMER_CLK>, |
| <&camcc CAM_CC_CSIPHY1_CLK>, |
| <&camcc CAM_CC_CSI1PHYTIMER_CLK>, |
| <&camcc CAM_CC_CSIPHY2_CLK>, |
| <&camcc CAM_CC_CSI2PHYTIMER_CLK>, |
| <&camcc CAM_CC_CSIPHY3_CLK>, |
| <&camcc CAM_CC_CSI3PHYTIMER_CLK>, |
| <&camcc CAM_CC_CSIPHY4_CLK>, |
| <&camcc CAM_CC_CSI4PHYTIMER_CLK>, |
| <&camcc CAM_CC_CSIPHY5_CLK>, |
| <&camcc CAM_CC_CSI5PHYTIMER_CLK>, |
| <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, |
| <&camcc CAM_CC_IFE_0_AHB_CLK>, |
| <&camcc CAM_CC_IFE_0_AXI_CLK>, |
| <&camcc CAM_CC_IFE_0_CLK>, |
| <&camcc CAM_CC_IFE_0_CPHY_RX_CLK>, |
| <&camcc CAM_CC_IFE_0_CSID_CLK>, |
| <&camcc CAM_CC_IFE_0_AREG_CLK>, |
| <&camcc CAM_CC_IFE_1_AHB_CLK>, |
| <&camcc CAM_CC_IFE_1_AXI_CLK>, |
| <&camcc CAM_CC_IFE_1_CLK>, |
| <&camcc CAM_CC_IFE_1_CPHY_RX_CLK>, |
| <&camcc CAM_CC_IFE_1_CSID_CLK>, |
| <&camcc CAM_CC_IFE_1_AREG_CLK>, |
| <&camcc CAM_CC_IFE_LITE_AHB_CLK>, |
| <&camcc CAM_CC_IFE_LITE_AXI_CLK>, |
| <&camcc CAM_CC_IFE_LITE_CLK>, |
| <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, |
| <&camcc CAM_CC_IFE_LITE_CSID_CLK>; |
| clock-names = "cam_ahb_clk", |
| "cam_hf_axi", |
| "cam_sf_axi", |
| "camnoc_axi", |
| "camnoc_axi_src", |
| "core_ahb", |
| "cpas_ahb", |
| "csiphy0", |
| "csiphy0_timer", |
| "csiphy1", |
| "csiphy1_timer", |
| "csiphy2", |
| "csiphy2_timer", |
| "csiphy3", |
| "csiphy3_timer", |
| "csiphy4", |
| "csiphy4_timer", |
| "csiphy5", |
| "csiphy5_timer", |
| "slow_ahb_src", |
| "vfe0_ahb", |
| "vfe0_axi", |
| "vfe0", |
| "vfe0_cphy_rx", |
| "vfe0_csid", |
| "vfe0_areg", |
| "vfe1_ahb", |
| "vfe1_axi", |
| "vfe1", |
| "vfe1_cphy_rx", |
| "vfe1_csid", |
| "vfe1_areg", |
| "vfe_lite_ahb", |
| "vfe_lite_axi", |
| "vfe_lite", |
| "vfe_lite_cphy_rx", |
| "vfe_lite_csid"; |
| |
| iommus = <&apps_smmu 0x800 0x400>, |
| <&apps_smmu 0x801 0x400>, |
| <&apps_smmu 0x840 0x400>, |
| <&apps_smmu 0x841 0x400>, |
| <&apps_smmu 0xC00 0x400>, |
| <&apps_smmu 0xC01 0x400>, |
| <&apps_smmu 0xC40 0x400>, |
| <&apps_smmu 0xC41 0x400>; |
| |
| interconnects = <&gem_noc MASTER_AMPSS_M0 &config_noc SLAVE_CAMERA_CFG>, |
| <&mmss_noc MASTER_CAMNOC_HF &mc_virt SLAVE_EBI_CH0>, |
| <&mmss_noc MASTER_CAMNOC_SF &mc_virt SLAVE_EBI_CH0>, |
| <&mmss_noc MASTER_CAMNOC_ICP &mc_virt SLAVE_EBI_CH0>; |
| interconnect-names = "cam_ahb", |
| "cam_hf_0_mnoc", |
| "cam_sf_0_mnoc", |
| "cam_sf_icp_mnoc"; |
| |
| ports { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| }; |
| }; |
| }; |
