| # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) |
| %YAML 1.2 |
| --- |
| $id: http://devicetree.org/schemas/media/renesas,vsp1.yaml# |
| $schema: http://devicetree.org/meta-schemas/core.yaml# |
| |
| title: Renesas VSP Video Processing Engine |
| |
| maintainers: |
| - Laurent Pinchart <laurent.pinchart@ideasonboard.com> |
| |
| description: |
| The VSP is a video processing engine that supports up-/down-scaling, alpha |
| blending, color space conversion and various other image processing features. |
| It can be found in the Renesas R-Car Gen2, R-Car Gen3, RZ/G1, and RZ/G2 SoCs. |
| |
| properties: |
| compatible: |
| oneOf: |
| - enum: |
| - renesas,r9a07g044-vsp2 # RZ/G2L |
| - renesas,vsp1 # R-Car Gen2 and RZ/G1 |
| - renesas,vsp2 # R-Car Gen3 and RZ/G2 |
| - items: |
| - enum: |
| - renesas,r9a07g054-vsp2 # RZ/V2L |
| - const: renesas,r9a07g044-vsp2 # RZ/G2L fallback |
| |
| reg: |
| maxItems: 1 |
| |
| interrupts: |
| maxItems: 1 |
| |
| clocks: true |
| clock-names: true |
| |
| power-domains: |
| maxItems: 1 |
| |
| resets: |
| maxItems: 1 |
| |
| renesas,fcp: |
| $ref: /schemas/types.yaml#/definitions/phandle |
| description: |
| A phandle referencing the FCP that handles memory accesses for the VSP. |
| |
| required: |
| - compatible |
| - reg |
| - interrupts |
| - clocks |
| - power-domains |
| - resets |
| |
| additionalProperties: false |
| |
| allOf: |
| - if: |
| properties: |
| compatible: |
| contains: |
| const: renesas,vsp1 |
| then: |
| properties: |
| renesas,fcp: false |
| else: |
| required: |
| - renesas,fcp |
| |
| - if: |
| properties: |
| compatible: |
| contains: |
| const: renesas,r9a07g044-vsp2 |
| then: |
| properties: |
| clocks: |
| items: |
| - description: Main clock |
| - description: Register access clock |
| - description: Video clock |
| clock-names: |
| items: |
| - const: aclk |
| - const: pclk |
| - const: vclk |
| required: |
| - clock-names |
| else: |
| properties: |
| clocks: |
| maxItems: 1 |
| clock-names: false |
| |
| examples: |
| # R8A7790 (R-Car H2) VSP1-S |
| - | |
| #include <dt-bindings/clock/renesas-cpg-mssr.h> |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| #include <dt-bindings/power/r8a7790-sysc.h> |
| |
| vsp@fe928000 { |
| compatible = "renesas,vsp1"; |
| reg = <0xfe928000 0x8000>; |
| interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 131>; |
| power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; |
| resets = <&cpg 131>; |
| }; |
| |
| # R8A77951 (R-Car H3) VSP2-BC |
| - | |
| #include <dt-bindings/clock/renesas-cpg-mssr.h> |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| #include <dt-bindings/power/r8a7795-sysc.h> |
| |
| vsp@fe920000 { |
| compatible = "renesas,vsp2"; |
| reg = <0xfe920000 0x8000>; |
| interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 624>; |
| power-domains = <&sysc R8A7795_PD_A3VP>; |
| resets = <&cpg 624>; |
| |
| renesas,fcp = <&fcpvb1>; |
| }; |
| ... |
