| # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| %YAML 1.2 |
| --- |
| $id: http://devicetree.org/schemas/pci/xlnx,axi-pcie-host.yaml# |
| $schema: http://devicetree.org/meta-schemas/core.yaml# |
| |
| title: Xilinx AXI PCIe Root Port Bridge |
| |
| maintainers: |
| - Thippeswamy Havalige <thippeswamy.havalige@amd.com> |
| |
| allOf: |
| - $ref: /schemas/pci/pci-host-bridge.yaml# |
| |
| properties: |
| compatible: |
| const: xlnx,axi-pcie-host-1.00.a |
| |
| reg: |
| maxItems: 1 |
| |
| interrupts: |
| maxItems: 1 |
| |
| ranges: |
| items: |
| - description: | |
| ranges for the PCI memory regions (I/O space region is not |
| supported by hardware) |
| |
| "#interrupt-cells": |
| const: 1 |
| |
| interrupt-controller: |
| description: identifies the node as an interrupt controller |
| type: object |
| properties: |
| interrupt-controller: true |
| |
| "#address-cells": |
| const: 0 |
| |
| "#interrupt-cells": |
| const: 1 |
| |
| required: |
| - interrupt-controller |
| - "#address-cells" |
| - "#interrupt-cells" |
| |
| additionalProperties: false |
| |
| required: |
| - compatible |
| - reg |
| - ranges |
| - interrupts |
| - interrupt-map |
| - "#interrupt-cells" |
| - interrupt-controller |
| |
| unevaluatedProperties: false |
| |
| examples: |
| - | |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| #include <dt-bindings/interrupt-controller/irq.h> |
| |
| pcie@50000000 { |
| compatible = "xlnx,axi-pcie-host-1.00.a"; |
| reg = <0x50000000 0x1000000>; |
| #address-cells = <3>; |
| #size-cells = <2>; |
| #interrupt-cells = <1>; |
| device_type = "pci"; |
| interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-map-mask = <0 0 0 7>; |
| interrupt-map = <0 0 0 1 &pcie_intc 1>, |
| <0 0 0 2 &pcie_intc 2>, |
| <0 0 0 3 &pcie_intc 3>, |
| <0 0 0 4 &pcie_intc 4>; |
| ranges = <0x02000000 0 0x60000000 0x60000000 0 0x10000000>; |
| pcie_intc: interrupt-controller { |
| interrupt-controller; |
| #address-cells = <0>; |
| #interrupt-cells = <1>; |
| }; |
| }; |