Documentation/devicetree/bindings/spi/qcom,spi-qpic-snand.yaml

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/spi/qcom,spi-qpic-snand.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm QPIC NAND controller

maintainers:
  - Md sadre Alam <quic_mdalam@quicinc.com>

description:
  The QCOM QPIC-SPI-NAND flash controller is an extended version of
  the QCOM QPIC NAND flash controller. It can work both in serial
  and parallel mode. It supports typical SPI-NAND page cache
  operations in single, dual or quad IO mode with pipelined ECC
  encoding/decoding using the QPIC ECC HW engine.

allOf:
  - $ref: /schemas/spi/spi-controller.yaml#

properties:
  compatible:
    enum:
      - qcom,ipq9574-snand

  reg:
    maxItems: 1

  clocks:
    maxItems: 3

  clock-names:
    items:
      - const: core
      - const: aon
      - const: iom

  dmas:
    items:
      - description: tx DMA channel
      - description: rx DMA channel
      - description: cmd DMA channel

  dma-names:
    items:
      - const: tx
      - const: rx
      - const: cmd

required:
  - compatible
  - reg
  - clocks
  - clock-names

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,ipq9574-gcc.h>
    spi@79b0000 {
        compatible = "qcom,ipq9574-snand";
        reg = <0x1ac00000 0x800>;

        clocks = <&gcc GCC_QPIC_CLK>,
                 <&gcc GCC_QPIC_AHB_CLK>,
                 <&gcc GCC_QPIC_IO_MACRO_CLK>;
        clock-names = "core", "aon", "iom";

        #address-cells = <1>;
        #size-cells = <0>;

        flash@0 {
            compatible = "spi-nand";
            reg = <0>;
            #address-cells = <1>;
            #size-cells = <1>;
            nand-ecc-engine = <&qpic_nand>;
            nand-ecc-strength = <4>;
            nand-ecc-step-size = <512>;
        };
    };