| // SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
| // Copyright (C) 2020 Arm Ltd. |
| // based on the H6 dtsi, which is: |
| // Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io> |
| |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| #include <dt-bindings/clock/sun50i-h616-ccu.h> |
| #include <dt-bindings/clock/sun50i-h6-r-ccu.h> |
| #include <dt-bindings/clock/sun6i-rtc.h> |
| #include <dt-bindings/reset/sun50i-h616-ccu.h> |
| #include <dt-bindings/reset/sun50i-h6-r-ccu.h> |
| #include <dt-bindings/thermal/thermal.h> |
| |
| / { |
| interrupt-parent = <&gic>; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| cpu0: cpu@0 { |
| compatible = "arm,cortex-a53"; |
| device_type = "cpu"; |
| reg = <0>; |
| enable-method = "psci"; |
| clocks = <&ccu CLK_CPUX>; |
| #cooling-cells = <2>; |
| i-cache-size = <0x8000>; |
| i-cache-line-size = <64>; |
| i-cache-sets = <256>; |
| d-cache-size = <0x8000>; |
| d-cache-line-size = <64>; |
| d-cache-sets = <128>; |
| next-level-cache = <&l2_cache>; |
| }; |
| |
| cpu1: cpu@1 { |
| compatible = "arm,cortex-a53"; |
| device_type = "cpu"; |
| reg = <1>; |
| enable-method = "psci"; |
| clocks = <&ccu CLK_CPUX>; |
| #cooling-cells = <2>; |
| i-cache-size = <0x8000>; |
| i-cache-line-size = <64>; |
| i-cache-sets = <256>; |
| d-cache-size = <0x8000>; |
| d-cache-line-size = <64>; |
| d-cache-sets = <128>; |
| next-level-cache = <&l2_cache>; |
| }; |
| |
| cpu2: cpu@2 { |
| compatible = "arm,cortex-a53"; |
| device_type = "cpu"; |
| reg = <2>; |
| enable-method = "psci"; |
| clocks = <&ccu CLK_CPUX>; |
| #cooling-cells = <2>; |
| i-cache-size = <0x8000>; |
| i-cache-line-size = <64>; |
| i-cache-sets = <256>; |
| d-cache-size = <0x8000>; |
| d-cache-line-size = <64>; |
| d-cache-sets = <128>; |
| next-level-cache = <&l2_cache>; |
| }; |
| |
| cpu3: cpu@3 { |
| compatible = "arm,cortex-a53"; |
| device_type = "cpu"; |
| reg = <3>; |
| enable-method = "psci"; |
| clocks = <&ccu CLK_CPUX>; |
| #cooling-cells = <2>; |
| i-cache-size = <0x8000>; |
| i-cache-line-size = <64>; |
| i-cache-sets = <256>; |
| d-cache-size = <0x8000>; |
| d-cache-line-size = <64>; |
| d-cache-sets = <128>; |
| next-level-cache = <&l2_cache>; |
| }; |
| |
| l2_cache: l2-cache { |
| compatible = "cache"; |
| cache-level = <2>; |
| cache-unified; |
| cache-size = <0x40000>; |
| cache-line-size = <64>; |
| cache-sets = <256>; |
| }; |
| }; |
| |
| reserved-memory { |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| |
| /* |
| * 256 KiB reserved for Trusted Firmware-A (BL31). |
| * This is added by BL31 itself, but some bootloaders fail |
| * to propagate this into the DTB handed to kernels. |
| */ |
| secmon@40000000 { |
| reg = <0x0 0x40000000 0x0 0x40000>; |
| no-map; |
| }; |
| }; |
| |
| osc24M: osc24M-clk { |
| #clock-cells = <0>; |
| compatible = "fixed-clock"; |
| clock-frequency = <24000000>; |
| clock-output-names = "osc24M"; |
| }; |
| |
| pmu { |
| compatible = "arm,cortex-a53-pmu"; |
| interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; |
| }; |
| |
| psci { |
| compatible = "arm,psci-0.2"; |
| method = "smc"; |
| }; |
| |
| timer { |
| compatible = "arm,armv8-timer"; |
| arm,no-tick-in-suspend; |
| interrupts = <GIC_PPI 13 |
| (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, |
| <GIC_PPI 14 |
| (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, |
| <GIC_PPI 11 |
| (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, |
| <GIC_PPI 10 |
| (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; |
| }; |
| |
| soc { |
| compatible = "simple-bus"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0x0 0x0 0x40000000>; |
| |
| crypto: crypto@1904000 { |
| compatible = "allwinner,sun50i-h616-crypto"; |
| reg = <0x01904000 0x800>; |
| interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>, |
| <&ccu CLK_MBUS_CE>, <&rtc CLK_IOSC>; |
| clock-names = "bus", "mod", "ram", "trng"; |
| resets = <&ccu RST_BUS_CE>; |
| }; |
| |
| syscon: syscon@3000000 { |
| compatible = "allwinner,sun50i-h616-system-control"; |
| reg = <0x03000000 0x1000>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges; |
| |
| sram_c: sram@28000 { |
| compatible = "mmio-sram"; |
| reg = <0x00028000 0x30000>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0 0x00028000 0x30000>; |
| }; |
| }; |
| |
| ccu: clock@3001000 { |
| compatible = "allwinner,sun50i-h616-ccu"; |
| reg = <0x03001000 0x1000>; |
| clocks = <&osc24M>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>; |
| clock-names = "hosc", "losc", "iosc"; |
| #clock-cells = <1>; |
| #reset-cells = <1>; |
| }; |
| |
| dma: dma-controller@3002000 { |
| compatible = "allwinner,sun50i-h616-dma", |
| "allwinner,sun50i-a100-dma"; |
| reg = <0x03002000 0x1000>; |
| interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>; |
| clock-names = "bus", "mbus"; |
| dma-channels = <16>; |
| dma-requests = <49>; |
| resets = <&ccu RST_BUS_DMA>; |
| #dma-cells = <1>; |
| }; |
| |
| sid: efuse@3006000 { |
| compatible = "allwinner,sun50i-h616-sid", "allwinner,sun50i-a64-sid"; |
| reg = <0x03006000 0x1000>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| ths_calibration: thermal-sensor-calibration@14 { |
| reg = <0x14 0x8>; |
| }; |
| |
| cpu_speed_grade: cpu-speed-grade@0 { |
| reg = <0x0 2>; |
| }; |
| }; |
| |
| watchdog: watchdog@30090a0 { |
| compatible = "allwinner,sun50i-h616-wdt", |
| "allwinner,sun6i-a31-wdt"; |
| reg = <0x030090a0 0x20>; |
| interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&osc24M>; |
| }; |
| |
| pio: pinctrl@300b000 { |
| compatible = "allwinner,sun50i-h616-pinctrl"; |
| reg = <0x0300b000 0x400>; |
| interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&ccu CLK_APB1>, <&osc24M>, <&rtc CLK_OSC32K>; |
| clock-names = "apb", "hosc", "losc"; |
| gpio-controller; |
| #gpio-cells = <3>; |
| interrupt-controller; |
| #interrupt-cells = <3>; |
| |
| ext_rgmii_pins: rgmii-pins { |
| pins = "PI0", "PI1", "PI2", "PI3", "PI4", |
| "PI5", "PI7", "PI8", "PI9", "PI10", |
| "PI11", "PI12", "PI13", "PI14", "PI15", |
| "PI16"; |
| function = "emac0"; |
| drive-strength = <40>; |
| }; |
| |
| i2c0_pins: i2c0-pins { |
| pins = "PI5", "PI6"; |
| function = "i2c0"; |
| }; |
| |
| i2c3_ph_pins: i2c3-ph-pins { |
| pins = "PH4", "PH5"; |
| function = "i2c3"; |
| }; |
| |
| ir_rx_pin: ir-rx-pin { |
| pins = "PH10"; |
| function = "ir_rx"; |
| }; |
| |
| mmc0_pins: mmc0-pins { |
| pins = "PF0", "PF1", "PF2", "PF3", |
| "PF4", "PF5"; |
| function = "mmc0"; |
| drive-strength = <30>; |
| bias-pull-up; |
| }; |
| |
| /omit-if-no-ref/ |
| mmc1_pins: mmc1-pins { |
| pins = "PG0", "PG1", "PG2", "PG3", |
| "PG4", "PG5"; |
| function = "mmc1"; |
| drive-strength = <30>; |
| bias-pull-up; |
| }; |
| |
| mmc2_pins: mmc2-pins { |
| pins = "PC0", "PC1", "PC5", "PC6", |
| "PC8", "PC9", "PC10", "PC11", |
| "PC13", "PC14", "PC15", "PC16"; |
| function = "mmc2"; |
| drive-strength = <30>; |
| bias-pull-up; |
| }; |
| |
| /omit-if-no-ref/ |
| spi0_pins: spi0-pins { |
| pins = "PC0", "PC2", "PC4"; |
| function = "spi0"; |
| }; |
| |
| /omit-if-no-ref/ |
| spi0_cs0_pin: spi0-cs0-pin { |
| pins = "PC3"; |
| function = "spi0"; |
| }; |
| |
| /omit-if-no-ref/ |
| spi1_pins: spi1-pins { |
| pins = "PH6", "PH7", "PH8"; |
| function = "spi1"; |
| }; |
| |
| /omit-if-no-ref/ |
| spi1_cs0_pin: spi1-cs0-pin { |
| pins = "PH5"; |
| function = "spi1"; |
| }; |
| |
| spdif_tx_pin: spdif-tx-pin { |
| pins = "PH4"; |
| function = "spdif"; |
| }; |
| |
| uart0_ph_pins: uart0-ph-pins { |
| pins = "PH0", "PH1"; |
| function = "uart0"; |
| }; |
| |
| /omit-if-no-ref/ |
| uart1_pins: uart1-pins { |
| pins = "PG6", "PG7"; |
| function = "uart1"; |
| }; |
| |
| /omit-if-no-ref/ |
| uart1_rts_cts_pins: uart1-rts-cts-pins { |
| pins = "PG8", "PG9"; |
| function = "uart1"; |
| }; |
| |
| /omit-if-no-ref/ |
| x32clk_fanout_pin: x32clk-fanout-pin { |
| pins = "PG10"; |
| function = "clock"; |
| }; |
| }; |
| |
| gic: interrupt-controller@3021000 { |
| compatible = "arm,gic-400"; |
| reg = <0x03021000 0x1000>, |
| <0x03022000 0x2000>, |
| <0x03024000 0x2000>, |
| <0x03026000 0x2000>; |
| interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; |
| interrupt-controller; |
| #interrupt-cells = <3>; |
| }; |
| |
| iommu: iommu@30f0000 { |
| compatible = "allwinner,sun50i-h616-iommu"; |
| reg = <0x030f0000 0x10000>; |
| interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&ccu CLK_BUS_IOMMU>; |
| resets = <&ccu RST_BUS_IOMMU>; |
| #iommu-cells = <1>; |
| }; |
| |
| mmc0: mmc@4020000 { |
| compatible = "allwinner,sun50i-h616-mmc", |
| "allwinner,sun50i-a100-mmc"; |
| reg = <0x04020000 0x1000>; |
| clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; |
| clock-names = "ahb", "mmc"; |
| resets = <&ccu RST_BUS_MMC0>; |
| reset-names = "ahb"; |
| interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&mmc0_pins>; |
| status = "disabled"; |
| max-frequency = <150000000>; |
| cap-sd-highspeed; |
| cap-mmc-highspeed; |
| mmc-ddr-3_3v; |
| cap-sdio-irq; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| }; |
| |
| mmc1: mmc@4021000 { |
| compatible = "allwinner,sun50i-h616-mmc", |
| "allwinner,sun50i-a100-mmc"; |
| reg = <0x04021000 0x1000>; |
| clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; |
| clock-names = "ahb", "mmc"; |
| resets = <&ccu RST_BUS_MMC1>; |
| reset-names = "ahb"; |
| interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&mmc1_pins>; |
| status = "disabled"; |
| max-frequency = <150000000>; |
| cap-sd-highspeed; |
| cap-mmc-highspeed; |
| mmc-ddr-3_3v; |
| cap-sdio-irq; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| }; |
| |
| mmc2: mmc@4022000 { |
| compatible = "allwinner,sun50i-h616-emmc", |
| "allwinner,sun50i-a100-emmc"; |
| reg = <0x04022000 0x1000>; |
| clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; |
| clock-names = "ahb", "mmc"; |
| resets = <&ccu RST_BUS_MMC2>; |
| reset-names = "ahb"; |
| interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&mmc2_pins>; |
| status = "disabled"; |
| max-frequency = <150000000>; |
| cap-sd-highspeed; |
| cap-mmc-highspeed; |
| mmc-ddr-3_3v; |
| cap-sdio-irq; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| }; |
| |
| uart0: serial@5000000 { |
| compatible = "snps,dw-apb-uart"; |
| reg = <0x05000000 0x400>; |
| interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; |
| reg-shift = <2>; |
| reg-io-width = <4>; |
| clocks = <&ccu CLK_BUS_UART0>; |
| dmas = <&dma 14>, <&dma 14>; |
| dma-names = "tx", "rx"; |
| resets = <&ccu RST_BUS_UART0>; |
| status = "disabled"; |
| }; |
| |
| uart1: serial@5000400 { |
| compatible = "snps,dw-apb-uart"; |
| reg = <0x05000400 0x400>; |
| interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; |
| reg-shift = <2>; |
| reg-io-width = <4>; |
| clocks = <&ccu CLK_BUS_UART1>; |
| dmas = <&dma 15>, <&dma 15>; |
| dma-names = "tx", "rx"; |
| resets = <&ccu RST_BUS_UART1>; |
| status = "disabled"; |
| }; |
| |
| uart2: serial@5000800 { |
| compatible = "snps,dw-apb-uart"; |
| reg = <0x05000800 0x400>; |
| interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; |
| reg-shift = <2>; |
| reg-io-width = <4>; |
| clocks = <&ccu CLK_BUS_UART2>; |
| dmas = <&dma 16>, <&dma 16>; |
| dma-names = "tx", "rx"; |
| resets = <&ccu RST_BUS_UART2>; |
| status = "disabled"; |
| }; |
| |
| uart3: serial@5000c00 { |
| compatible = "snps,dw-apb-uart"; |
| reg = <0x05000c00 0x400>; |
| interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; |
| reg-shift = <2>; |
| reg-io-width = <4>; |
| clocks = <&ccu CLK_BUS_UART3>; |
| dmas = <&dma 17>, <&dma 17>; |
| dma-names = "tx", "rx"; |
| resets = <&ccu RST_BUS_UART3>; |
| status = "disabled"; |
| }; |
| |
| uart4: serial@5001000 { |
| compatible = "snps,dw-apb-uart"; |
| reg = <0x05001000 0x400>; |
| interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; |
| reg-shift = <2>; |
| reg-io-width = <4>; |
| clocks = <&ccu CLK_BUS_UART4>; |
| dmas = <&dma 18>, <&dma 18>; |
| dma-names = "tx", "rx"; |
| resets = <&ccu RST_BUS_UART4>; |
| status = "disabled"; |
| }; |
| |
| uart5: serial@5001400 { |
| compatible = "snps,dw-apb-uart"; |
| reg = <0x05001400 0x400>; |
| interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; |
| reg-shift = <2>; |
| reg-io-width = <4>; |
| clocks = <&ccu CLK_BUS_UART5>; |
| dmas = <&dma 19>, <&dma 19>; |
| dma-names = "tx", "rx"; |
| resets = <&ccu RST_BUS_UART5>; |
| status = "disabled"; |
| }; |
| |
| i2c0: i2c@5002000 { |
| compatible = "allwinner,sun50i-h616-i2c", |
| "allwinner,sun8i-v536-i2c", |
| "allwinner,sun6i-a31-i2c"; |
| reg = <0x05002000 0x400>; |
| interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&ccu CLK_BUS_I2C0>; |
| dmas = <&dma 43>, <&dma 43>; |
| dma-names = "rx", "tx"; |
| resets = <&ccu RST_BUS_I2C0>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&i2c0_pins>; |
| status = "disabled"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| }; |
| |
| i2c1: i2c@5002400 { |
| compatible = "allwinner,sun50i-h616-i2c", |
| "allwinner,sun8i-v536-i2c", |
| "allwinner,sun6i-a31-i2c"; |
| reg = <0x05002400 0x400>; |
| interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&ccu CLK_BUS_I2C1>; |
| dmas = <&dma 44>, <&dma 44>; |
| dma-names = "rx", "tx"; |
| resets = <&ccu RST_BUS_I2C1>; |
| status = "disabled"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| }; |
| |
| i2c2: i2c@5002800 { |
| compatible = "allwinner,sun50i-h616-i2c", |
| "allwinner,sun8i-v536-i2c", |
| "allwinner,sun6i-a31-i2c"; |
| reg = <0x05002800 0x400>; |
| interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&ccu CLK_BUS_I2C2>; |
| dmas = <&dma 45>, <&dma 45>; |
| dma-names = "rx", "tx"; |
| resets = <&ccu RST_BUS_I2C2>; |
| status = "disabled"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| }; |
| |
| i2c3: i2c@5002c00 { |
| compatible = "allwinner,sun50i-h616-i2c", |
| "allwinner,sun8i-v536-i2c", |
| "allwinner,sun6i-a31-i2c"; |
| reg = <0x05002c00 0x400>; |
| interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&ccu CLK_BUS_I2C3>; |
| dmas = <&dma 46>, <&dma 46>; |
| dma-names = "rx", "tx"; |
| resets = <&ccu RST_BUS_I2C3>; |
| status = "disabled"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| }; |
| |
| i2c4: i2c@5003000 { |
| compatible = "allwinner,sun50i-h616-i2c", |
| "allwinner,sun8i-v536-i2c", |
| "allwinner,sun6i-a31-i2c"; |
| reg = <0x05003000 0x400>; |
| interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&ccu CLK_BUS_I2C4>; |
| dmas = <&dma 47>, <&dma 47>; |
| dma-names = "rx", "tx"; |
| resets = <&ccu RST_BUS_I2C4>; |
| status = "disabled"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| }; |
| |
| spi0: spi@5010000 { |
| compatible = "allwinner,sun50i-h616-spi", |
| "allwinner,sun8i-h3-spi"; |
| reg = <0x05010000 0x1000>; |
| interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; |
| clock-names = "ahb", "mod"; |
| dmas = <&dma 22>, <&dma 22>; |
| dma-names = "rx", "tx"; |
| resets = <&ccu RST_BUS_SPI0>; |
| status = "disabled"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| }; |
| |
| spi1: spi@5011000 { |
| compatible = "allwinner,sun50i-h616-spi", |
| "allwinner,sun8i-h3-spi"; |
| reg = <0x05011000 0x1000>; |
| interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; |
| clock-names = "ahb", "mod"; |
| dmas = <&dma 23>, <&dma 23>; |
| dma-names = "rx", "tx"; |
| resets = <&ccu RST_BUS_SPI1>; |
| status = "disabled"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| }; |
| |
| emac0: ethernet@5020000 { |
| compatible = "allwinner,sun50i-h616-emac0", |
| "allwinner,sun50i-a64-emac"; |
| reg = <0x05020000 0x10000>; |
| interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "macirq"; |
| clocks = <&ccu CLK_BUS_EMAC0>; |
| clock-names = "stmmaceth"; |
| resets = <&ccu RST_BUS_EMAC0>; |
| reset-names = "stmmaceth"; |
| syscon = <&syscon>; |
| status = "disabled"; |
| |
| mdio0: mdio { |
| compatible = "snps,dwmac-mdio"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| }; |
| }; |
| |
| spdif: spdif@5093000 { |
| compatible = "allwinner,sun50i-h616-spdif"; |
| reg = <0x05093000 0x400>; |
| interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>; |
| clock-names = "apb", "spdif"; |
| resets = <&ccu RST_BUS_SPDIF>; |
| dmas = <&dma 2>; |
| dma-names = "tx"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&spdif_tx_pin>; |
| #sound-dai-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| gpadc: adc@5070000 { |
| compatible = "allwinner,sun50i-h616-gpadc", |
| "allwinner,sun20i-d1-gpadc"; |
| reg = <0x05070000 0x400>; |
| clocks = <&ccu CLK_BUS_GPADC>; |
| resets = <&ccu RST_BUS_GPADC>; |
| interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; |
| status = "disabled"; |
| #io-channel-cells = <1>; |
| }; |
| |
| ths: thermal-sensor@5070400 { |
| compatible = "allwinner,sun50i-h616-ths"; |
| reg = <0x05070400 0x400>; |
| interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&ccu CLK_BUS_THS>; |
| clock-names = "bus"; |
| resets = <&ccu RST_BUS_THS>; |
| nvmem-cells = <&ths_calibration>; |
| nvmem-cell-names = "calibration"; |
| allwinner,sram = <&syscon>; |
| #thermal-sensor-cells = <1>; |
| }; |
| |
| lradc: lradc@5070800 { |
| compatible = "allwinner,sun50i-h616-lradc", |
| "allwinner,sun50i-r329-lradc"; |
| reg = <0x05070800 0x400>; |
| interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&ccu CLK_BUS_KEYADC>; |
| resets = <&ccu RST_BUS_KEYADC>; |
| status = "disabled"; |
| }; |
| |
| usbotg: usb@5100000 { |
| compatible = "allwinner,sun50i-h616-musb", |
| "allwinner,sun8i-h3-musb"; |
| reg = <0x05100000 0x0400>; |
| clocks = <&ccu CLK_BUS_OTG>; |
| resets = <&ccu RST_BUS_OTG>; |
| interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "mc"; |
| phys = <&usbphy 0>; |
| phy-names = "usb"; |
| extcon = <&usbphy 0>; |
| status = "disabled"; |
| }; |
| |
| usbphy: phy@5100400 { |
| compatible = "allwinner,sun50i-h616-usb-phy"; |
| reg = <0x05100400 0x24>, |
| <0x05101800 0x14>, |
| <0x05200800 0x14>, |
| <0x05310800 0x14>, |
| <0x05311800 0x14>; |
| reg-names = "phy_ctrl", |
| "pmu0", |
| "pmu1", |
| "pmu2", |
| "pmu3"; |
| clocks = <&ccu CLK_USB_PHY0>, |
| <&ccu CLK_USB_PHY1>, |
| <&ccu CLK_USB_PHY2>, |
| <&ccu CLK_USB_PHY3>, |
| <&ccu CLK_BUS_EHCI2>; |
| clock-names = "usb0_phy", |
| "usb1_phy", |
| "usb2_phy", |
| "usb3_phy", |
| "pmu2_clk"; |
| resets = <&ccu RST_USB_PHY0>, |
| <&ccu RST_USB_PHY1>, |
| <&ccu RST_USB_PHY2>, |
| <&ccu RST_USB_PHY3>; |
| reset-names = "usb0_reset", |
| "usb1_reset", |
| "usb2_reset", |
| "usb3_reset"; |
| status = "disabled"; |
| #phy-cells = <1>; |
| }; |
| |
| ehci0: usb@5101000 { |
| compatible = "allwinner,sun50i-h616-ehci", |
| "generic-ehci"; |
| reg = <0x05101000 0x100>; |
| interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&ccu CLK_BUS_OHCI0>, |
| <&ccu CLK_BUS_EHCI0>, |
| <&ccu CLK_USB_OHCI0>; |
| resets = <&ccu RST_BUS_OHCI0>, |
| <&ccu RST_BUS_EHCI0>; |
| phys = <&usbphy 0>; |
| phy-names = "usb"; |
| status = "disabled"; |
| }; |
| |
| ohci0: usb@5101400 { |
| compatible = "allwinner,sun50i-h616-ohci", |
| "generic-ohci"; |
| reg = <0x05101400 0x100>; |
| interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&ccu CLK_BUS_OHCI0>, |
| <&ccu CLK_USB_OHCI0>; |
| resets = <&ccu RST_BUS_OHCI0>; |
| phys = <&usbphy 0>; |
| phy-names = "usb"; |
| status = "disabled"; |
| }; |
| |
| ehci1: usb@5200000 { |
| compatible = "allwinner,sun50i-h616-ehci", |
| "generic-ehci"; |
| reg = <0x05200000 0x100>; |
| interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&ccu CLK_BUS_OHCI1>, |
| <&ccu CLK_BUS_EHCI1>, |
| <&ccu CLK_USB_OHCI1>; |
| resets = <&ccu RST_BUS_OHCI1>, |
| <&ccu RST_BUS_EHCI1>; |
| phys = <&usbphy 1>; |
| phy-names = "usb"; |
| status = "disabled"; |
| }; |
| |
| ohci1: usb@5200400 { |
| compatible = "allwinner,sun50i-h616-ohci", |
| "generic-ohci"; |
| reg = <0x05200400 0x100>; |
| interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&ccu CLK_BUS_OHCI1>, |
| <&ccu CLK_USB_OHCI1>; |
| resets = <&ccu RST_BUS_OHCI1>; |
| phys = <&usbphy 1>; |
| phy-names = "usb"; |
| status = "disabled"; |
| }; |
| |
| ehci2: usb@5310000 { |
| compatible = "allwinner,sun50i-h616-ehci", |
| "generic-ehci"; |
| reg = <0x05310000 0x100>; |
| interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&ccu CLK_BUS_OHCI2>, |
| <&ccu CLK_BUS_EHCI2>, |
| <&ccu CLK_USB_OHCI2>; |
| resets = <&ccu RST_BUS_OHCI2>, |
| <&ccu RST_BUS_EHCI2>; |
| phys = <&usbphy 2>; |
| phy-names = "usb"; |
| status = "disabled"; |
| }; |
| |
| ohci2: usb@5310400 { |
| compatible = "allwinner,sun50i-h616-ohci", |
| "generic-ohci"; |
| reg = <0x05310400 0x100>; |
| interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&ccu CLK_BUS_OHCI2>, |
| <&ccu CLK_USB_OHCI2>; |
| resets = <&ccu RST_BUS_OHCI2>; |
| phys = <&usbphy 2>; |
| phy-names = "usb"; |
| status = "disabled"; |
| }; |
| |
| ehci3: usb@5311000 { |
| compatible = "allwinner,sun50i-h616-ehci", |
| "generic-ehci"; |
| reg = <0x05311000 0x100>; |
| interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&ccu CLK_BUS_OHCI3>, |
| <&ccu CLK_BUS_EHCI3>, |
| <&ccu CLK_USB_OHCI3>; |
| resets = <&ccu RST_BUS_OHCI3>, |
| <&ccu RST_BUS_EHCI3>; |
| phys = <&usbphy 3>; |
| phy-names = "usb"; |
| status = "disabled"; |
| }; |
| |
| ohci3: usb@5311400 { |
| compatible = "allwinner,sun50i-h616-ohci", |
| "generic-ohci"; |
| reg = <0x05311400 0x100>; |
| interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&ccu CLK_BUS_OHCI3>, |
| <&ccu CLK_USB_OHCI3>; |
| resets = <&ccu RST_BUS_OHCI3>; |
| phys = <&usbphy 3>; |
| phy-names = "usb"; |
| status = "disabled"; |
| }; |
| |
| rtc: rtc@7000000 { |
| compatible = "allwinner,sun50i-h616-rtc"; |
| reg = <0x07000000 0x400>; |
| interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&r_ccu CLK_R_APB1_RTC>, <&osc24M>, |
| <&ccu CLK_PLL_SYSTEM_32K>; |
| clock-names = "bus", "hosc", |
| "pll-32k"; |
| #clock-cells = <1>; |
| }; |
| |
| r_ccu: clock@7010000 { |
| compatible = "allwinner,sun50i-h616-r-ccu"; |
| reg = <0x07010000 0x210>; |
| clocks = <&osc24M>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>, |
| <&ccu CLK_PLL_PERIPH0>; |
| clock-names = "hosc", "losc", "iosc", "pll-periph"; |
| #clock-cells = <1>; |
| #reset-cells = <1>; |
| }; |
| |
| nmi_intc: interrupt-controller@7010320 { |
| compatible = "allwinner,sun50i-h616-nmi", |
| "allwinner,sun9i-a80-nmi"; |
| reg = <0x07010320 0xc>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| r_pio: pinctrl@7022000 { |
| compatible = "allwinner,sun50i-h616-r-pinctrl"; |
| reg = <0x07022000 0x400>; |
| clocks = <&r_ccu CLK_R_APB1>, <&osc24M>, |
| <&rtc CLK_OSC32K>; |
| clock-names = "apb", "hosc", "losc"; |
| gpio-controller; |
| #gpio-cells = <3>; |
| |
| /omit-if-no-ref/ |
| r_i2c_pins: r-i2c-pins { |
| pins = "PL0", "PL1"; |
| function = "s_i2c"; |
| }; |
| |
| r_rsb_pins: r-rsb-pins { |
| pins = "PL0", "PL1"; |
| function = "s_rsb"; |
| }; |
| }; |
| |
| ir: ir@7040000 { |
| compatible = "allwinner,sun50i-h616-ir", |
| "allwinner,sun6i-a31-ir"; |
| reg = <0x07040000 0x400>; |
| interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&r_ccu CLK_R_APB1_IR>, |
| <&r_ccu CLK_IR>; |
| clock-names = "apb", "ir"; |
| resets = <&r_ccu RST_R_APB1_IR>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&ir_rx_pin>; |
| status = "disabled"; |
| }; |
| |
| r_i2c: i2c@7081400 { |
| compatible = "allwinner,sun50i-h616-i2c", |
| "allwinner,sun8i-v536-i2c", |
| "allwinner,sun6i-a31-i2c"; |
| reg = <0x07081400 0x400>; |
| interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&r_ccu CLK_R_APB2_I2C>; |
| dmas = <&dma 48>, <&dma 48>; |
| dma-names = "rx", "tx"; |
| resets = <&r_ccu RST_R_APB2_I2C>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&r_i2c_pins>; |
| status = "disabled"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| }; |
| |
| r_rsb: rsb@7083000 { |
| compatible = "allwinner,sun50i-h616-rsb", |
| "allwinner,sun8i-a23-rsb"; |
| reg = <0x07083000 0x400>; |
| interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&r_ccu CLK_R_APB2_RSB>; |
| clock-frequency = <3000000>; |
| resets = <&r_ccu RST_R_APB2_RSB>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&r_rsb_pins>; |
| status = "disabled"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| }; |
| }; |
| |
| thermal-zones { |
| cpu-thermal { |
| polling-delay-passive = <500>; |
| polling-delay = <1000>; |
| thermal-sensors = <&ths 2>; |
| sustainable-power = <1000>; |
| |
| trips { |
| cpu_threshold: cpu-trip-0 { |
| temperature = <60000>; |
| type = "passive"; |
| hysteresis = <0>; |
| }; |
| cpu_target: cpu-trip-1 { |
| temperature = <70000>; |
| type = "passive"; |
| hysteresis = <0>; |
| }; |
| cpu_critical: cpu-trip-2 { |
| temperature = <110000>; |
| type = "critical"; |
| hysteresis = <0>; |
| }; |
| }; |
| }; |
| |
| gpu-thermal { |
| polling-delay-passive = <500>; |
| polling-delay = <1000>; |
| thermal-sensors = <&ths 0>; |
| sustainable-power = <1100>; |
| |
| trips { |
| gpu_temp_critical: gpu-trip-0 { |
| temperature = <110000>; |
| type = "critical"; |
| hysteresis = <0>; |
| }; |
| }; |
| }; |
| |
| ve-thermal { |
| polling-delay-passive = <0>; |
| polling-delay = <0>; |
| thermal-sensors = <&ths 1>; |
| |
| trips { |
| ve_temp_critical: ve-trip-0 { |
| temperature = <110000>; |
| type = "critical"; |
| hysteresis = <0>; |
| }; |
| }; |
| }; |
| |
| ddr-thermal { |
| polling-delay-passive = <0>; |
| polling-delay = <0>; |
| thermal-sensors = <&ths 3>; |
| |
| trips { |
| ddr_temp_critical: ddr-trip-0 { |
| temperature = <110000>; |
| type = "critical"; |
| hysteresis = <0>; |
| }; |
| }; |
| }; |
| }; |
| }; |
