| /* |
| * ARM Ltd. Juno Platform |
| * |
| * Copyright (c) 2015 ARM Ltd. |
| * |
| * This file is licensed under a dual GPLv2 or BSD license. |
| */ |
| |
| /dts-v1/; |
| |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| #include <dt-bindings/arm/coresight-cti-dt.h> |
| #include "juno-base.dtsi" |
| #include "juno-cs-r1r2.dtsi" |
| |
| / { |
| model = "ARM Juno development board (r1)"; |
| compatible = "arm,juno-r1", "arm,juno", "arm,vexpress"; |
| interrupt-parent = <&gic>; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| |
| aliases { |
| serial0 = &soc_uart0; |
| }; |
| |
| chosen { |
| stdout-path = "serial0:115200n8"; |
| }; |
| |
| psci { |
| compatible = "arm,psci-0.2"; |
| method = "smc"; |
| }; |
| |
| cpus { |
| #address-cells = <2>; |
| #size-cells = <0>; |
| |
| cpu-map { |
| cluster0 { |
| core0 { |
| cpu = <&A57_0>; |
| }; |
| core1 { |
| cpu = <&A57_1>; |
| }; |
| }; |
| |
| cluster1 { |
| core0 { |
| cpu = <&A53_0>; |
| }; |
| core1 { |
| cpu = <&A53_1>; |
| }; |
| core2 { |
| cpu = <&A53_2>; |
| }; |
| core3 { |
| cpu = <&A53_3>; |
| }; |
| }; |
| }; |
| |
| idle-states { |
| entry-method = "psci"; |
| |
| CPU_SLEEP_0: cpu-sleep-0 { |
| compatible = "arm,idle-state"; |
| arm,psci-suspend-param = <0x0010000>; |
| local-timer-stop; |
| entry-latency-us = <300>; |
| exit-latency-us = <1200>; |
| min-residency-us = <2000>; |
| }; |
| |
| CLUSTER_SLEEP_0: cluster-sleep-0 { |
| compatible = "arm,idle-state"; |
| arm,psci-suspend-param = <0x1010000>; |
| local-timer-stop; |
| entry-latency-us = <400>; |
| exit-latency-us = <1200>; |
| min-residency-us = <2500>; |
| }; |
| }; |
| |
| A57_0: cpu@0 { |
| compatible = "arm,cortex-a57"; |
| reg = <0x0 0x0>; |
| device_type = "cpu"; |
| enable-method = "psci"; |
| i-cache-size = <0xc000>; |
| i-cache-line-size = <64>; |
| i-cache-sets = <256>; |
| d-cache-size = <0x8000>; |
| d-cache-line-size = <64>; |
| d-cache-sets = <256>; |
| next-level-cache = <&A57_L2>; |
| clocks = <&scpi_dvfs 0>; |
| cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; |
| capacity-dmips-mhz = <1024>; |
| }; |
| |
| A57_1: cpu@1 { |
| compatible = "arm,cortex-a57"; |
| reg = <0x0 0x1>; |
| device_type = "cpu"; |
| enable-method = "psci"; |
| i-cache-size = <0xc000>; |
| i-cache-line-size = <64>; |
| i-cache-sets = <256>; |
| d-cache-size = <0x8000>; |
| d-cache-line-size = <64>; |
| d-cache-sets = <256>; |
| next-level-cache = <&A57_L2>; |
| clocks = <&scpi_dvfs 0>; |
| cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; |
| capacity-dmips-mhz = <1024>; |
| }; |
| |
| A53_0: cpu@100 { |
| compatible = "arm,cortex-a53"; |
| reg = <0x0 0x100>; |
| device_type = "cpu"; |
| enable-method = "psci"; |
| i-cache-size = <0x8000>; |
| i-cache-line-size = <64>; |
| i-cache-sets = <256>; |
| d-cache-size = <0x8000>; |
| d-cache-line-size = <64>; |
| d-cache-sets = <128>; |
| next-level-cache = <&A53_L2>; |
| clocks = <&scpi_dvfs 1>; |
| cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; |
| capacity-dmips-mhz = <578>; |
| }; |
| |
| A53_1: cpu@101 { |
| compatible = "arm,cortex-a53"; |
| reg = <0x0 0x101>; |
| device_type = "cpu"; |
| enable-method = "psci"; |
| i-cache-size = <0x8000>; |
| i-cache-line-size = <64>; |
| i-cache-sets = <256>; |
| d-cache-size = <0x8000>; |
| d-cache-line-size = <64>; |
| d-cache-sets = <128>; |
| next-level-cache = <&A53_L2>; |
| clocks = <&scpi_dvfs 1>; |
| cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; |
| capacity-dmips-mhz = <578>; |
| }; |
| |
| A53_2: cpu@102 { |
| compatible = "arm,cortex-a53"; |
| reg = <0x0 0x102>; |
| device_type = "cpu"; |
| enable-method = "psci"; |
| i-cache-size = <0x8000>; |
| i-cache-line-size = <64>; |
| i-cache-sets = <256>; |
| d-cache-size = <0x8000>; |
| d-cache-line-size = <64>; |
| d-cache-sets = <128>; |
| next-level-cache = <&A53_L2>; |
| clocks = <&scpi_dvfs 1>; |
| cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; |
| capacity-dmips-mhz = <578>; |
| }; |
| |
| A53_3: cpu@103 { |
| compatible = "arm,cortex-a53"; |
| reg = <0x0 0x103>; |
| device_type = "cpu"; |
| enable-method = "psci"; |
| i-cache-size = <0x8000>; |
| i-cache-line-size = <64>; |
| i-cache-sets = <256>; |
| d-cache-size = <0x8000>; |
| d-cache-line-size = <64>; |
| d-cache-sets = <128>; |
| next-level-cache = <&A53_L2>; |
| clocks = <&scpi_dvfs 1>; |
| cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; |
| capacity-dmips-mhz = <578>; |
| }; |
| |
| A57_L2: l2-cache0 { |
| compatible = "cache"; |
| cache-unified; |
| cache-size = <0x200000>; |
| cache-line-size = <64>; |
| cache-sets = <2048>; |
| cache-level = <2>; |
| }; |
| |
| A53_L2: l2-cache1 { |
| compatible = "cache"; |
| cache-unified; |
| cache-size = <0x100000>; |
| cache-line-size = <64>; |
| cache-sets = <1024>; |
| cache-level = <2>; |
| }; |
| }; |
| |
| pmu-a57 { |
| compatible = "arm,cortex-a57-pmu"; |
| interrupts = <GIC_SPI 02 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 06 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-affinity = <&A57_0>, |
| <&A57_1>; |
| }; |
| |
| pmu-a53 { |
| compatible = "arm,cortex-a53-pmu"; |
| interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-affinity = <&A53_0>, |
| <&A53_1>, |
| <&A53_2>, |
| <&A53_3>; |
| }; |
| }; |
| |
| &memtimer { |
| status = "okay"; |
| }; |
| |
| &pcie_ctlr { |
| status = "okay"; |
| }; |
| |
| &smmu_pcie { |
| status = "okay"; |
| }; |
| |
| &etm0 { |
| cpu = <&A57_0>; |
| }; |
| |
| &etm1 { |
| cpu = <&A57_1>; |
| }; |
| |
| &etm2 { |
| cpu = <&A53_0>; |
| }; |
| |
| &etm3 { |
| cpu = <&A53_1>; |
| }; |
| |
| &etm4 { |
| cpu = <&A53_2>; |
| }; |
| |
| &etm5 { |
| cpu = <&A53_3>; |
| }; |
| |
| &big_cluster_thermal_zone { |
| status = "okay"; |
| }; |
| |
| &little_cluster_thermal_zone { |
| status = "okay"; |
| }; |
| |
| &gpu0_thermal_zone { |
| status = "okay"; |
| }; |
| |
| &gpu1_thermal_zone { |
| status = "okay"; |
| }; |
| |
| &etf0_out_port { |
| remote-endpoint = <&csys2_funnel_in_port0>; |
| }; |
| |
| &replicator_in_port0 { |
| remote-endpoint = <&csys2_funnel_out_port>; |
| }; |
| |
| &csys1_funnel_in_port0 { |
| remote-endpoint = <&stm_out_port>; |
| }; |
| |
| &stm_out_port { |
| remote-endpoint = <&csys1_funnel_in_port0>; |
| }; |
| |
| &cpu_debug0 { |
| cpu = <&A57_0>; |
| }; |
| |
| &cpu_debug1 { |
| cpu = <&A57_1>; |
| }; |
| |
| &cpu_debug2 { |
| cpu = <&A53_0>; |
| }; |
| |
| &cpu_debug3 { |
| cpu = <&A53_1>; |
| }; |
| |
| &cpu_debug4 { |
| cpu = <&A53_2>; |
| }; |
| |
| &cpu_debug5 { |
| cpu = <&A53_3>; |
| }; |
| |
| &cti0 { |
| cpu = <&A57_0>; |
| }; |
| |
| &cti1 { |
| cpu = <&A57_1>; |
| }; |
| |
| &cti2 { |
| cpu = <&A53_0>; |
| }; |
| |
| &cti3 { |
| cpu = <&A53_1>; |
| }; |
| |
| &cti4 { |
| cpu = <&A53_2>; |
| }; |
| |
| &cti5 { |
| cpu = <&A53_3>; |
| }; |
