arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi - linux - Git at Google

 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
 /*
  * Device Tree Source for the RZ/{G2L,V2L} SMARC SOM common parts
  *
  * Copyright (C) 2021 Renesas Electronics Corp.
  */

 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/interrupt-controller/irqc-rzg2l.h>
 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>

 /* SW1[2] should be at position 2/OFF to enable 64 GB eMMC */
 #define EMMC	1

 /*
  * To enable uSD card on CN3,
  * SW1[2] should be at position 3/ON.
  * Disable eMMC by setting "#define EMMC	0" above.
  */
 #define SDHI	(!EMMC)

 / {
 	aliases {
 		ethernet0 = &eth0;
 		ethernet1 = &eth1;
 	};

 	chosen {
 		bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
 	};

 	memory@48000000 {
 		device_type = "memory";
 		/* first 128MB is reserved for secure area. */
 		reg = <0x0 0x48000000 0x0 0x78000000>;
 	};

 	reg_1p8v: regulator-1p8v {
 		compatible = "regulator-fixed";
 		regulator-name = "fixed-1.8V";
 		regulator-min-microvolt = <1800000>;
 		regulator-max-microvolt = <1800000>;
 		regulator-boot-on;
 		regulator-always-on;
 	};

 	reg_3p3v: regulator-3p3v {
 		compatible = "regulator-fixed";
 		regulator-name = "fixed-3.3V";
 		regulator-min-microvolt = <3300000>;
 		regulator-max-microvolt = <3300000>;
 		regulator-boot-on;
 		regulator-always-on;
 	};

 	reg_1p1v: regulator-vdd-core {
 		compatible = "regulator-fixed";
 		regulator-name = "fixed-1.1V";
 		regulator-min-microvolt = <1100000>;
 		regulator-max-microvolt = <1100000>;
 		regulator-boot-on;
 		regulator-always-on;
 	};

 	vccq_sdhi0: regulator-vccq-sdhi0 {
 		compatible = "regulator-gpio";

 		regulator-name = "SDHI0 VccQ";
 		regulator-min-microvolt = <1800000>;
 		regulator-max-microvolt = <3300000>;
 		states = <3300000 1>, <1800000 0>;
 		regulator-boot-on;
 		gpios = <&pinctrl RZG2L_GPIO(39, 0) GPIO_ACTIVE_HIGH>;
 		regulator-always-on;
 	};

 	/* 32.768kHz crystal */
 	x2: x2-clock {
 		compatible = "fixed-clock";
 		#clock-cells = <0>;
 		clock-frequency = <32768>;
 	};
 };

 &adc {
 	pinctrl-0 = <&adc_pins>;
 	pinctrl-names = "default";
 	status = "okay";

 	/delete-node/ channel@6;
 	/delete-node/ channel@7;
 };

 &eth0 {
 	pinctrl-0 = <&eth0_pins>;
 	pinctrl-names = "default";
 	phy-handle = <&phy0>;
 	phy-mode = "rgmii-id";
 	status = "okay";

 	phy0: ethernet-phy@7 {
 		compatible = "ethernet-phy-id0022.1640",
 			     "ethernet-phy-ieee802.3-c22";
 		reg = <7>;
 		interrupt-parent = <&irqc>;
 		interrupts = <RZG2L_IRQ2 IRQ_TYPE_LEVEL_LOW>;
 		rxc-skew-psec = <2400>;
 		txc-skew-psec = <2400>;
 		rxdv-skew-psec = <0>;
 		txen-skew-psec = <0>;
 		rxd0-skew-psec = <0>;
 		rxd1-skew-psec = <0>;
 		rxd2-skew-psec = <0>;
 		rxd3-skew-psec = <0>;
 		txd0-skew-psec = <0>;
 		txd1-skew-psec = <0>;
 		txd2-skew-psec = <0>;
 		txd3-skew-psec = <0>;
 	};
 };

 &eth1 {
 	pinctrl-0 = <&eth1_pins>;
 	pinctrl-names = "default";
 	phy-handle = <&phy1>;
 	phy-mode = "rgmii-id";
 	status = "okay";

 	phy1: ethernet-phy@7 {
 		compatible = "ethernet-phy-id0022.1640",
 			     "ethernet-phy-ieee802.3-c22";
 		reg = <7>;
 		interrupt-parent = <&irqc>;
 		interrupts = <RZG2L_IRQ3 IRQ_TYPE_LEVEL_LOW>;
 		rxc-skew-psec = <2400>;
 		txc-skew-psec = <2400>;
 		rxdv-skew-psec = <0>;
 		txen-skew-psec = <0>;
 		rxd0-skew-psec = <0>;
 		rxd1-skew-psec = <0>;
 		rxd2-skew-psec = <0>;
 		rxd3-skew-psec = <0>;
 		txd0-skew-psec = <0>;
 		txd1-skew-psec = <0>;
 		txd2-skew-psec = <0>;
 		txd3-skew-psec = <0>;
 	};
 };

 &extal_clk {
 	clock-frequency = <24000000>;
 };

 &gpu {
 	mali-supply = <&reg_1p1v>;
 };

 &i2c3 {
 	raa215300: pmic@12 {
 		compatible = "renesas,raa215300";
 		reg = <0x12>, <0x6f>;
 		reg-names = "main", "rtc";

 		clocks = <&x2>;
 		clock-names = "xin";
 	};
 };

 &ostm1 {
 	status = "okay";
 };

 &ostm2 {
 	status = "okay";
 };

 &pinctrl {
 	adc_pins: adc {
 		pinmux = <RZG2L_PORT_PINMUX(9, 0, 2)>; /* ADC_TRG */
 	};

 	eth0_pins: eth0 {
 		txc {
 			pinmux = <RZG2L_PORT_PINMUX(20, 0, 1)>; /* ET0_TXC */
 			power-source = <1800>;
 			output-enable;
 		};

 		mux {
 			pinmux = <RZG2L_PORT_PINMUX(28, 1, 1)>, /* ET0_LINKSTA */
 				 <RZG2L_PORT_PINMUX(27, 1, 1)>, /* ET0_MDC */
 				 <RZG2L_PORT_PINMUX(28, 0, 1)>, /* ET0_MDIO */
 				 <RZG2L_PORT_PINMUX(20, 1, 1)>, /* ET0_TX_CTL */
 				 <RZG2L_PORT_PINMUX(20, 2, 1)>, /* ET0_TXD0 */
 				 <RZG2L_PORT_PINMUX(21, 0, 1)>, /* ET0_TXD1 */
 				 <RZG2L_PORT_PINMUX(21, 1, 1)>, /* ET0_TXD2 */
 				 <RZG2L_PORT_PINMUX(22, 0, 1)>, /* ET0_TXD3 */
 				 <RZG2L_PORT_PINMUX(24, 0, 1)>, /* ET0_RXC */
 				 <RZG2L_PORT_PINMUX(24, 1, 1)>, /* ET0_RX_CTL */
 				 <RZG2L_PORT_PINMUX(25, 0, 1)>, /* ET0_RXD0 */
 				 <RZG2L_PORT_PINMUX(25, 1, 1)>, /* ET0_RXD1 */
 				 <RZG2L_PORT_PINMUX(26, 0, 1)>, /* ET0_RXD2 */
 				 <RZG2L_PORT_PINMUX(26, 1, 1)>; /* ET0_RXD3 */
 			power-source = <1800>;
 		};

 		irq {
 			pinmux = <RZG2L_PORT_PINMUX(1, 0, 1)>;  /* IRQ2 */
 		};
 	};

 	eth1_pins: eth1 {
 		txc {
 			pinmux = <RZG2L_PORT_PINMUX(29, 0, 1)>; /* ET1_TXC */
 			power-source = <1800>;
 			output-enable;
 		};

 		mux {
 			pinmux = <RZG2L_PORT_PINMUX(37, 2, 1)>, /* ET1_LINKSTA */
 				 <RZG2L_PORT_PINMUX(37, 0, 1)>, /* ET1_MDC */
 				 <RZG2L_PORT_PINMUX(37, 1, 1)>, /* ET1_MDIO */
 				 <RZG2L_PORT_PINMUX(29, 1, 1)>, /* ET1_TX_CTL */
 				 <RZG2L_PORT_PINMUX(30, 0, 1)>, /* ET1_TXD0 */
 				 <RZG2L_PORT_PINMUX(30, 1, 1)>, /* ET1_TXD1 */
 				 <RZG2L_PORT_PINMUX(31, 0, 1)>, /* ET1_TXD2 */
 				 <RZG2L_PORT_PINMUX(31, 1, 1)>, /* ET1_TXD3 */
 				 <RZG2L_PORT_PINMUX(33, 1, 1)>, /* ET1_RXC */
 				 <RZG2L_PORT_PINMUX(34, 0, 1)>, /* ET1_RX_CTL */
 				 <RZG2L_PORT_PINMUX(34, 1, 1)>, /* ET1_RXD0 */
 				 <RZG2L_PORT_PINMUX(35, 0, 1)>, /* ET1_RXD1 */
 				 <RZG2L_PORT_PINMUX(35, 1, 1)>, /* ET1_RXD2 */
 				 <RZG2L_PORT_PINMUX(36, 0, 1)>; /* ET1_RXD3 */
 			power-source = <1800>;
 		};

 		irq {
 			pinmux = <RZG2L_PORT_PINMUX(1, 1, 1)>;  /* IRQ3 */
 		};
 	};

 	gpio-sd0-pwr-en-hog {
 		gpio-hog;
 		gpios = <RZG2L_GPIO(4, 1) GPIO_ACTIVE_HIGH>;
 		output-high;
 		line-name = "gpio_sd0_pwr_en";
 	};

 	qspi0_pins: qspi0 {
 		qspi0-data {
 			pins = "QSPI0_IO0", "QSPI0_IO1", "QSPI0_IO2", "QSPI0_IO3";
 			power-source = <1800>;
 		};

 		qspi0-ctrl {
 			pins = "QSPI0_SPCLK", "QSPI0_SSL", "QSPI_RESET#";
 			power-source = <1800>;
 		};
 	};

 	/*
 	 * SD0 device selection is XOR between GPIO_SD0_DEV_SEL and SW1[2]
 	 * The below switch logic can be used to select the device between
 	 * eMMC and microSD, after setting GPIO_SD0_DEV_SEL to high in DT.
 	 * SW1[2] should be at position 2/OFF to enable 64 GB eMMC
 	 * SW1[2] should be at position 3/ON to enable uSD card CN3
 	 */
 	sd0-dev-sel-hog {
 		gpio-hog;
 		gpios = <RZG2L_GPIO(41, 1) GPIO_ACTIVE_HIGH>;
 		output-high;
 		line-name = "sd0_dev_sel";
 	};

 	sdhi0_emmc_pins: sd0emmc {
 		sd0_emmc_data {
 			pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3",
 			       "SD0_DATA4", "SD0_DATA5", "SD0_DATA6", "SD0_DATA7";
 			power-source = <1800>;
 		};

 		sd0_emmc_ctrl {
 			pins = "SD0_CLK", "SD0_CMD";
 			power-source = <1800>;
 		};

 		sd0_emmc_rst {
 			pins = "SD0_RST#";
 			power-source = <1800>;
 		};
 	};

 	sdhi0_pins: sd0 {
 		sd0_data {
 			pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3";
 			power-source = <3300>;
 		};

 		sd0_ctrl {
 			pins = "SD0_CLK", "SD0_CMD";
 			power-source = <3300>;
 		};

 		sd0_mux {
 			pinmux = <RZG2L_PORT_PINMUX(47, 0, 2)>; /* SD0_CD */
 		};
 	};

 	sdhi0_pins_uhs: sd0_uhs {
 		sd0_data_uhs {
 			pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3";
 			power-source = <1800>;
 		};

 		sd0_ctrl_uhs {
 			pins = "SD0_CLK", "SD0_CMD";
 			power-source = <1800>;
 		};

 		sd0_mux_uhs {
 			pinmux = <RZG2L_PORT_PINMUX(47, 0, 2)>; /* SD0_CD */
 		};
 	};
 };

 &sbc {
 	pinctrl-0 = <&qspi0_pins>;
 	pinctrl-names = "default";
 	status = "okay";

 	flash@0 {
 		compatible = "micron,mt25qu512a", "jedec,spi-nor";
 		reg = <0>;
 		m25p,fast-read;
 		spi-max-frequency = <50000000>;
 		spi-rx-bus-width = <4>;
 		spi-tx-bus-width = <4>;

 		partitions {
 			compatible = "fixed-partitions";
 			#address-cells = <1>;
 			#size-cells = <1>;

 			boot@0 {
 				reg = <0x00000000 0x2000000>;
 				read-only;
 			};
 			user@2000000 {
 				reg = <0x2000000 0x2000000>;
 			};
 		};
 	};
 };

 #if SDHI
 &sdhi0 {
 	pinctrl-0 = <&sdhi0_pins>;
 	pinctrl-1 = <&sdhi0_pins_uhs>;
 	pinctrl-names = "default", "state_uhs";

 	vmmc-supply = <&reg_3p3v>;
 	vqmmc-supply = <&vccq_sdhi0>;
 	bus-width = <4>;
 	sd-uhs-sdr50;
 	sd-uhs-sdr104;
 	status = "okay";
 };
 #endif

 #if EMMC
 &sdhi0 {
 	pinctrl-0 = <&sdhi0_emmc_pins>;
 	pinctrl-1 = <&sdhi0_emmc_pins>;
 	pinctrl-names = "default", "state_uhs";

 	vmmc-supply = <&reg_3p3v>;
 	vqmmc-supply = <&reg_1p8v>;
 	bus-width = <8>;
 	mmc-hs200-1_8v;
 	non-removable;
 	fixed-emmc-driver-type = <1>;
 	status = "okay";
 };
 #endif

 &wdt0 {
 	status = "okay";
 	timeout-sec = <60>;
 };

 &wdt1 {
 	status = "okay";
 	timeout-sec = <60>;
 };
	// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
	/*
	* Device Tree Source for the RZ/{G2L,V2L} SMARC SOM common parts
	*
	* Copyright (C) 2021 Renesas Electronics Corp.
	*/

	#include <dt-bindings/gpio/gpio.h>
	#include <dt-bindings/interrupt-controller/irqc-rzg2l.h>
	#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>

	/* SW1[2] should be at position 2/OFF to enable 64 GB eMMC */
	#define EMMC 1

	/*
	* To enable uSD card on CN3,
	* SW1[2] should be at position 3/ON.
	* Disable eMMC by setting "#define EMMC 0" above.
	*/
	#define SDHI (!EMMC)

	/ {
	aliases {
	ethernet0 = &eth0;
	ethernet1 = &eth1;
	};

	chosen {
	bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
	};

	memory@48000000 {
	device_type = "memory";
	/* first 128MB is reserved for secure area. */
	reg = <0x0 0x48000000 0x0 0x78000000>;
	};

	reg_1p8v: regulator-1p8v {
	compatible = "regulator-fixed";
	regulator-name = "fixed-1.8V";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-boot-on;
	regulator-always-on;
	};

	reg_3p3v: regulator-3p3v {
	compatible = "regulator-fixed";
	regulator-name = "fixed-3.3V";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-boot-on;
	regulator-always-on;
	};

	reg_1p1v: regulator-vdd-core {
	compatible = "regulator-fixed";
	regulator-name = "fixed-1.1V";
	regulator-min-microvolt = <1100000>;
	regulator-max-microvolt = <1100000>;
	regulator-boot-on;
	regulator-always-on;
	};

	vccq_sdhi0: regulator-vccq-sdhi0 {
	compatible = "regulator-gpio";

	regulator-name = "SDHI0 VccQ";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <3300000>;
	states = <3300000 1>, <1800000 0>;
	regulator-boot-on;
	gpios = <&pinctrl RZG2L_GPIO(39, 0) GPIO_ACTIVE_HIGH>;
	regulator-always-on;
	};

	/* 32.768kHz crystal */
	x2: x2-clock {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <32768>;
	};
	};

	&adc {
	pinctrl-0 = <&adc_pins>;
	pinctrl-names = "default";
	status = "okay";

	/delete-node/ channel@6;
	/delete-node/ channel@7;
	};

	&eth0 {
	pinctrl-0 = <&eth0_pins>;
	pinctrl-names = "default";
	phy-handle = <&phy0>;
	phy-mode = "rgmii-id";
	status = "okay";

	phy0: ethernet-phy@7 {
	compatible = "ethernet-phy-id0022.1640",
	"ethernet-phy-ieee802.3-c22";
	reg = <7>;
	interrupt-parent = <&irqc>;
	interrupts = <RZG2L_IRQ2 IRQ_TYPE_LEVEL_LOW>;
	rxc-skew-psec = <2400>;
	txc-skew-psec = <2400>;
	rxdv-skew-psec = <0>;
	txen-skew-psec = <0>;
	rxd0-skew-psec = <0>;
	rxd1-skew-psec = <0>;
	rxd2-skew-psec = <0>;
	rxd3-skew-psec = <0>;
	txd0-skew-psec = <0>;
	txd1-skew-psec = <0>;
	txd2-skew-psec = <0>;
	txd3-skew-psec = <0>;
	};
	};

	&eth1 {
	pinctrl-0 = <&eth1_pins>;
	pinctrl-names = "default";
	phy-handle = <&phy1>;
	phy-mode = "rgmii-id";
	status = "okay";

	phy1: ethernet-phy@7 {
	compatible = "ethernet-phy-id0022.1640",
	"ethernet-phy-ieee802.3-c22";
	reg = <7>;
	interrupt-parent = <&irqc>;
	interrupts = <RZG2L_IRQ3 IRQ_TYPE_LEVEL_LOW>;
	rxc-skew-psec = <2400>;
	txc-skew-psec = <2400>;
	rxdv-skew-psec = <0>;
	txen-skew-psec = <0>;
	rxd0-skew-psec = <0>;
	rxd1-skew-psec = <0>;
	rxd2-skew-psec = <0>;
	rxd3-skew-psec = <0>;
	txd0-skew-psec = <0>;
	txd1-skew-psec = <0>;
	txd2-skew-psec = <0>;
	txd3-skew-psec = <0>;
	};
	};

	&extal_clk {
	clock-frequency = <24000000>;
	};

	&gpu {
	mali-supply = <&reg_1p1v>;
	};

	&i2c3 {
	raa215300: pmic@12 {
	compatible = "renesas,raa215300";
	reg = <0x12>, <0x6f>;
	reg-names = "main", "rtc";

	clocks = <&x2>;
	clock-names = "xin";
	};
	};

	&ostm1 {
	status = "okay";
	};

	&ostm2 {
	status = "okay";
	};

	&pinctrl {
	adc_pins: adc {
	pinmux = <RZG2L_PORT_PINMUX(9, 0, 2)>; /* ADC_TRG */
	};

	eth0_pins: eth0 {
	txc {
	pinmux = <RZG2L_PORT_PINMUX(20, 0, 1)>; /* ET0_TXC */
	power-source = <1800>;
	output-enable;
	};

	mux {
	pinmux = <RZG2L_PORT_PINMUX(28, 1, 1)>, /* ET0_LINKSTA */
	<RZG2L_PORT_PINMUX(27, 1, 1)>, /* ET0_MDC */
	<RZG2L_PORT_PINMUX(28, 0, 1)>, /* ET0_MDIO */
	<RZG2L_PORT_PINMUX(20, 1, 1)>, /* ET0_TX_CTL */
	<RZG2L_PORT_PINMUX(20, 2, 1)>, /* ET0_TXD0 */
	<RZG2L_PORT_PINMUX(21, 0, 1)>, /* ET0_TXD1 */
	<RZG2L_PORT_PINMUX(21, 1, 1)>, /* ET0_TXD2 */
	<RZG2L_PORT_PINMUX(22, 0, 1)>, /* ET0_TXD3 */
	<RZG2L_PORT_PINMUX(24, 0, 1)>, /* ET0_RXC */
	<RZG2L_PORT_PINMUX(24, 1, 1)>, /* ET0_RX_CTL */
	<RZG2L_PORT_PINMUX(25, 0, 1)>, /* ET0_RXD0 */
	<RZG2L_PORT_PINMUX(25, 1, 1)>, /* ET0_RXD1 */
	<RZG2L_PORT_PINMUX(26, 0, 1)>, /* ET0_RXD2 */
	<RZG2L_PORT_PINMUX(26, 1, 1)>; /* ET0_RXD3 */
	power-source = <1800>;
	};

	irq {
	pinmux = <RZG2L_PORT_PINMUX(1, 0, 1)>; /* IRQ2 */
	};
	};

	eth1_pins: eth1 {
	txc {
	pinmux = <RZG2L_PORT_PINMUX(29, 0, 1)>; /* ET1_TXC */
	power-source = <1800>;
	output-enable;
	};

	mux {
	pinmux = <RZG2L_PORT_PINMUX(37, 2, 1)>, /* ET1_LINKSTA */
	<RZG2L_PORT_PINMUX(37, 0, 1)>, /* ET1_MDC */
	<RZG2L_PORT_PINMUX(37, 1, 1)>, /* ET1_MDIO */
	<RZG2L_PORT_PINMUX(29, 1, 1)>, /* ET1_TX_CTL */
	<RZG2L_PORT_PINMUX(30, 0, 1)>, /* ET1_TXD0 */
	<RZG2L_PORT_PINMUX(30, 1, 1)>, /* ET1_TXD1 */
	<RZG2L_PORT_PINMUX(31, 0, 1)>, /* ET1_TXD2 */
	<RZG2L_PORT_PINMUX(31, 1, 1)>, /* ET1_TXD3 */
	<RZG2L_PORT_PINMUX(33, 1, 1)>, /* ET1_RXC */
	<RZG2L_PORT_PINMUX(34, 0, 1)>, /* ET1_RX_CTL */
	<RZG2L_PORT_PINMUX(34, 1, 1)>, /* ET1_RXD0 */
	<RZG2L_PORT_PINMUX(35, 0, 1)>, /* ET1_RXD1 */
	<RZG2L_PORT_PINMUX(35, 1, 1)>, /* ET1_RXD2 */
	<RZG2L_PORT_PINMUX(36, 0, 1)>; /* ET1_RXD3 */
	power-source = <1800>;
	};

	irq {
	pinmux = <RZG2L_PORT_PINMUX(1, 1, 1)>; /* IRQ3 */
	};
	};

	gpio-sd0-pwr-en-hog {
	gpio-hog;
	gpios = <RZG2L_GPIO(4, 1) GPIO_ACTIVE_HIGH>;
	output-high;
	line-name = "gpio_sd0_pwr_en";
	};

	qspi0_pins: qspi0 {
	qspi0-data {
	pins = "QSPI0_IO0", "QSPI0_IO1", "QSPI0_IO2", "QSPI0_IO3";
	power-source = <1800>;
	};

	qspi0-ctrl {
	pins = "QSPI0_SPCLK", "QSPI0_SSL", "QSPI_RESET#";
	power-source = <1800>;
	};
	};

	/*
	* SD0 device selection is XOR between GPIO_SD0_DEV_SEL and SW1[2]
	* The below switch logic can be used to select the device between
	* eMMC and microSD, after setting GPIO_SD0_DEV_SEL to high in DT.
	* SW1[2] should be at position 2/OFF to enable 64 GB eMMC
	* SW1[2] should be at position 3/ON to enable uSD card CN3
	*/
	sd0-dev-sel-hog {
	gpio-hog;
	gpios = <RZG2L_GPIO(41, 1) GPIO_ACTIVE_HIGH>;
	output-high;
	line-name = "sd0_dev_sel";
	};

	sdhi0_emmc_pins: sd0emmc {
	sd0_emmc_data {
	pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3",
	"SD0_DATA4", "SD0_DATA5", "SD0_DATA6", "SD0_DATA7";
	power-source = <1800>;
	};

	sd0_emmc_ctrl {
	pins = "SD0_CLK", "SD0_CMD";
	power-source = <1800>;
	};

	sd0_emmc_rst {
	pins = "SD0_RST#";
	power-source = <1800>;
	};
	};

	sdhi0_pins: sd0 {
	sd0_data {
	pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3";
	power-source = <3300>;
	};

	sd0_ctrl {
	pins = "SD0_CLK", "SD0_CMD";
	power-source = <3300>;
	};

	sd0_mux {
	pinmux = <RZG2L_PORT_PINMUX(47, 0, 2)>; /* SD0_CD */
	};
	};

	sdhi0_pins_uhs: sd0_uhs {
	sd0_data_uhs {
	pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3";
	power-source = <1800>;
	};

	sd0_ctrl_uhs {
	pins = "SD0_CLK", "SD0_CMD";
	power-source = <1800>;
	};

	sd0_mux_uhs {
	pinmux = <RZG2L_PORT_PINMUX(47, 0, 2)>; /* SD0_CD */
	};
	};
	};

	&sbc {
	pinctrl-0 = <&qspi0_pins>;
	pinctrl-names = "default";
	status = "okay";

	flash@0 {
	compatible = "micron,mt25qu512a", "jedec,spi-nor";
	reg = <0>;
	m25p,fast-read;
	spi-max-frequency = <50000000>;
	spi-rx-bus-width = <4>;
	spi-tx-bus-width = <4>;

	partitions {
	compatible = "fixed-partitions";
	#address-cells = <1>;
	#size-cells = <1>;

	boot@0 {
	reg = <0x00000000 0x2000000>;
	read-only;
	};
	user@2000000 {
	reg = <0x2000000 0x2000000>;
	};
	};
	};
	};

	#if SDHI
	&sdhi0 {
	pinctrl-0 = <&sdhi0_pins>;
	pinctrl-1 = <&sdhi0_pins_uhs>;
	pinctrl-names = "default", "state_uhs";

	vmmc-supply = <&reg_3p3v>;
	vqmmc-supply = <&vccq_sdhi0>;
	bus-width = <4>;
	sd-uhs-sdr50;
	sd-uhs-sdr104;
	status = "okay";
	};
	#endif

	#if EMMC
	&sdhi0 {
	pinctrl-0 = <&sdhi0_emmc_pins>;
	pinctrl-1 = <&sdhi0_emmc_pins>;
	pinctrl-names = "default", "state_uhs";

	vmmc-supply = <&reg_3p3v>;
	vqmmc-supply = <&reg_1p8v>;
	bus-width = <8>;
	mmc-hs200-1_8v;
	non-removable;
	fixed-emmc-driver-type = <1>;
	status = "okay";
	};
	#endif

	&wdt0 {
	status = "okay";
	timeout-sec = <60>;
	};

	&wdt1 {
	status = "okay";
	timeout-sec = <60>;
	};