| // SPDX-License-Identifier: GPL-2.0+ |
| /* |
| * Copyright 2018-2019 NXP |
| * Dong Aisheng <aisheng.dong@nxp.com> |
| */ |
| |
| #include <dt-bindings/clock/imx8-lpcg.h> |
| #include <dt-bindings/firmware/imx/rsrc.h> |
| #include <dt-bindings/gpio/gpio.h> |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| #include <dt-bindings/pinctrl/pads-imx8qm.h> |
| |
| / { |
| interrupt-parent = <&gic>; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| |
| aliases { |
| mmc0 = &usdhc1; |
| mmc1 = &usdhc2; |
| mmc2 = &usdhc3; |
| serial0 = &lpuart0; |
| serial1 = &lpuart1; |
| serial2 = &lpuart2; |
| serial3 = &lpuart3; |
| }; |
| |
| cpus { |
| #address-cells = <2>; |
| #size-cells = <0>; |
| |
| cpu-map { |
| cluster0 { |
| core0 { |
| cpu = <&A53_0>; |
| }; |
| core1 { |
| cpu = <&A53_1>; |
| }; |
| core2 { |
| cpu = <&A53_2>; |
| }; |
| core3 { |
| cpu = <&A53_3>; |
| }; |
| }; |
| |
| cluster1 { |
| core0 { |
| cpu = <&A72_0>; |
| }; |
| core1 { |
| cpu = <&A72_1>; |
| }; |
| }; |
| }; |
| |
| A53_0: cpu@0 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a53"; |
| reg = <0x0 0x0>; |
| enable-method = "psci"; |
| i-cache-size = <0x8000>; |
| i-cache-line-size = <64>; |
| i-cache-sets = <256>; |
| d-cache-size = <0x8000>; |
| d-cache-line-size = <64>; |
| d-cache-sets = <128>; |
| next-level-cache = <&A53_L2>; |
| }; |
| |
| A53_1: cpu@1 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a53"; |
| reg = <0x0 0x1>; |
| enable-method = "psci"; |
| i-cache-size = <0x8000>; |
| i-cache-line-size = <64>; |
| i-cache-sets = <256>; |
| d-cache-size = <0x8000>; |
| d-cache-line-size = <64>; |
| d-cache-sets = <128>; |
| next-level-cache = <&A53_L2>; |
| }; |
| |
| A53_2: cpu@2 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a53"; |
| reg = <0x0 0x2>; |
| enable-method = "psci"; |
| i-cache-size = <0x8000>; |
| i-cache-line-size = <64>; |
| i-cache-sets = <256>; |
| d-cache-size = <0x8000>; |
| d-cache-line-size = <64>; |
| d-cache-sets = <128>; |
| next-level-cache = <&A53_L2>; |
| }; |
| |
| A53_3: cpu@3 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a53"; |
| reg = <0x0 0x3>; |
| enable-method = "psci"; |
| i-cache-size = <0x8000>; |
| i-cache-line-size = <64>; |
| i-cache-sets = <256>; |
| d-cache-size = <0x8000>; |
| d-cache-line-size = <64>; |
| d-cache-sets = <128>; |
| next-level-cache = <&A53_L2>; |
| }; |
| |
| A72_0: cpu@100 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a72"; |
| reg = <0x0 0x100>; |
| enable-method = "psci"; |
| i-cache-size = <0xC000>; |
| i-cache-line-size = <64>; |
| i-cache-sets = <256>; |
| d-cache-size = <0x8000>; |
| d-cache-line-size = <64>; |
| d-cache-sets = <256>; |
| next-level-cache = <&A72_L2>; |
| }; |
| |
| A72_1: cpu@101 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a72"; |
| reg = <0x0 0x101>; |
| enable-method = "psci"; |
| next-level-cache = <&A72_L2>; |
| }; |
| |
| A53_L2: l2-cache0 { |
| compatible = "cache"; |
| cache-level = <2>; |
| cache-size = <0x100000>; |
| cache-line-size = <64>; |
| cache-sets = <1024>; |
| }; |
| |
| A72_L2: l2-cache1 { |
| compatible = "cache"; |
| cache-level = <2>; |
| cache-size = <0x100000>; |
| cache-line-size = <64>; |
| cache-sets = <1024>; |
| }; |
| }; |
| |
| gic: interrupt-controller@51a00000 { |
| compatible = "arm,gic-v3"; |
| reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */ |
| <0x0 0x51b00000 0 0xC0000>, /* GICR */ |
| <0x0 0x52000000 0 0x2000>, /* GICC */ |
| <0x0 0x52010000 0 0x1000>, /* GICH */ |
| <0x0 0x52020000 0 0x20000>; /* GICV */ |
| #interrupt-cells = <3>; |
| interrupt-controller; |
| interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-parent = <&gic>; |
| }; |
| |
| pmu { |
| compatible = "arm,armv8-pmuv3"; |
| interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| psci { |
| compatible = "arm,psci-1.0"; |
| method = "smc"; |
| }; |
| |
| timer { |
| compatible = "arm,armv8-timer"; |
| interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */ |
| <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */ |
| <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */ |
| <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */ |
| }; |
| |
| system-controller { |
| compatible = "fsl,imx-scu"; |
| mbox-names = "tx0", |
| "rx0", |
| "gip3"; |
| mboxes = <&lsio_mu1 0 0 |
| &lsio_mu1 1 0 |
| &lsio_mu1 3 3>; |
| |
| pd: power-controller { |
| compatible = "fsl,imx8qm-scu-pd", "fsl,scu-pd"; |
| #power-domain-cells = <1>; |
| }; |
| |
| clk: clock-controller { |
| compatible = "fsl,imx8qm-clk", "fsl,scu-clk"; |
| #clock-cells = <2>; |
| }; |
| |
| iomuxc: pinctrl { |
| compatible = "fsl,imx8qm-iomuxc"; |
| }; |
| |
| rtc: rtc { |
| compatible = "fsl,imx8qxp-sc-rtc"; |
| }; |
| }; |
| |
| /* sorted in register address */ |
| #include "imx8-ss-img.dtsi" |
| #include "imx8-ss-dma.dtsi" |
| #include "imx8-ss-conn.dtsi" |
| #include "imx8-ss-lsio.dtsi" |
| }; |
| |
| #include "imx8qm-ss-img.dtsi" |
| #include "imx8qm-ss-dma.dtsi" |
| #include "imx8qm-ss-conn.dtsi" |
| #include "imx8qm-ss-lsio.dtsi" |
