| // SPDX-License-Identifier: GPL-2.0-only |
| /* |
| * Copyright (c) 2021, The Linux Foundation. All rights reserved. |
| */ |
| |
| #include <linux/clk-provider.h> |
| #include <linux/err.h> |
| #include <linux/kernel.h> |
| #include <linux/module.h> |
| #include <linux/of_device.h> |
| #include <linux/of.h> |
| #include <linux/regmap.h> |
| |
| #include <dt-bindings/clock/qcom,camcc-sc7280.h> |
| |
| #include "clk-alpha-pll.h" |
| #include "clk-branch.h" |
| #include "clk-rcg.h" |
| #include "common.h" |
| #include "gdsc.h" |
| #include "reset.h" |
| |
| enum { |
| P_BI_TCXO, |
| P_CAM_CC_PLL0_OUT_EVEN, |
| P_CAM_CC_PLL0_OUT_MAIN, |
| P_CAM_CC_PLL0_OUT_ODD, |
| P_CAM_CC_PLL1_OUT_EVEN, |
| P_CAM_CC_PLL2_OUT_AUX2, |
| P_CAM_CC_PLL2_OUT_EARLY, |
| P_CAM_CC_PLL3_OUT_EVEN, |
| P_CAM_CC_PLL4_OUT_EVEN, |
| P_CAM_CC_PLL5_OUT_EVEN, |
| P_CAM_CC_PLL6_OUT_EVEN, |
| P_CAM_CC_PLL6_OUT_MAIN, |
| P_CAM_CC_PLL6_OUT_ODD, |
| P_SLEEP_CLK, |
| }; |
| |
| static struct pll_vco lucid_vco[] = { |
| { 249600000, 2000000000, 0 }, |
| }; |
| |
| static struct pll_vco zonda_vco[] = { |
| { 595200000UL, 3600000000UL, 0 }, |
| }; |
| |
| /* 1200MHz Configuration */ |
| static const struct alpha_pll_config cam_cc_pll0_config = { |
| .l = 0x3E, |
| .alpha = 0x8000, |
| .config_ctl_val = 0x20485699, |
| .config_ctl_hi_val = 0x00002261, |
| .config_ctl_hi1_val = 0x329A299C, |
| .user_ctl_val = 0x00003101, |
| .user_ctl_hi_val = 0x00000805, |
| .user_ctl_hi1_val = 0x00000000, |
| }; |
| |
| static struct clk_alpha_pll cam_cc_pll0 = { |
| .offset = 0x0, |
| .vco_table = lucid_vco, |
| .num_vco = ARRAY_SIZE(lucid_vco), |
| .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], |
| .clkr = { |
| .hw.init = &(struct clk_init_data){ |
| .name = "cam_cc_pll0", |
| .parent_data = &(const struct clk_parent_data){ |
| .fw_name = "bi_tcxo", |
| }, |
| .num_parents = 1, |
| .ops = &clk_alpha_pll_lucid_ops, |
| }, |
| }, |
| }; |
| |
| static const struct clk_div_table post_div_table_cam_cc_pll0_out_even[] = { |
| { 0x1, 2 }, |
| { } |
| }; |
| |
| static struct clk_alpha_pll_postdiv cam_cc_pll0_out_even = { |
| .offset = 0x0, |
| .post_div_shift = 8, |
| .post_div_table = post_div_table_cam_cc_pll0_out_even, |
| .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll0_out_even), |
| .width = 4, |
| .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], |
| .clkr.hw.init = &(struct clk_init_data){ |
| .name = "cam_cc_pll0_out_even", |
| .parent_data = &(const struct clk_parent_data){ |
| .hw = &cam_cc_pll0.clkr.hw, |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_alpha_pll_postdiv_lucid_ops, |
| }, |
| }; |
| |
| static const struct clk_div_table post_div_table_cam_cc_pll0_out_odd[] = { |
| { 0x3, 3 }, |
| { } |
| }; |
| |
| static struct clk_alpha_pll_postdiv cam_cc_pll0_out_odd = { |
| .offset = 0x0, |
| .post_div_shift = 12, |
| .post_div_table = post_div_table_cam_cc_pll0_out_odd, |
| .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll0_out_odd), |
| .width = 4, |
| .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], |
| .clkr.hw.init = &(struct clk_init_data){ |
| .name = "cam_cc_pll0_out_odd", |
| .parent_data = &(const struct clk_parent_data){ |
| .hw = &cam_cc_pll0.clkr.hw, |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_alpha_pll_postdiv_lucid_ops, |
| }, |
| }; |
| |
| /* 600MHz Configuration */ |
| static const struct alpha_pll_config cam_cc_pll1_config = { |
| .l = 0x1F, |
| .alpha = 0x4000, |
| .config_ctl_val = 0x20485699, |
| .config_ctl_hi_val = 0x00002261, |
| .config_ctl_hi1_val = 0x329A299C, |
| .user_ctl_val = 0x00000101, |
| .user_ctl_hi_val = 0x00000805, |
| .user_ctl_hi1_val = 0x00000000, |
| }; |
| |
| static struct clk_alpha_pll cam_cc_pll1 = { |
| .offset = 0x1000, |
| .vco_table = lucid_vco, |
| .num_vco = ARRAY_SIZE(lucid_vco), |
| .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], |
| .clkr = { |
| .hw.init = &(struct clk_init_data){ |
| .name = "cam_cc_pll1", |
| .parent_data = &(const struct clk_parent_data){ |
| .fw_name = "bi_tcxo", |
| }, |
| .num_parents = 1, |
| .ops = &clk_alpha_pll_lucid_ops, |
| }, |
| }, |
| }; |
| |
| static const struct clk_div_table post_div_table_cam_cc_pll1_out_even[] = { |
| { 0x1, 2 }, |
| { } |
| }; |
| |
| static struct clk_alpha_pll_postdiv cam_cc_pll1_out_even = { |
| .offset = 0x1000, |
| .post_div_shift = 8, |
| .post_div_table = post_div_table_cam_cc_pll1_out_even, |
| .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll1_out_even), |
| .width = 4, |
| .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], |
| .clkr.hw.init = &(struct clk_init_data){ |
| .name = "cam_cc_pll1_out_even", |
| .parent_data = &(const struct clk_parent_data){ |
| .hw = &cam_cc_pll1.clkr.hw, |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_alpha_pll_postdiv_lucid_ops, |
| }, |
| }; |
| |
| /* 1440MHz Configuration */ |
| static const struct alpha_pll_config cam_cc_pll2_config = { |
| .l = 0x4B, |
| .alpha = 0x0, |
| .config_ctl_val = 0x08200800, |
| .config_ctl_hi_val = 0x05022011, |
| .config_ctl_hi1_val = 0x08000000, |
| .user_ctl_val = 0x00000301, |
| }; |
| |
| static struct clk_alpha_pll cam_cc_pll2 = { |
| .offset = 0x2000, |
| .vco_table = zonda_vco, |
| .num_vco = ARRAY_SIZE(zonda_vco), |
| .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_ZONDA], |
| .clkr = { |
| .hw.init = &(struct clk_init_data){ |
| .name = "cam_cc_pll2", |
| .parent_data = &(const struct clk_parent_data){ |
| .fw_name = "bi_tcxo", |
| }, |
| .num_parents = 1, |
| .ops = &clk_alpha_pll_zonda_ops, |
| }, |
| }, |
| }; |
| |
| static const struct clk_div_table post_div_table_cam_cc_pll2_out_aux[] = { |
| { 0x3, 4 }, |
| { } |
| }; |
| |
| static struct clk_alpha_pll_postdiv cam_cc_pll2_out_aux = { |
| .offset = 0x2000, |
| .post_div_shift = 8, |
| .post_div_table = post_div_table_cam_cc_pll2_out_aux, |
| .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll2_out_aux), |
| .width = 2, |
| .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_ZONDA], |
| .clkr.hw.init = &(struct clk_init_data){ |
| .name = "cam_cc_pll2_out_aux", |
| .parent_data = &(const struct clk_parent_data){ |
| .hw = &cam_cc_pll2.clkr.hw, |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_alpha_pll_postdiv_zonda_ops, |
| }, |
| }; |
| |
| static const struct clk_div_table post_div_table_cam_cc_pll2_out_aux2[] = { |
| { 0x3, 4 }, |
| { } |
| }; |
| |
| static struct clk_alpha_pll_postdiv cam_cc_pll2_out_aux2 = { |
| .offset = 0x2000, |
| .post_div_shift = 8, |
| .post_div_table = post_div_table_cam_cc_pll2_out_aux2, |
| .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll2_out_aux2), |
| .width = 2, |
| .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_ZONDA], |
| .clkr.hw.init = &(struct clk_init_data){ |
| .name = "cam_cc_pll2_out_aux2", |
| .parent_data = &(const struct clk_parent_data){ |
| .hw = &cam_cc_pll2.clkr.hw, |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_alpha_pll_postdiv_zonda_ops, |
| }, |
| }; |
| |
| /* 760MHz Configuration */ |
| static const struct alpha_pll_config cam_cc_pll3_config = { |
| .l = 0x27, |
| .alpha = 0x9555, |
| .config_ctl_val = 0x20485699, |
| .config_ctl_hi_val = 0x00002261, |
| .config_ctl_hi1_val = 0x329A299C, |
| .user_ctl_val = 0x00000101, |
| .user_ctl_hi_val = 0x00000805, |
| .user_ctl_hi1_val = 0x00000000, |
| }; |
| |
| static struct clk_alpha_pll cam_cc_pll3 = { |
| .offset = 0x3000, |
| .vco_table = lucid_vco, |
| .num_vco = ARRAY_SIZE(lucid_vco), |
| .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], |
| .clkr = { |
| .hw.init = &(struct clk_init_data){ |
| .name = "cam_cc_pll3", |
| .parent_data = &(const struct clk_parent_data){ |
| .fw_name = "bi_tcxo", |
| }, |
| .num_parents = 1, |
| .ops = &clk_alpha_pll_lucid_ops, |
| }, |
| }, |
| }; |
| |
| static const struct clk_div_table post_div_table_cam_cc_pll3_out_even[] = { |
| { 0x1, 2 }, |
| { } |
| }; |
| |
| static struct clk_alpha_pll_postdiv cam_cc_pll3_out_even = { |
| .offset = 0x3000, |
| .post_div_shift = 8, |
| .post_div_table = post_div_table_cam_cc_pll3_out_even, |
| .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll3_out_even), |
| .width = 4, |
| .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], |
| .clkr.hw.init = &(struct clk_init_data){ |
| .name = "cam_cc_pll3_out_even", |
| .parent_data = &(const struct clk_parent_data){ |
| .hw = &cam_cc_pll3.clkr.hw, |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_alpha_pll_postdiv_lucid_ops, |
| }, |
| }; |
| |
| /* 760MHz Configuration */ |
| static const struct alpha_pll_config cam_cc_pll4_config = { |
| .l = 0x27, |
| .alpha = 0x9555, |
| .config_ctl_val = 0x20485699, |
| .config_ctl_hi_val = 0x00002261, |
| .config_ctl_hi1_val = 0x329A299C, |
| .user_ctl_val = 0x00000101, |
| .user_ctl_hi_val = 0x00000805, |
| .user_ctl_hi1_val = 0x00000000, |
| }; |
| |
| static struct clk_alpha_pll cam_cc_pll4 = { |
| .offset = 0x4000, |
| .vco_table = lucid_vco, |
| .num_vco = ARRAY_SIZE(lucid_vco), |
| .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], |
| .clkr = { |
| .hw.init = &(struct clk_init_data){ |
| .name = "cam_cc_pll4", |
| .parent_data = &(const struct clk_parent_data){ |
| .fw_name = "bi_tcxo", |
| }, |
| .num_parents = 1, |
| .ops = &clk_alpha_pll_lucid_ops, |
| }, |
| }, |
| }; |
| |
| static const struct clk_div_table post_div_table_cam_cc_pll4_out_even[] = { |
| { 0x1, 2 }, |
| { } |
| }; |
| |
| static struct clk_alpha_pll_postdiv cam_cc_pll4_out_even = { |
| .offset = 0x4000, |
| .post_div_shift = 8, |
| .post_div_table = post_div_table_cam_cc_pll4_out_even, |
| .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll4_out_even), |
| .width = 4, |
| .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], |
| .clkr.hw.init = &(struct clk_init_data){ |
| .name = "cam_cc_pll4_out_even", |
| .parent_data = &(const struct clk_parent_data){ |
| .hw = &cam_cc_pll4.clkr.hw, |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_alpha_pll_postdiv_lucid_ops, |
| }, |
| }; |
| |
| /* 760MHz Configuration */ |
| static const struct alpha_pll_config cam_cc_pll5_config = { |
| .l = 0x27, |
| .alpha = 0x9555, |
| .config_ctl_val = 0x20485699, |
| .config_ctl_hi_val = 0x00002261, |
| .config_ctl_hi1_val = 0x329A299C, |
| .user_ctl_val = 0x00000101, |
| .user_ctl_hi_val = 0x00000805, |
| .user_ctl_hi1_val = 0x00000000, |
| }; |
| |
| static struct clk_alpha_pll cam_cc_pll5 = { |
| .offset = 0x5000, |
| .vco_table = lucid_vco, |
| .num_vco = ARRAY_SIZE(lucid_vco), |
| .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], |
| .clkr = { |
| .hw.init = &(struct clk_init_data){ |
| .name = "cam_cc_pll5", |
| .parent_data = &(const struct clk_parent_data){ |
| .fw_name = "bi_tcxo", |
| }, |
| .num_parents = 1, |
| .ops = &clk_alpha_pll_lucid_ops, |
| }, |
| }, |
| }; |
| |
| static const struct clk_div_table post_div_table_cam_cc_pll5_out_even[] = { |
| { 0x1, 2 }, |
| { } |
| }; |
| |
| static struct clk_alpha_pll_postdiv cam_cc_pll5_out_even = { |
| .offset = 0x5000, |
| .post_div_shift = 8, |
| .post_div_table = post_div_table_cam_cc_pll5_out_even, |
| .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll5_out_even), |
| .width = 4, |
| .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], |
| .clkr.hw.init = &(struct clk_init_data){ |
| .name = "cam_cc_pll5_out_even", |
| .parent_data = &(const struct clk_parent_data){ |
| .hw = &cam_cc_pll5.clkr.hw, |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_alpha_pll_postdiv_lucid_ops, |
| }, |
| }; |
| |
| /* 960MHz Configuration */ |
| static const struct alpha_pll_config cam_cc_pll6_config = { |
| .l = 0x32, |
| .alpha = 0x0, |
| .config_ctl_val = 0x20485699, |
| .config_ctl_hi_val = 0x00002261, |
| .config_ctl_hi1_val = 0x329A299C, |
| .user_ctl_val = 0x00003101, |
| .user_ctl_hi_val = 0x00000805, |
| .user_ctl_hi1_val = 0x00000000, |
| }; |
| |
| static struct clk_alpha_pll cam_cc_pll6 = { |
| .offset = 0x6000, |
| .vco_table = lucid_vco, |
| .num_vco = ARRAY_SIZE(lucid_vco), |
| .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], |
| .clkr = { |
| .hw.init = &(struct clk_init_data){ |
| .name = "cam_cc_pll6", |
| .parent_data = &(const struct clk_parent_data){ |
| .fw_name = "bi_tcxo", |
| }, |
| .num_parents = 1, |
| .ops = &clk_alpha_pll_lucid_ops, |
| }, |
| }, |
| }; |
| |
| static const struct clk_div_table post_div_table_cam_cc_pll6_out_even[] = { |
| { 0x1, 2 }, |
| { } |
| }; |
| |
| static struct clk_alpha_pll_postdiv cam_cc_pll6_out_even = { |
| .offset = 0x6000, |
| .post_div_shift = 8, |
| .post_div_table = post_div_table_cam_cc_pll6_out_even, |
| .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll6_out_even), |
| .width = 4, |
| .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], |
| .clkr.hw.init = &(struct clk_init_data){ |
| .name = "cam_cc_pll6_out_even", |
| .parent_data = &(const struct clk_parent_data){ |
| .hw = &cam_cc_pll6.clkr.hw, |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_alpha_pll_postdiv_lucid_ops, |
| }, |
| }; |
| |
| static const struct clk_div_table post_div_table_cam_cc_pll6_out_odd[] = { |
| { 0x3, 3 }, |
| { } |
| }; |
| |
| static struct clk_alpha_pll_postdiv cam_cc_pll6_out_odd = { |
| .offset = 0x6000, |
| .post_div_shift = 12, |
| .post_div_table = post_div_table_cam_cc_pll6_out_odd, |
| .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll6_out_odd), |
| .width = 4, |
| .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], |
| .clkr.hw.init = &(struct clk_init_data){ |
| .name = "cam_cc_pll6_out_odd", |
| .parent_data = &(const struct clk_parent_data){ |
| .hw = &cam_cc_pll6.clkr.hw, |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_alpha_pll_postdiv_lucid_ops, |
| }, |
| }; |
| |
| static const struct parent_map cam_cc_parent_map_0[] = { |
| { P_BI_TCXO, 0 }, |
| { P_CAM_CC_PLL0_OUT_MAIN, 1 }, |
| { P_CAM_CC_PLL0_OUT_EVEN, 2 }, |
| { P_CAM_CC_PLL0_OUT_ODD, 3 }, |
| { P_CAM_CC_PLL6_OUT_EVEN, 5 }, |
| }; |
| |
| static const struct clk_parent_data cam_cc_parent_data_0[] = { |
| { .fw_name = "bi_tcxo" }, |
| { .hw = &cam_cc_pll0.clkr.hw }, |
| { .hw = &cam_cc_pll0_out_even.clkr.hw }, |
| { .hw = &cam_cc_pll0_out_odd.clkr.hw }, |
| { .hw = &cam_cc_pll6_out_even.clkr.hw }, |
| }; |
| |
| static const struct parent_map cam_cc_parent_map_1[] = { |
| { P_BI_TCXO, 0 }, |
| { P_CAM_CC_PLL0_OUT_MAIN, 1 }, |
| { P_CAM_CC_PLL0_OUT_EVEN, 2 }, |
| { P_CAM_CC_PLL0_OUT_ODD, 3 }, |
| { P_CAM_CC_PLL6_OUT_MAIN, 4 }, |
| { P_CAM_CC_PLL6_OUT_EVEN, 5 }, |
| }; |
| |
| static const struct clk_parent_data cam_cc_parent_data_1[] = { |
| { .fw_name = "bi_tcxo" }, |
| { .hw = &cam_cc_pll0.clkr.hw }, |
| { .hw = &cam_cc_pll0_out_even.clkr.hw }, |
| { .hw = &cam_cc_pll0_out_odd.clkr.hw }, |
| { .hw = &cam_cc_pll6.clkr.hw }, |
| { .hw = &cam_cc_pll6_out_even.clkr.hw }, |
| }; |
| |
| static const struct parent_map cam_cc_parent_map_2[] = { |
| { P_BI_TCXO, 0 }, |
| { P_CAM_CC_PLL2_OUT_AUX2, 3 }, |
| { P_CAM_CC_PLL2_OUT_EARLY, 5 }, |
| }; |
| |
| static const struct clk_parent_data cam_cc_parent_data_2[] = { |
| { .fw_name = "bi_tcxo" }, |
| { .hw = &cam_cc_pll2_out_aux2.clkr.hw }, |
| { .hw = &cam_cc_pll2.clkr.hw }, |
| }; |
| |
| static const struct parent_map cam_cc_parent_map_3[] = { |
| { P_BI_TCXO, 0 }, |
| { P_CAM_CC_PLL0_OUT_MAIN, 1 }, |
| { P_CAM_CC_PLL0_OUT_EVEN, 2 }, |
| { P_CAM_CC_PLL0_OUT_ODD, 3 }, |
| { P_CAM_CC_PLL6_OUT_EVEN, 5 }, |
| { P_CAM_CC_PLL6_OUT_ODD, 6 }, |
| }; |
| |
| static const struct clk_parent_data cam_cc_parent_data_3[] = { |
| { .fw_name = "bi_tcxo" }, |
| { .hw = &cam_cc_pll0.clkr.hw }, |
| { .hw = &cam_cc_pll0_out_even.clkr.hw }, |
| { .hw = &cam_cc_pll0_out_odd.clkr.hw }, |
| { .hw = &cam_cc_pll6_out_even.clkr.hw }, |
| { .hw = &cam_cc_pll6_out_odd.clkr.hw }, |
| }; |
| |
| static const struct parent_map cam_cc_parent_map_4[] = { |
| { P_BI_TCXO, 0 }, |
| { P_CAM_CC_PLL3_OUT_EVEN, 6 }, |
| }; |
| |
| static const struct clk_parent_data cam_cc_parent_data_4[] = { |
| { .fw_name = "bi_tcxo" }, |
| { .hw = &cam_cc_pll3_out_even.clkr.hw }, |
| }; |
| |
| static const struct parent_map cam_cc_parent_map_5[] = { |
| { P_BI_TCXO, 0 }, |
| { P_CAM_CC_PLL4_OUT_EVEN, 6 }, |
| }; |
| |
| static const struct clk_parent_data cam_cc_parent_data_5[] = { |
| { .fw_name = "bi_tcxo" }, |
| { .hw = &cam_cc_pll4_out_even.clkr.hw }, |
| }; |
| |
| static const struct parent_map cam_cc_parent_map_6[] = { |
| { P_BI_TCXO, 0 }, |
| { P_CAM_CC_PLL5_OUT_EVEN, 6 }, |
| }; |
| |
| static const struct clk_parent_data cam_cc_parent_data_6[] = { |
| { .fw_name = "bi_tcxo" }, |
| { .hw = &cam_cc_pll5_out_even.clkr.hw }, |
| }; |
| |
| static const struct parent_map cam_cc_parent_map_7[] = { |
| { P_BI_TCXO, 0 }, |
| { P_CAM_CC_PLL1_OUT_EVEN, 4 }, |
| }; |
| |
| static const struct clk_parent_data cam_cc_parent_data_7[] = { |
| { .fw_name = "bi_tcxo" }, |
| { .hw = &cam_cc_pll1_out_even.clkr.hw }, |
| }; |
| |
| static const struct parent_map cam_cc_parent_map_8[] = { |
| { P_SLEEP_CLK, 0 }, |
| }; |
| |
| static const struct clk_parent_data cam_cc_parent_data_8[] = { |
| { .fw_name = "sleep_clk" }, |
| }; |
| |
| static const struct parent_map cam_cc_parent_map_9[] = { |
| { P_BI_TCXO, 0 }, |
| }; |
| |
| static const struct clk_parent_data cam_cc_parent_data_9_ao[] = { |
| { .fw_name = "bi_tcxo_ao" }, |
| }; |
| |
| static const struct freq_tbl ftbl_cam_cc_bps_clk_src[] = { |
| F(19200000, P_BI_TCXO, 1, 0, 0), |
| F(100000000, P_CAM_CC_PLL0_OUT_ODD, 4, 0, 0), |
| F(200000000, P_CAM_CC_PLL0_OUT_ODD, 2, 0, 0), |
| F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), |
| F(480000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0), |
| F(600000000, P_CAM_CC_PLL0_OUT_MAIN, 2, 0, 0), |
| { } |
| }; |
| |
| static struct clk_rcg2 cam_cc_bps_clk_src = { |
| .cmd_rcgr = 0x7010, |
| .mnd_width = 0, |
| .hid_width = 5, |
| .parent_map = cam_cc_parent_map_0, |
| .freq_tbl = ftbl_cam_cc_bps_clk_src, |
| .clkr.hw.init = &(struct clk_init_data){ |
| .name = "cam_cc_bps_clk_src", |
| .parent_data = cam_cc_parent_data_0, |
| .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), |
| .ops = &clk_rcg2_shared_ops, |
| }, |
| }; |
| |
| static const struct freq_tbl ftbl_cam_cc_camnoc_axi_clk_src[] = { |
| F(19200000, P_BI_TCXO, 1, 0, 0), |
| F(150000000, P_CAM_CC_PLL0_OUT_EVEN, 4, 0, 0), |
| F(240000000, P_CAM_CC_PLL6_OUT_EVEN, 2, 0, 0), |
| F(320000000, P_CAM_CC_PLL6_OUT_ODD, 1, 0, 0), |
| F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0), |
| F(480000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0), |
| { } |
| }; |
| |
| static struct clk_rcg2 cam_cc_camnoc_axi_clk_src = { |
| .cmd_rcgr = 0xc124, |
| .mnd_width = 0, |
| .hid_width = 5, |
| .parent_map = cam_cc_parent_map_3, |
| .freq_tbl = ftbl_cam_cc_camnoc_axi_clk_src, |
| .clkr.hw.init = &(struct clk_init_data){ |
| .name = "cam_cc_camnoc_axi_clk_src", |
| .parent_data = cam_cc_parent_data_3, |
| .num_parents = ARRAY_SIZE(cam_cc_parent_data_3), |
| .ops = &clk_rcg2_shared_ops, |
| }, |
| }; |
| |
| static const struct freq_tbl ftbl_cam_cc_cci_0_clk_src[] = { |
| F(19200000, P_BI_TCXO, 1, 0, 0), |
| F(37500000, P_CAM_CC_PLL0_OUT_EVEN, 16, 0, 0), |
| { } |
| }; |
| |
| static struct clk_rcg2 cam_cc_cci_0_clk_src = { |
| .cmd_rcgr = 0xc0e0, |
| .mnd_width = 8, |
| .hid_width = 5, |
| .parent_map = cam_cc_parent_map_0, |
| .freq_tbl = ftbl_cam_cc_cci_0_clk_src, |
| .clkr.hw.init = &(struct clk_init_data){ |
| .name = "cam_cc_cci_0_clk_src", |
| .parent_data = cam_cc_parent_data_0, |
| .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), |
| .ops = &clk_rcg2_shared_ops, |
| }, |
| }; |
| |
| static struct clk_rcg2 cam_cc_cci_1_clk_src = { |
| .cmd_rcgr = 0xc0fc, |
| .mnd_width = 8, |
| .hid_width = 5, |
| .parent_map = cam_cc_parent_map_0, |
| .freq_tbl = ftbl_cam_cc_cci_0_clk_src, |
| .clkr.hw.init = &(struct clk_init_data){ |
| .name = "cam_cc_cci_1_clk_src", |
| .parent_data = cam_cc_parent_data_0, |
| .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), |
| .ops = &clk_rcg2_shared_ops, |
| }, |
| }; |
| |
| static const struct freq_tbl ftbl_cam_cc_cphy_rx_clk_src[] = { |
| F(19200000, P_BI_TCXO, 1, 0, 0), |
| F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0), |
| F(400000000, P_CAM_CC_PLL0_OUT_EVEN, 1.5, 0, 0), |
| { } |
| }; |
| |
| static struct clk_rcg2 cam_cc_cphy_rx_clk_src = { |
| .cmd_rcgr = 0xa064, |
| .mnd_width = 0, |
| .hid_width = 5, |
| .parent_map = cam_cc_parent_map_1, |
| .freq_tbl = ftbl_cam_cc_cphy_rx_clk_src, |
| .clkr.hw.init = &(struct clk_init_data){ |
| .name = "cam_cc_cphy_rx_clk_src", |
| .parent_data = cam_cc_parent_data_1, |
| .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), |
| .ops = &clk_rcg2_shared_ops, |
| }, |
| }; |
| |
| static const struct freq_tbl ftbl_cam_cc_csi0phytimer_clk_src[] = { |
| F(19200000, P_BI_TCXO, 1, 0, 0), |
| F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0), |
| { } |
| }; |
| |
| static struct clk_rcg2 cam_cc_csi0phytimer_clk_src = { |
| .cmd_rcgr = 0xe0ac, |
| .mnd_width = 0, |
| .hid_width = 5, |
| .parent_map = cam_cc_parent_map_0, |
| .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, |
| .clkr.hw.init = &(struct clk_init_data){ |
| .name = "cam_cc_csi0phytimer_clk_src", |
| .parent_data = cam_cc_parent_data_0, |
| .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), |
| .ops = &clk_rcg2_shared_ops, |
| }, |
| }; |
| |
| static struct clk_rcg2 cam_cc_csi1phytimer_clk_src = { |
| .cmd_rcgr = 0xe0d0, |
| .mnd_width = 0, |
| .hid_width = 5, |
| .parent_map = cam_cc_parent_map_0, |
| .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, |
| .clkr.hw.init = &(struct clk_init_data){ |
| .name = "cam_cc_csi1phytimer_clk_src", |
| .parent_data = cam_cc_parent_data_0, |
| .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), |
| .ops = &clk_rcg2_shared_ops, |
| }, |
| }; |
| |
| static struct clk_rcg2 cam_cc_csi2phytimer_clk_src = { |
| .cmd_rcgr = 0xe0f4, |
| .mnd_width = 0, |
| .hid_width = 5, |
| .parent_map = cam_cc_parent_map_0, |
| .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, |
| .clkr.hw.init = &(struct clk_init_data){ |
| .name = "cam_cc_csi2phytimer_clk_src", |
| .parent_data = cam_cc_parent_data_0, |
| .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), |
| .ops = &clk_rcg2_shared_ops, |
| }, |
| }; |
| |
| static struct clk_rcg2 cam_cc_csi3phytimer_clk_src = { |
| .cmd_rcgr = 0xe11c, |
| .mnd_width = 0, |
| .hid_width = 5, |
| .parent_map = cam_cc_parent_map_0, |
| .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, |
| .clkr.hw.init = &(struct clk_init_data){ |
| .name = "cam_cc_csi3phytimer_clk_src", |
| .parent_data = cam_cc_parent_data_0, |
| .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), |
| .ops = &clk_rcg2_shared_ops, |
| }, |
| }; |
| |
| static struct clk_rcg2 cam_cc_csi4phytimer_clk_src = { |
| .cmd_rcgr = 0xe140, |
| .mnd_width = 0, |
| .hid_width = 5, |
| .parent_map = cam_cc_parent_map_0, |
| .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, |
| .clkr.hw.init = &(struct clk_init_data){ |
| .name = "cam_cc_csi4phytimer_clk_src", |
| .parent_data = cam_cc_parent_data_0, |
| .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), |
| .ops = &clk_rcg2_shared_ops, |
| }, |
| }; |
| |
| static const struct freq_tbl ftbl_cam_cc_fast_ahb_clk_src[] = { |
| F(19200000, P_BI_TCXO, 1, 0, 0), |
| F(50000000, P_CAM_CC_PLL0_OUT_EVEN, 12, 0, 0), |
| F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0), |
| F(200000000, P_CAM_CC_PLL0_OUT_EVEN, 3, 0, 0), |
| F(300000000, P_CAM_CC_PLL0_OUT_MAIN, 4, 0, 0), |
| F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0), |
| { } |
| }; |
| |
| static struct clk_rcg2 cam_cc_fast_ahb_clk_src = { |
| .cmd_rcgr = 0x703c, |
| .mnd_width = 0, |
| .hid_width = 5, |
| .parent_map = cam_cc_parent_map_0, |
| .freq_tbl = ftbl_cam_cc_fast_ahb_clk_src, |
| .clkr.hw.init = &(struct clk_init_data){ |
| .name = "cam_cc_fast_ahb_clk_src", |
| .parent_data = cam_cc_parent_data_0, |
| .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), |
| .ops = &clk_rcg2_shared_ops, |
| }, |
| }; |
| |
| static const struct freq_tbl ftbl_cam_cc_icp_clk_src[] = { |
| F(19200000, P_BI_TCXO, 1, 0, 0), |
| F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), |
| F(480000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0), |
| F(600000000, P_CAM_CC_PLL0_OUT_MAIN, 2, 0, 0), |
| { } |
| }; |
| |
| static struct clk_rcg2 cam_cc_icp_clk_src = { |
| .cmd_rcgr = 0xc0b8, |
| .mnd_width = 0, |
| .hid_width = 5, |
| .parent_map = cam_cc_parent_map_0, |
| .freq_tbl = ftbl_cam_cc_icp_clk_src, |
| .clkr.hw.init = &(struct clk_init_data){ |
| .name = "cam_cc_icp_clk_src", |
| .parent_data = cam_cc_parent_data_0, |
| .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), |
| .ops = &clk_rcg2_shared_ops, |
| }, |
| }; |
| |
| static const struct freq_tbl ftbl_cam_cc_ife_0_clk_src[] = { |
| F(19200000, P_BI_TCXO, 1, 0, 0), |
| F(380000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), |
| F(510000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), |
| F(637000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), |
| F(760000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), |
| { } |
| }; |
| |
| static struct clk_rcg2 cam_cc_ife_0_clk_src = { |
| .cmd_rcgr = 0xa010, |
| .mnd_width = 0, |
| .hid_width = 5, |
| .parent_map = cam_cc_parent_map_4, |
| .freq_tbl = ftbl_cam_cc_ife_0_clk_src, |
| .clkr.hw.init = &(struct clk_init_data){ |
| .name = "cam_cc_ife_0_clk_src", |
| .parent_data = cam_cc_parent_data_4, |
| .num_parents = ARRAY_SIZE(cam_cc_parent_data_4), |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_rcg2_shared_ops, |
| }, |
| }; |
| |
| static const struct freq_tbl ftbl_cam_cc_ife_1_clk_src[] = { |
| F(19200000, P_BI_TCXO, 1, 0, 0), |
| F(380000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), |
| F(510000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), |
| F(637000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), |
| F(760000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), |
| { } |
| }; |
| |
| static struct clk_rcg2 cam_cc_ife_1_clk_src = { |
| .cmd_rcgr = 0xb010, |
| .mnd_width = 0, |
| .hid_width = 5, |
| .parent_map = cam_cc_parent_map_5, |
| .freq_tbl = ftbl_cam_cc_ife_1_clk_src, |
| .clkr.hw.init = &(struct clk_init_data){ |
| .name = "cam_cc_ife_1_clk_src", |
| .parent_data = cam_cc_parent_data_5, |
| .num_parents = ARRAY_SIZE(cam_cc_parent_data_5), |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_rcg2_shared_ops, |
| }, |
| }; |
| |
| static const struct freq_tbl ftbl_cam_cc_ife_0_csid_clk_src[] = { |
| F(19200000, P_BI_TCXO, 1, 0, 0), |
| F(75000000, P_CAM_CC_PLL0_OUT_EVEN, 8, 0, 0), |
| F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0), |
| F(400000000, P_CAM_CC_PLL0_OUT_EVEN, 1.5, 0, 0), |
| { } |
| }; |
| |
| static struct clk_rcg2 cam_cc_ife_0_csid_clk_src = { |
| .cmd_rcgr = 0xa03c, |
| .mnd_width = 0, |
| .hid_width = 5, |
| .parent_map = cam_cc_parent_map_1, |
| .freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src, |
| .clkr.hw.init = &(struct clk_init_data){ |
| .name = "cam_cc_ife_0_csid_clk_src", |
| .parent_data = cam_cc_parent_data_1, |
| .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), |
| .ops = &clk_rcg2_shared_ops, |
| }, |
| }; |
| |
| static struct clk_rcg2 cam_cc_ife_1_csid_clk_src = { |
| .cmd_rcgr = 0xb03c, |
| .mnd_width = 0, |
| .hid_width = 5, |
| .parent_map = cam_cc_parent_map_1, |
| .freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src, |
| .clkr.hw.init = &(struct clk_init_data){ |
| .name = "cam_cc_ife_1_csid_clk_src", |
| .parent_data = cam_cc_parent_data_1, |
| .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), |
| .ops = &clk_rcg2_shared_ops, |
| }, |
| }; |
| |
| static const struct freq_tbl ftbl_cam_cc_ife_2_clk_src[] = { |
| F(19200000, P_BI_TCXO, 1, 0, 0), |
| F(380000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0), |
| F(510000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0), |
| F(637000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0), |
| F(760000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0), |
| { } |
| }; |
| |
| static struct clk_rcg2 cam_cc_ife_2_clk_src = { |
| .cmd_rcgr = 0xb07c, |
| .mnd_width = 0, |
| .hid_width = 5, |
| .parent_map = cam_cc_parent_map_6, |
| .freq_tbl = ftbl_cam_cc_ife_2_clk_src, |
| .clkr.hw.init = &(struct clk_init_data){ |
| .name = "cam_cc_ife_2_clk_src", |
| .parent_data = cam_cc_parent_data_6, |
| .num_parents = ARRAY_SIZE(cam_cc_parent_data_6), |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_rcg2_shared_ops, |
| }, |
| }; |
| |
| static struct clk_rcg2 cam_cc_ife_2_csid_clk_src = { |
| .cmd_rcgr = 0xb0a8, |
| .mnd_width = 0, |
| .hid_width = 5, |
| .parent_map = cam_cc_parent_map_1, |
| .freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src, |
| .clkr.hw.init = &(struct clk_init_data){ |
| .name = "cam_cc_ife_2_csid_clk_src", |
| .parent_data = cam_cc_parent_data_1, |
| .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), |
| .ops = &clk_rcg2_shared_ops, |
| }, |
| }; |
| |
| static const struct freq_tbl ftbl_cam_cc_ife_lite_0_clk_src[] = { |
| F(19200000, P_BI_TCXO, 1, 0, 0), |
| F(320000000, P_CAM_CC_PLL6_OUT_ODD, 1, 0, 0), |
| F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), |
| F(480000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0), |
| F(600000000, P_CAM_CC_PLL0_OUT_MAIN, 2, 0, 0), |
| { } |
| }; |
| |
| static struct clk_rcg2 cam_cc_ife_lite_0_clk_src = { |
| .cmd_rcgr = 0xc004, |
| .mnd_width = 0, |
| .hid_width = 5, |
| .parent_map = cam_cc_parent_map_3, |
| .freq_tbl = ftbl_cam_cc_ife_lite_0_clk_src, |
| .clkr.hw.init = &(struct clk_init_data){ |
| .name = "cam_cc_ife_lite_0_clk_src", |
| .parent_data = cam_cc_parent_data_3, |
| .num_parents = ARRAY_SIZE(cam_cc_parent_data_3), |
| .ops = &clk_rcg2_shared_ops, |
| }, |
| }; |
| |
| static struct clk_rcg2 cam_cc_ife_lite_0_csid_clk_src = { |
| .cmd_rcgr = 0xc020, |
| .mnd_width = 0, |
| .hid_width = 5, |
| .parent_map = cam_cc_parent_map_1, |
| .freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src, |
| .clkr.hw.init = &(struct clk_init_data){ |
| .name = "cam_cc_ife_lite_0_csid_clk_src", |
| .parent_data = cam_cc_parent_data_1, |
| .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), |
| .ops = &clk_rcg2_shared_ops, |
| }, |
| }; |
| |
| static struct clk_rcg2 cam_cc_ife_lite_1_clk_src = { |
| .cmd_rcgr = 0xc048, |
| .mnd_width = 0, |
| .hid_width = 5, |
| .parent_map = cam_cc_parent_map_3, |
| .freq_tbl = ftbl_cam_cc_ife_lite_0_clk_src, |
| .clkr.hw.init = &(struct clk_init_data){ |
| .name = "cam_cc_ife_lite_1_clk_src", |
| .parent_data = cam_cc_parent_data_3, |
| .num_parents = ARRAY_SIZE(cam_cc_parent_data_3), |
| .ops = &clk_rcg2_shared_ops, |
| }, |
| }; |
| |
| static struct clk_rcg2 cam_cc_ife_lite_1_csid_clk_src = { |
| .cmd_rcgr = 0xc064, |
| .mnd_width = 0, |
| .hid_width = 5, |
| .parent_map = cam_cc_parent_map_1, |
| .freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src, |
| .clkr.hw.init = &(struct clk_init_data){ |
| .name = "cam_cc_ife_lite_1_csid_clk_src", |
| .parent_data = cam_cc_parent_data_1, |
| .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), |
| .ops = &clk_rcg2_shared_ops, |
| }, |
| }; |
| |
| static const struct freq_tbl ftbl_cam_cc_ipe_0_clk_src[] = { |
| F(19200000, P_BI_TCXO, 1, 0, 0), |
| F(300000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), |
| F(430000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), |
| F(520000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), |
| F(600000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), |
| { } |
| }; |
| |
| static struct clk_rcg2 cam_cc_ipe_0_clk_src = { |
| .cmd_rcgr = 0x8010, |
| .mnd_width = 0, |
| .hid_width = 5, |
| .parent_map = cam_cc_parent_map_7, |
| .freq_tbl = ftbl_cam_cc_ipe_0_clk_src, |
| .clkr.hw.init = &(struct clk_init_data){ |
| .name = "cam_cc_ipe_0_clk_src", |
| .parent_data = cam_cc_parent_data_7, |
| .num_parents = ARRAY_SIZE(cam_cc_parent_data_7), |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_rcg2_shared_ops, |
| }, |
| }; |
| |
| static struct clk_rcg2 cam_cc_jpeg_clk_src = { |
| .cmd_rcgr = 0xc08c, |
| .mnd_width = 0, |
| .hid_width = 5, |
| .parent_map = cam_cc_parent_map_0, |
| .freq_tbl = ftbl_cam_cc_bps_clk_src, |
| .clkr.hw.init = &(struct clk_init_data){ |
| .name = "cam_cc_jpeg_clk_src", |
| .parent_data = cam_cc_parent_data_0, |
| .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), |
| .ops = &clk_rcg2_shared_ops, |
| }, |
| }; |
| |
| static const struct freq_tbl ftbl_cam_cc_lrme_clk_src[] = { |
| F(19200000, P_BI_TCXO, 1, 0, 0), |
| F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0), |
| F(240000000, P_CAM_CC_PLL6_OUT_EVEN, 2, 0, 0), |
| F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0), |
| F(320000000, P_CAM_CC_PLL6_OUT_ODD, 1, 0, 0), |
| F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0), |
| { } |
| }; |
| |
| static struct clk_rcg2 cam_cc_lrme_clk_src = { |
| .cmd_rcgr = 0xc150, |
| .mnd_width = 0, |
| .hid_width = 5, |
| .parent_map = cam_cc_parent_map_3, |
| .freq_tbl = ftbl_cam_cc_lrme_clk_src, |
| .clkr.hw.init = &(struct clk_init_data){ |
| .name = "cam_cc_lrme_clk_src", |
| .parent_data = cam_cc_parent_data_3, |
| .num_parents = ARRAY_SIZE(cam_cc_parent_data_3), |
| .ops = &clk_rcg2_shared_ops, |
| }, |
| }; |
| |
| static const struct freq_tbl ftbl_cam_cc_mclk0_clk_src[] = { |
| F(19200000, P_CAM_CC_PLL2_OUT_EARLY, 1, 1, 75), |
| F(24000000, P_CAM_CC_PLL2_OUT_EARLY, 10, 1, 6), |
| F(34285714, P_CAM_CC_PLL2_OUT_EARLY, 2, 1, 21), |
| { } |
| }; |
| |
| static struct clk_rcg2 cam_cc_mclk0_clk_src = { |
| .cmd_rcgr = 0xe000, |
| .mnd_width = 8, |
| .hid_width = 5, |
| .parent_map = cam_cc_parent_map_2, |
| .freq_tbl = ftbl_cam_cc_mclk0_clk_src, |
| .clkr.hw.init = &(struct clk_init_data){ |
| .name = "cam_cc_mclk0_clk_src", |
| .parent_data = cam_cc_parent_data_2, |
| .num_parents = ARRAY_SIZE(cam_cc_parent_data_2), |
| .ops = &clk_rcg2_shared_ops, |
| }, |
| }; |
| |
| static struct clk_rcg2 cam_cc_mclk1_clk_src = { |
| .cmd_rcgr = 0xe01c, |
| .mnd_width = 8, |
| .hid_width = 5, |
| .parent_map = cam_cc_parent_map_2, |
| .freq_tbl = ftbl_cam_cc_mclk0_clk_src, |
| .clkr.hw.init = &(struct clk_init_data){ |
| .name = "cam_cc_mclk1_clk_src", |
| .parent_data = cam_cc_parent_data_2, |
| .num_parents = ARRAY_SIZE(cam_cc_parent_data_2), |
| .ops = &clk_rcg2_shared_ops, |
| }, |
| }; |
| |
| static struct clk_rcg2 cam_cc_mclk2_clk_src = { |
| .cmd_rcgr = 0xe038, |
| .mnd_width = 8, |
| .hid_width = 5, |
| .parent_map = cam_cc_parent_map_2, |
| .freq_tbl = ftbl_cam_cc_mclk0_clk_src, |
| .clkr.hw.init = &(struct clk_init_data){ |
| .name = "cam_cc_mclk2_clk_src", |
| .parent_data = cam_cc_parent_data_2, |
| .num_parents = ARRAY_SIZE(cam_cc_parent_data_2), |
| .ops = &clk_rcg2_shared_ops, |
| }, |
| }; |
| |
| static struct clk_rcg2 cam_cc_mclk3_clk_src = { |
| .cmd_rcgr = 0xe054, |
| .mnd_width = 8, |
| .hid_width = 5, |
| .parent_map = cam_cc_parent_map_2, |
| .freq_tbl = ftbl_cam_cc_mclk0_clk_src, |
| .clkr.hw.init = &(struct clk_init_data){ |
| .name = "cam_cc_mclk3_clk_src", |
| .parent_data = cam_cc_parent_data_2, |
| .num_parents = ARRAY_SIZE(cam_cc_parent_data_2), |
| .ops = &clk_rcg2_shared_ops, |
| }, |
| }; |
| |
| static struct clk_rcg2 cam_cc_mclk4_clk_src = { |
| .cmd_rcgr = 0xe070, |
| .mnd_width = 8, |
| .hid_width = 5, |
| .parent_map = cam_cc_parent_map_2, |
| .freq_tbl = ftbl_cam_cc_mclk0_clk_src, |
| .clkr.hw.init = &(struct clk_init_data){ |
| .name = "cam_cc_mclk4_clk_src", |
| .parent_data = cam_cc_parent_data_2, |
| .num_parents = ARRAY_SIZE(cam_cc_parent_data_2), |
| .ops = &clk_rcg2_shared_ops, |
| }, |
| }; |
| |
| static struct clk_rcg2 cam_cc_mclk5_clk_src = { |
| .cmd_rcgr = 0xe08c, |
| .mnd_width = 8, |
| .hid_width = 5, |
| .parent_map = cam_cc_parent_map_2, |
| .freq_tbl = ftbl_cam_cc_mclk0_clk_src, |
| .clkr.hw.init = &(struct clk_init_data){ |
| .name = "cam_cc_mclk5_clk_src", |
| .parent_data = cam_cc_parent_data_2, |
| .num_parents = ARRAY_SIZE(cam_cc_parent_data_2), |
| .ops = &clk_rcg2_shared_ops, |
| }, |
| }; |
| |
| static const struct freq_tbl ftbl_cam_cc_sleep_clk_src[] = { |
| F(32000, P_SLEEP_CLK, 1, 0, 0), |
| { } |
| }; |
| |
| static struct clk_rcg2 cam_cc_sleep_clk_src = { |
| .cmd_rcgr = 0xc1c0, |
| .mnd_width = 0, |
| .hid_width = 5, |
| .parent_map = cam_cc_parent_map_8, |
| .freq_tbl = ftbl_cam_cc_sleep_clk_src, |
| .clkr.hw.init = &(struct clk_init_data){ |
| .name = "cam_cc_sleep_clk_src", |
| .parent_data = cam_cc_parent_data_8, |
| .num_parents = ARRAY_SIZE(cam_cc_parent_data_8), |
| .ops = &clk_rcg2_ops, |
| }, |
| }; |
| |
| static const struct freq_tbl ftbl_cam_cc_slow_ahb_clk_src[] = { |
| F(19200000, P_BI_TCXO, 1, 0, 0), |
| F(80000000, P_CAM_CC_PLL0_OUT_EVEN, 7.5, 0, 0), |
| { } |
| }; |
| |
| static struct clk_rcg2 cam_cc_slow_ahb_clk_src = { |
| .cmd_rcgr = 0x7058, |
| .mnd_width = 8, |
| .hid_width = 5, |
| .parent_map = cam_cc_parent_map_0, |
| .freq_tbl = ftbl_cam_cc_slow_ahb_clk_src, |
| .clkr.hw.init = &(struct clk_init_data){ |
| .name = "cam_cc_slow_ahb_clk_src", |
| .parent_data = cam_cc_parent_data_0, |
| .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), |
| .ops = &clk_rcg2_shared_ops, |
| }, |
| }; |
| |
| static const struct freq_tbl ftbl_cam_cc_xo_clk_src[] = { |
| F(19200000, P_BI_TCXO, 1, 0, 0), |
| { } |
| }; |
| |
| static struct clk_rcg2 cam_cc_xo_clk_src = { |
| .cmd_rcgr = 0xc1a4, |
| .mnd_width = 0, |
| .hid_width = 5, |
| .parent_map = cam_cc_parent_map_9, |
| .freq_tbl = ftbl_cam_cc_xo_clk_src, |
| .clkr.hw.init = &(struct clk_init_data){ |
| .name = "cam_cc_xo_clk_src", |
| .parent_data = cam_cc_parent_data_9_ao, |
| .num_parents = ARRAY_SIZE(cam_cc_parent_data_9_ao), |
| .ops = &clk_rcg2_ops, |
| }, |
| }; |
| |
| static struct clk_branch cam_cc_bps_ahb_clk = { |
| .halt_reg = 0x7070, |
| .halt_check = BRANCH_HALT, |
| .clkr = { |
| .enable_reg = 0x7070, |
| .enable_mask = BIT(0), |
| .hw.init = &(struct clk_init_data){ |
| .name = "cam_cc_bps_ahb_clk", |
| .parent_data = &(const struct clk_parent_data){ |
| .hw = &cam_cc_slow_ahb_clk_src.clkr.hw, |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch cam_cc_bps_areg_clk = { |
| .halt_reg = 0x7054, |
| .halt_check = BRANCH_HALT, |
| .clkr = { |
| .enable_reg = 0x7054, |
| .enable_mask = BIT(0), |
| .hw.init = &(struct clk_init_data){ |
| .name = "cam_cc_bps_areg_clk", |
| .parent_data = &(const struct clk_parent_data){ |
| .hw = &cam_cc_fast_ahb_clk_src.clkr.hw, |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch cam_cc_bps_axi_clk = { |
| .halt_reg = 0x7038, |
| .halt_check = BRANCH_HALT, |
| .clkr = { |
| .enable_reg = 0x7038, |
| .enable_mask = BIT(0), |
| .hw.init = &(struct clk_init_data){ |
| .name = "cam_cc_bps_axi_clk", |
| .parent_data = &(const struct clk_parent_data){ |
| .hw = &cam_cc_camnoc_axi_clk_src.clkr.hw, |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch cam_cc_bps_clk = { |
| .halt_reg = 0x7028, |
| .halt_check = BRANCH_HALT, |
| .clkr = { |
| .enable_reg = 0x7028, |
| .enable_mask = BIT(0), |
| .hw.init = &(struct clk_init_data){ |
| .name = "cam_cc_bps_clk", |
| .parent_data = &(const struct clk_parent_data){ |
| .hw = &cam_cc_bps_clk_src.clkr.hw, |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch cam_cc_camnoc_axi_clk = { |
| .halt_reg = 0xc140, |
| .halt_check = BRANCH_HALT, |
| .clkr = { |
| .enable_reg = 0xc140, |
| .enable_mask = BIT(0), |
| .hw.init = &(struct clk_init_data){ |
| .name = "cam_cc_camnoc_axi_clk", |
| .parent_data = &(const struct clk_parent_data){ |
| .hw = &cam_cc_camnoc_axi_clk_src.clkr.hw, |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch cam_cc_camnoc_dcd_xo_clk = { |
| .halt_reg = 0xc148, |
| .halt_check = BRANCH_HALT, |
| .clkr = { |
| .enable_reg = 0xc148, |
| .enable_mask = BIT(0), |
| .hw.init = &(struct clk_init_data){ |
| .name = "cam_cc_camnoc_dcd_xo_clk", |
| .parent_data = &(const struct clk_parent_data){ |
| .hw = &cam_cc_xo_clk_src.clkr.hw, |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch cam_cc_cci_0_clk = { |
| .halt_reg = 0xc0f8, |
| .halt_check = BRANCH_HALT, |
| .clkr = { |
| .enable_reg = 0xc0f8, |
| .enable_mask = BIT(0), |
| .hw.init = &(struct clk_init_data){ |
| .name = "cam_cc_cci_0_clk", |
| .parent_data = &(const struct clk_parent_data){ |
| .hw = &cam_cc_cci_0_clk_src.clkr.hw, |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch cam_cc_cci_1_clk = { |
| .halt_reg = 0xc114, |
| .halt_check = BRANCH_HALT, |
| .clkr = { |
| .enable_reg = 0xc114, |
| .enable_mask = BIT(0), |
| .hw.init = &(struct clk_init_data){ |
| .name = "cam_cc_cci_1_clk", |
| .parent_data = &(const struct clk_parent_data){ |
| .hw = &cam_cc_cci_1_clk_src.clkr.hw, |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch cam_cc_core_ahb_clk = { |
| .halt_reg = 0xc1a0, |
| .halt_check = BRANCH_HALT_DELAY, |
| .clkr = { |
| .enable_reg = 0xc1a0, |
| .enable_mask = BIT(0), |
| .hw.init = &(struct clk_init_data){ |
| .name = "cam_cc_core_ahb_clk", |
| .parent_data = &(const struct clk_parent_data){ |
| .hw = &cam_cc_slow_ahb_clk_src.clkr.hw, |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch cam_cc_cpas_ahb_clk = { |
| .halt_reg = 0xc11c, |
| .halt_check = BRANCH_HALT, |
| .clkr = { |
| .enable_reg = 0xc11c, |
| .enable_mask = BIT(0), |
| .hw.init = &(struct clk_init_data){ |
| .name = "cam_cc_cpas_ahb_clk", |
| .parent_data = &(const struct clk_parent_data){ |
| .hw = &cam_cc_slow_ahb_clk_src.clkr.hw, |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch cam_cc_csi0phytimer_clk = { |
| .halt_reg = 0xe0c4, |
| .halt_check = BRANCH_HALT, |
| .clkr = { |
| .enable_reg = 0xe0c4, |
| .enable_mask = BIT(0), |
| .hw.init = &(struct clk_init_data){ |
| .name = "cam_cc_csi0phytimer_clk", |
| .parent_data = &(const struct clk_parent_data){ |
| .hw = &cam_cc_csi0phytimer_clk_src.clkr.hw, |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch cam_cc_csi1phytimer_clk = { |
| .halt_reg = 0xe0e8, |
| .halt_check = BRANCH_HALT, |
| .clkr = { |
| .enable_reg = 0xe0e8, |
| .enable_mask = BIT(0), |
| .hw.init = &(struct clk_init_data){ |
| .name = "cam_cc_csi1phytimer_clk", |
| .parent_data = &(const struct clk_parent_data){ |
| .hw = &cam_cc_csi1phytimer_clk_src.clkr.hw, |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch cam_cc_csi2phytimer_clk = { |
| .halt_reg = 0xe10c, |
| .halt_check = BRANCH_HALT, |
| .clkr = { |
| .enable_reg = 0xe10c, |
| .enable_mask = BIT(0), |
| .hw.init = &(struct clk_init_data){ |
| .name = "cam_cc_csi2phytimer_clk", |
| .parent_data = &(const struct clk_parent_data){ |
| .hw = &cam_cc_csi2phytimer_clk_src.clkr.hw, |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch cam_cc_csi3phytimer_clk = { |
| .halt_reg = 0xe134, |
| .halt_check = BRANCH_HALT, |
| .clkr = { |
| .enable_reg = 0xe134, |
| .enable_mask = BIT(0), |
| .hw.init = &(struct clk_init_data){ |
| .name = "cam_cc_csi3phytimer_clk", |
| .parent_data = &(const struct clk_parent_data){ |
| .hw = &cam_cc_csi3phytimer_clk_src.clkr.hw, |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch cam_cc_csi4phytimer_clk = { |
| .halt_reg = 0xe158, |
| .halt_check = BRANCH_HALT, |
| .clkr = { |
| .enable_reg = 0xe158, |
| .enable_mask = BIT(0), |
| .hw.init = &(struct clk_init_data){ |
| .name = "cam_cc_csi4phytimer_clk", |
| .parent_data = &(const struct clk_parent_data){ |
| .hw = &cam_cc_csi4phytimer_clk_src.clkr.hw, |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch cam_cc_csiphy0_clk = { |
| .halt_reg = 0xe0c8, |
| .halt_check = BRANCH_HALT, |
| .clkr = { |
| .enable_reg = 0xe0c8, |
| .enable_mask = BIT(0), |
| .hw.init = &(struct clk_init_data){ |
| .name = "cam_cc_csiphy0_clk", |
| .parent_data = &(const struct clk_parent_data){ |
| .hw = &cam_cc_cphy_rx_clk_src.clkr.hw, |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch cam_cc_csiphy1_clk = { |
| .halt_reg = 0xe0ec, |
| .halt_check = BRANCH_HALT, |
| .clkr = { |
| .enable_reg = 0xe0ec, |
| .enable_mask = BIT(0), |
| .hw.init = &(struct clk_init_data){ |
| .name = "cam_cc_csiphy1_clk", |
| .parent_data = &(const struct clk_parent_data){ |
| .hw = &cam_cc_cphy_rx_clk_src.clkr.hw, |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch cam_cc_csiphy2_clk = { |
| .halt_reg = 0xe110, |
| .halt_check = BRANCH_HALT, |
| .clkr = { |
| .enable_reg = 0xe110, |
| .enable_mask = BIT(0), |
| .hw.init = &(struct clk_init_data){ |
| .name = "cam_cc_csiphy2_clk", |
| .parent_data = &(const struct clk_parent_data){ |
| .hw = &cam_cc_cphy_rx_clk_src.clkr.hw, |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch cam_cc_csiphy3_clk = { |
| .halt_reg = 0xe138, |
| .halt_check = BRANCH_HALT, |
| .clkr = { |
| .enable_reg = 0xe138, |
| .enable_mask = BIT(0), |
| .hw.init = &(struct clk_init_data){ |
| .name = "cam_cc_csiphy3_clk", |
| .parent_data = &(const struct clk_parent_data){ |
| .hw = &cam_cc_cphy_rx_clk_src.clkr.hw, |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch cam_cc_csiphy4_clk = { |
| .halt_reg = 0xe15c, |
| .halt_check = BRANCH_HALT, |
| .clkr = { |
| .enable_reg = 0xe15c, |
| .enable_mask = BIT(0), |
| .hw.init = &(struct clk_init_data){ |
| .name = "cam_cc_csiphy4_clk", |
| .parent_data = &(const struct clk_parent_data){ |
| .hw = &cam_cc_cphy_rx_clk_src.clkr.hw, |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch cam_cc_gdsc_clk = { |
| .halt_reg = 0xc1bc, |
| .halt_check = BRANCH_HALT, |
| .clkr = { |
| .enable_reg = 0xc1bc, |
| .enable_mask = BIT(0), |
| .hw.init = &(struct clk_init_data){ |
| .name = "cam_cc_gdsc_clk", |
| .parent_data = &(const struct clk_parent_data){ |
| .hw = &cam_cc_xo_clk_src.clkr.hw, |
| }, |
| .num_parents = 1, |
| .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch cam_cc_icp_ahb_clk = { |
| .halt_reg = 0xc0d8, |
| .halt_check = BRANCH_HALT, |
| .clkr = { |
| .enable_reg = 0xc0d8, |
| .enable_mask = BIT(0), |
| .hw.init = &(struct clk_init_data){ |
| .name = "cam_cc_icp_ahb_clk", |
| .parent_data = &(const struct clk_parent_data){ |
| .hw = &cam_cc_slow_ahb_clk_src.clkr.hw, |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch cam_cc_icp_clk = { |
| .halt_reg = 0xc0d0, |
| .halt_check = BRANCH_HALT, |
| .clkr = { |
| .enable_reg = 0xc0d0, |
| .enable_mask = BIT(0), |
| .hw.init = &(struct clk_init_data){ |
| .name = "cam_cc_icp_clk", |
| .parent_data = &(const struct clk_parent_data){ |
| .hw = &cam_cc_icp_clk_src.clkr.hw, |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch cam_cc_ife_0_axi_clk = { |
| .halt_reg = 0xa080, |
| .halt_check = BRANCH_HALT, |
| .clkr = { |
| .enable_reg = 0xa080, |
| .enable_mask = BIT(0), |
| .hw.init = &(struct clk_init_data){ |
| .name = "cam_cc_ife_0_axi_clk", |
| .parent_data = &(const struct clk_parent_data){ |
| .hw = &cam_cc_camnoc_axi_clk_src.clkr.hw, |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch cam_cc_ife_0_clk = { |
| .halt_reg = 0xa028, |
| .halt_check = BRANCH_HALT, |
| .clkr = { |
| .enable_reg = 0xa028, |
| .enable_mask = BIT(0), |
| .hw.init = &(struct clk_init_data){ |
| .name = "cam_cc_ife_0_clk", |
| .parent_data = &(const struct clk_parent_data){ |
| .hw = &cam_cc_ife_0_clk_src.clkr.hw, |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch cam_cc_ife_0_cphy_rx_clk = { |
| .halt_reg = 0xa07c, |
| .halt_check = BRANCH_HALT, |
| .clkr = { |
| .enable_reg = 0xa07c, |
| .enable_mask = BIT(0), |
| .hw.init = &(struct clk_init_data){ |
| .name = "cam_cc_ife_0_cphy_rx_clk", |
| .parent_data = &(const struct clk_parent_data){ |
| .hw = &cam_cc_cphy_rx_clk_src.clkr.hw, |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch cam_cc_ife_0_csid_clk = { |
| .halt_reg = 0xa054, |
| .halt_check = BRANCH_HALT, |
| .clkr = { |
| .enable_reg = 0xa054, |
| .enable_mask = BIT(0), |
| .hw.init = &(struct clk_init_data){ |
| .name = "cam_cc_ife_0_csid_clk", |
| .parent_data = &(const struct clk_parent_data){ |
| .hw = &cam_cc_ife_0_csid_clk_src.clkr.hw, |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch cam_cc_ife_0_dsp_clk = { |
| .halt_reg = 0xa038, |
| .halt_check = BRANCH_HALT, |
| .clkr = { |
| .enable_reg = 0xa038, |
| .enable_mask = BIT(0), |
| .hw.init = &(struct clk_init_data){ |
| .name = "cam_cc_ife_0_dsp_clk", |
| .parent_data = &(const struct clk_parent_data){ |
| .hw = &cam_cc_ife_0_clk_src.clkr.hw, |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch cam_cc_ife_1_axi_clk = { |
| .halt_reg = 0xb068, |
| .halt_check = BRANCH_HALT, |
| .clkr = { |
| .enable_reg = 0xb068, |
| .enable_mask = BIT(0), |
| .hw.init = &(struct clk_init_data){ |
| .name = "cam_cc_ife_1_axi_clk", |
| .parent_data = &(const struct clk_parent_data){ |
| .hw = &cam_cc_camnoc_axi_clk_src.clkr.hw, |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch cam_cc_ife_1_clk = { |
| .halt_reg = 0xb028, |
| .halt_check = BRANCH_HALT, |
| .clkr = { |
| .enable_reg = 0xb028, |
| .enable_mask = BIT(0), |
| .hw.init = &(struct clk_init_data){ |
| .name = "cam_cc_ife_1_clk", |
| .parent_data = &(const struct clk_parent_data){ |
| .hw = &cam_cc_ife_1_clk_src.clkr.hw, |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch cam_cc_ife_1_cphy_rx_clk = { |
| .halt_reg = 0xb064, |
| .halt_check = BRANCH_HALT, |
| .clkr = { |
| .enable_reg = 0xb064, |
| .enable_mask = BIT(0), |
| .hw.init = &(struct clk_init_data){ |
| .name = "cam_cc_ife_1_cphy_rx_clk", |
| .parent_data = &(const struct clk_parent_data){ |
| .hw = &cam_cc_cphy_rx_clk_src.clkr.hw, |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch cam_cc_ife_1_csid_clk = { |
| .halt_reg = 0xb054, |
| .halt_check = BRANCH_HALT, |
| .clkr = { |
| .enable_reg = 0xb054, |
| .enable_mask = BIT(0), |
| .hw.init = &(struct clk_init_data){ |
| .name = "cam_cc_ife_1_csid_clk", |
| .parent_data = &(const struct clk_parent_data){ |
| .hw = &cam_cc_ife_1_csid_clk_src.clkr.hw, |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch cam_cc_ife_1_dsp_clk = { |
| .halt_reg = 0xb038, |
| .halt_check = BRANCH_HALT, |
| .clkr = { |
| .enable_reg = 0xb038, |
| .enable_mask = BIT(0), |
| .hw.init = &(struct clk_init_data){ |
| .name = "cam_cc_ife_1_dsp_clk", |
| .parent_data = &(const struct clk_parent_data){ |
| .hw = &cam_cc_ife_1_clk_src.clkr.hw, |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch cam_cc_ife_2_axi_clk = { |
| .halt_reg = 0xb0d4, |
| .halt_check = BRANCH_HALT, |
| .clkr = { |
| .enable_reg = 0xb0d4, |
| .enable_mask = BIT(0), |
| .hw.init = &(struct clk_init_data){ |
| .name = "cam_cc_ife_2_axi_clk", |
| .parent_data = &(const struct clk_parent_data){ |
| .hw = &cam_cc_camnoc_axi_clk_src.clkr.hw, |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch cam_cc_ife_2_clk = { |
| .halt_reg = 0xb094, |
| .halt_check = BRANCH_HALT, |
| .clkr = { |
| .enable_reg = 0xb094, |
| .enable_mask = BIT(0), |
| .hw.init = &(struct clk_init_data){ |
| .name = "cam_cc_ife_2_clk", |
| .parent_data = &(const struct clk_parent_data){ |
| .hw = &cam_cc_ife_2_clk_src.clkr.hw, |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch cam_cc_ife_2_cphy_rx_clk = { |
| .halt_reg = 0xb0d0, |
| .halt_check = BRANCH_HALT, |
| .clkr = { |
| .enable_reg = 0xb0d0, |
| .enable_mask = BIT(0), |
| .hw.init = &(struct clk_init_data){ |
| .name = "cam_cc_ife_2_cphy_rx_clk", |
| .parent_data = &(const struct clk_parent_data){ |
| .hw = &cam_cc_cphy_rx_clk_src.clkr.hw, |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch cam_cc_ife_2_csid_clk = { |
| .halt_reg = 0xb0c0, |
| .halt_check = BRANCH_HALT, |
| .clkr = { |
| .enable_reg = 0xb0c0, |
| .enable_mask = BIT(0), |
| .hw.init = &(struct clk_init_data){ |
| .name = "cam_cc_ife_2_csid_clk", |
| .parent_data = &(const struct clk_parent_data){ |
| .hw = &cam_cc_ife_2_csid_clk_src.clkr.hw, |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch cam_cc_ife_2_dsp_clk = { |
| .halt_reg = 0xb0a4, |
| .halt_check = BRANCH_HALT, |
| .clkr = { |
| .enable_reg = 0xb0a4, |
| .enable_mask = BIT(0), |
| .hw.init = &(struct clk_init_data){ |
| .name = "cam_cc_ife_2_dsp_clk", |
| .parent_data = &(const struct clk_parent_data){ |
| .hw = &cam_cc_ife_2_clk_src.clkr.hw, |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch cam_cc_ife_lite_0_clk = { |
| .halt_reg = 0xc01c, |
| .halt_check = BRANCH_HALT, |
| .clkr = { |
| .enable_reg = 0xc01c, |
| .enable_mask = BIT(0), |
| .hw.init = &(struct clk_init_data){ |
| .name = "cam_cc_ife_lite_0_clk", |
| .parent_data = &(const struct clk_parent_data){ |
| .hw = &cam_cc_ife_lite_0_clk_src.clkr.hw, |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch cam_cc_ife_lite_0_cphy_rx_clk = { |
| .halt_reg = 0xc040, |
| .halt_check = BRANCH_HALT, |
| .clkr = { |
| .enable_reg = 0xc040, |
| .enable_mask = BIT(0), |
| .hw.init = &(struct clk_init_data){ |
| .name = "cam_cc_ife_lite_0_cphy_rx_clk", |
| .parent_data = &(const struct clk_parent_data){ |
| .hw = &cam_cc_cphy_rx_clk_src.clkr.hw, |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch cam_cc_ife_lite_0_csid_clk = { |
| .halt_reg = 0xc038, |
| .halt_check = BRANCH_HALT, |
| .clkr = { |
| .enable_reg = 0xc038, |
| .enable_mask = BIT(0), |
| .hw.init = &(struct clk_init_data){ |
| .name = "cam_cc_ife_lite_0_csid_clk", |
| .parent_data = &(const struct clk_parent_data){ |
| .hw = &cam_cc_ife_lite_0_csid_clk_src.clkr.hw, |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch cam_cc_ife_lite_1_clk = { |
| .halt_reg = 0xc060, |
| .halt_check = BRANCH_HALT, |
| .clkr = { |
| .enable_reg = 0xc060, |
| .enable_mask = BIT(0), |
| .hw.init = &(struct clk_init_data){ |
| .name = "cam_cc_ife_lite_1_clk", |
| .parent_data = &(const struct clk_parent_data){ |
| .hw = &cam_cc_ife_lite_1_clk_src.clkr.hw, |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch cam_cc_ife_lite_1_cphy_rx_clk = { |
| .halt_reg = 0xc084, |
| .halt_check = BRANCH_HALT, |
| .clkr = { |
| .enable_reg = 0xc084, |
| .enable_mask = BIT(0), |
| .hw.init = &(struct clk_init_data){ |
| .name = "cam_cc_ife_lite_1_cphy_rx_clk", |
| .parent_data = &(const struct clk_parent_data){ |
| .hw = &cam_cc_cphy_rx_clk_src.clkr.hw, |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch cam_cc_ife_lite_1_csid_clk = { |
| .halt_reg = 0xc07c, |
| .halt_check = BRANCH_HALT, |
| .clkr = { |
| .enable_reg = 0xc07c, |
| .enable_mask = BIT(0), |
| .hw.init = &(struct clk_init_data){ |
| .name = "cam_cc_ife_lite_1_csid_clk", |
| .parent_data = &(const struct clk_parent_data){ |
| .hw = &cam_cc_ife_lite_1_csid_clk_src.clkr.hw, |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch cam_cc_ipe_0_ahb_clk = { |
| .halt_reg = 0x8040, |
| .halt_check = BRANCH_HALT, |
| .clkr = { |
| .enable_reg = 0x8040, |
| .enable_mask = BIT(0), |
| .hw.init = &(struct clk_init_data){ |
| .name = "cam_cc_ipe_0_ahb_clk", |
| .parent_data = &(const struct clk_parent_data){ |
| .hw = &cam_cc_slow_ahb_clk_src.clkr.hw, |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch cam_cc_ipe_0_areg_clk = { |
| .halt_reg = 0x803c, |
| .halt_check = BRANCH_HALT, |
| .clkr = { |
| .enable_reg = 0x803c, |
| .enable_mask = BIT(0), |
| .hw.init = &(struct clk_init_data){ |
| .name = "cam_cc_ipe_0_areg_clk", |
| .parent_data = &(const struct clk_parent_data){ |
| .hw = &cam_cc_fast_ahb_clk_src.clkr.hw, |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch cam_cc_ipe_0_axi_clk = { |
| .halt_reg = 0x8038, |
| .halt_check = BRANCH_HALT, |
| .clkr = { |
| .enable_reg = 0x8038, |
| .enable_mask = BIT(0), |
| .hw.init = &(struct clk_init_data){ |
| .name = "cam_cc_ipe_0_axi_clk", |
| .parent_data = &(const struct clk_parent_data){ |
| .hw = &cam_cc_camnoc_axi_clk_src.clkr.hw, |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch cam_cc_ipe_0_clk = { |
| .halt_reg = 0x8028, |
| .halt_check = BRANCH_HALT, |
| .clkr = { |
| .enable_reg = 0x8028, |
| .enable_mask = BIT(0), |
| .hw.init = &(struct clk_init_data){ |
| .name = "cam_cc_ipe_0_clk", |
| .parent_data = &(const struct clk_parent_data){ |
| .hw = &cam_cc_ipe_0_clk_src.clkr.hw, |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch cam_cc_jpeg_clk = { |
| .halt_reg = 0xc0a4, |
| .halt_check = BRANCH_HALT, |
| .clkr = { |
| .enable_reg = 0xc0a4, |
| .enable_mask = BIT(0), |
| .hw.init = &(struct clk_init_data){ |
| .name = "cam_cc_jpeg_clk", |
| .parent_data = &(const struct clk_parent_data){ |
| .hw = &cam_cc_jpeg_clk_src.clkr.hw, |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch cam_cc_lrme_clk = { |
| .halt_reg = 0xc168, |
| .halt_check = BRANCH_HALT, |
| .clkr = { |
| .enable_reg = 0xc168, |
| .enable_mask = BIT(0), |
| .hw.init = &(struct clk_init_data){ |
| .name = "cam_cc_lrme_clk", |
| .parent_data = &(const struct clk_parent_data){ |
| .hw = &cam_cc_lrme_clk_src.clkr.hw, |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch cam_cc_mclk0_clk = { |
| .halt_reg = 0xe018, |
| .halt_check = BRANCH_HALT, |
| .clkr = { |
| .enable_reg = 0xe018, |
| .enable_mask = BIT(0), |
| .hw.init = &(struct clk_init_data){ |
| .name = "cam_cc_mclk0_clk", |
| .parent_data = &(const struct clk_parent_data){ |
| .hw = &cam_cc_mclk0_clk_src.clkr.hw, |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch cam_cc_mclk1_clk = { |
| .halt_reg = 0xe034, |
| .halt_check = BRANCH_HALT, |
| .clkr = { |
| .enable_reg = 0xe034, |
| .enable_mask = BIT(0), |
| .hw.init = &(struct clk_init_data){ |
| .name = "cam_cc_mclk1_clk", |
| .parent_data = &(const struct clk_parent_data){ |
| .hw = &cam_cc_mclk1_clk_src.clkr.hw, |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch cam_cc_mclk2_clk = { |
| .halt_reg = 0xe050, |
| .halt_check = BRANCH_HALT, |
| .clkr = { |
| .enable_reg = 0xe050, |
| .enable_mask = BIT(0), |
| .hw.init = &(struct clk_init_data){ |
| .name = "cam_cc_mclk2_clk", |
| .parent_data = &(const struct clk_parent_data){ |
| .hw = &cam_cc_mclk2_clk_src.clkr.hw, |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch cam_cc_mclk3_clk = { |
| .halt_reg = 0xe06c, |
| .halt_check = BRANCH_HALT, |
| .clkr = { |
| .enable_reg = 0xe06c, |
| .enable_mask = BIT(0), |
| .hw.init = &(struct clk_init_data){ |
| .name = "cam_cc_mclk3_clk", |
| .parent_data = &(const struct clk_parent_data){ |
| .hw = &cam_cc_mclk3_clk_src.clkr.hw, |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch cam_cc_mclk4_clk = { |
| .halt_reg = 0xe088, |
| .halt_check = BRANCH_HALT, |
| .clkr = { |
| .enable_reg = 0xe088, |
| .enable_mask = BIT(0), |
| .hw.init = &(struct clk_init_data){ |
| .name = "cam_cc_mclk4_clk", |
| .parent_data = &(const struct clk_parent_data){ |
| .hw = &cam_cc_mclk4_clk_src.clkr.hw, |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch cam_cc_mclk5_clk = { |
| .halt_reg = 0xe0a4, |
| .halt_check = BRANCH_HALT, |
| .clkr = { |
| .enable_reg = 0xe0a4, |
| .enable_mask = BIT(0), |
| .hw.init = &(struct clk_init_data){ |
| .name = "cam_cc_mclk5_clk", |
| .parent_data = &(const struct clk_parent_data){ |
| .hw = &cam_cc_mclk5_clk_src.clkr.hw, |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch cam_cc_sleep_clk = { |
| .halt_reg = 0xc1d8, |
| .halt_check = BRANCH_HALT, |
| .clkr = { |
| .enable_reg = 0xc1d8, |
| .enable_mask = BIT(0), |
| .hw.init = &(struct clk_init_data){ |
| .name = "cam_cc_sleep_clk", |
| .parent_data = &(const struct clk_parent_data){ |
| .hw = &cam_cc_sleep_clk_src.clkr.hw, |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct gdsc cam_cc_titan_top_gdsc = { |
| .gdscr = 0xc194, |
| .pd = { |
| .name = "cam_cc_titan_top_gdsc", |
| }, |
| .pwrsts = PWRSTS_OFF_ON, |
| .flags = RETAIN_FF_ENABLE, |
| }; |
| |
| static struct gdsc cam_cc_bps_gdsc = { |
| .gdscr = 0x7004, |
| .pd = { |
| .name = "cam_cc_bps_gdsc", |
| }, |
| .pwrsts = PWRSTS_OFF_ON, |
| .flags = HW_CTRL | RETAIN_FF_ENABLE, |
| }; |
| |
| static struct gdsc cam_cc_ife_0_gdsc = { |
| .gdscr = 0xa004, |
| .pd = { |
| .name = "cam_cc_ife_0_gdsc", |
| }, |
| .pwrsts = PWRSTS_OFF_ON, |
| .flags = RETAIN_FF_ENABLE, |
| }; |
| |
| static struct gdsc cam_cc_ife_1_gdsc = { |
| .gdscr = 0xb004, |
| .pd = { |
| .name = "cam_cc_ife_1_gdsc", |
| }, |
| .pwrsts = PWRSTS_OFF_ON, |
| .flags = RETAIN_FF_ENABLE, |
| }; |
| |
| static struct gdsc cam_cc_ife_2_gdsc = { |
| .gdscr = 0xb070, |
| .pd = { |
| .name = "cam_cc_ife_2_gdsc", |
| }, |
| .pwrsts = PWRSTS_OFF_ON, |
| .flags = RETAIN_FF_ENABLE, |
| }; |
| |
| static struct gdsc cam_cc_ipe_0_gdsc = { |
| .gdscr = 0x8004, |
| .pd = { |
| .name = "cam_cc_ipe_0_gdsc", |
| }, |
| .pwrsts = PWRSTS_OFF_ON, |
| .flags = HW_CTRL | RETAIN_FF_ENABLE, |
| }; |
| |
| static struct clk_regmap *cam_cc_sc7280_clocks[] = { |
| [CAM_CC_BPS_AHB_CLK] = &cam_cc_bps_ahb_clk.clkr, |
| [CAM_CC_BPS_AREG_CLK] = &cam_cc_bps_areg_clk.clkr, |
| [CAM_CC_BPS_AXI_CLK] = &cam_cc_bps_axi_clk.clkr, |
| [CAM_CC_BPS_CLK] = &cam_cc_bps_clk.clkr, |
| [CAM_CC_BPS_CLK_SRC] = &cam_cc_bps_clk_src.clkr, |
| [CAM_CC_CAMNOC_AXI_CLK] = &cam_cc_camnoc_axi_clk.clkr, |
| [CAM_CC_CAMNOC_AXI_CLK_SRC] = &cam_cc_camnoc_axi_clk_src.clkr, |
| [CAM_CC_CAMNOC_DCD_XO_CLK] = &cam_cc_camnoc_dcd_xo_clk.clkr, |
| [CAM_CC_CCI_0_CLK] = &cam_cc_cci_0_clk.clkr, |
| [CAM_CC_CCI_0_CLK_SRC] = &cam_cc_cci_0_clk_src.clkr, |
| [CAM_CC_CCI_1_CLK] = &cam_cc_cci_1_clk.clkr, |
| [CAM_CC_CCI_1_CLK_SRC] = &cam_cc_cci_1_clk_src.clkr, |
| [CAM_CC_CORE_AHB_CLK] = &cam_cc_core_ahb_clk.clkr, |
| [CAM_CC_CPAS_AHB_CLK] = &cam_cc_cpas_ahb_clk.clkr, |
| [CAM_CC_CPHY_RX_CLK_SRC] = &cam_cc_cphy_rx_clk_src.clkr, |
| [CAM_CC_CSI0PHYTIMER_CLK] = &cam_cc_csi0phytimer_clk.clkr, |
| [CAM_CC_CSI0PHYTIMER_CLK_SRC] = &cam_cc_csi0phytimer_clk_src.clkr, |
| [CAM_CC_CSI1PHYTIMER_CLK] = &cam_cc_csi1phytimer_clk.clkr, |
| [CAM_CC_CSI1PHYTIMER_CLK_SRC] = &cam_cc_csi1phytimer_clk_src.clkr, |
| [CAM_CC_CSI2PHYTIMER_CLK] = &cam_cc_csi2phytimer_clk.clkr, |
| [CAM_CC_CSI2PHYTIMER_CLK_SRC] = &cam_cc_csi2phytimer_clk_src.clkr, |
| [CAM_CC_CSI3PHYTIMER_CLK] = &cam_cc_csi3phytimer_clk.clkr, |
| [CAM_CC_CSI3PHYTIMER_CLK_SRC] = &cam_cc_csi3phytimer_clk_src.clkr, |
| [CAM_CC_CSI4PHYTIMER_CLK] = &cam_cc_csi4phytimer_clk.clkr, |
| [CAM_CC_CSI4PHYTIMER_CLK_SRC] = &cam_cc_csi4phytimer_clk_src.clkr, |
| [CAM_CC_CSIPHY0_CLK] = &cam_cc_csiphy0_clk.clkr, |
| [CAM_CC_CSIPHY1_CLK] = &cam_cc_csiphy1_clk.clkr, |
| [CAM_CC_CSIPHY2_CLK] = &cam_cc_csiphy2_clk.clkr, |
| [CAM_CC_CSIPHY3_CLK] = &cam_cc_csiphy3_clk.clkr, |
| [CAM_CC_CSIPHY4_CLK] = &cam_cc_csiphy4_clk.clkr, |
| [CAM_CC_FAST_AHB_CLK_SRC] = &cam_cc_fast_ahb_clk_src.clkr, |
| [CAM_CC_GDSC_CLK] = &cam_cc_gdsc_clk.clkr, |
| [CAM_CC_ICP_AHB_CLK] = &cam_cc_icp_ahb_clk.clkr, |
| [CAM_CC_ICP_CLK] = &cam_cc_icp_clk.clkr, |
| [CAM_CC_ICP_CLK_SRC] = &cam_cc_icp_clk_src.clkr, |
| [CAM_CC_IFE_0_AXI_CLK] = &cam_cc_ife_0_axi_clk.clkr, |
| [CAM_CC_IFE_0_CLK] = &cam_cc_ife_0_clk.clkr, |
| [CAM_CC_IFE_0_CLK_SRC] = &cam_cc_ife_0_clk_src.clkr, |
| [CAM_CC_IFE_0_CPHY_RX_CLK] = &cam_cc_ife_0_cphy_rx_clk.clkr, |
| [CAM_CC_IFE_0_CSID_CLK] = &cam_cc_ife_0_csid_clk.clkr, |
| [CAM_CC_IFE_0_CSID_CLK_SRC] = &cam_cc_ife_0_csid_clk_src.clkr, |
| [CAM_CC_IFE_0_DSP_CLK] = &cam_cc_ife_0_dsp_clk.clkr, |
| [CAM_CC_IFE_1_AXI_CLK] = &cam_cc_ife_1_axi_clk.clkr, |
| [CAM_CC_IFE_1_CLK] = &cam_cc_ife_1_clk.clkr, |
| [CAM_CC_IFE_1_CLK_SRC] = &cam_cc_ife_1_clk_src.clkr, |
| [CAM_CC_IFE_1_CPHY_RX_CLK] = &cam_cc_ife_1_cphy_rx_clk.clkr, |
| [CAM_CC_IFE_1_CSID_CLK] = &cam_cc_ife_1_csid_clk.clkr, |
| [CAM_CC_IFE_1_CSID_CLK_SRC] = &cam_cc_ife_1_csid_clk_src.clkr, |
| [CAM_CC_IFE_1_DSP_CLK] = &cam_cc_ife_1_dsp_clk.clkr, |
| [CAM_CC_IFE_2_AXI_CLK] = &cam_cc_ife_2_axi_clk.clkr, |
| [CAM_CC_IFE_2_CLK] = &cam_cc_ife_2_clk.clkr, |
| [CAM_CC_IFE_2_CLK_SRC] = &cam_cc_ife_2_clk_src.clkr, |
| [CAM_CC_IFE_2_CPHY_RX_CLK] = &cam_cc_ife_2_cphy_rx_clk.clkr, |
| [CAM_CC_IFE_2_CSID_CLK] = &cam_cc_ife_2_csid_clk.clkr, |
| [CAM_CC_IFE_2_CSID_CLK_SRC] = &cam_cc_ife_2_csid_clk_src.clkr, |
| [CAM_CC_IFE_2_DSP_CLK] = &cam_cc_ife_2_dsp_clk.clkr, |
| [CAM_CC_IFE_LITE_0_CLK] = &cam_cc_ife_lite_0_clk.clkr, |
| [CAM_CC_IFE_LITE_0_CLK_SRC] = &cam_cc_ife_lite_0_clk_src.clkr, |
| [CAM_CC_IFE_LITE_0_CPHY_RX_CLK] = &cam_cc_ife_lite_0_cphy_rx_clk.clkr, |
| [CAM_CC_IFE_LITE_0_CSID_CLK] = &cam_cc_ife_lite_0_csid_clk.clkr, |
| [CAM_CC_IFE_LITE_0_CSID_CLK_SRC] = &cam_cc_ife_lite_0_csid_clk_src.clkr, |
| [CAM_CC_IFE_LITE_1_CLK] = &cam_cc_ife_lite_1_clk.clkr, |
| [CAM_CC_IFE_LITE_1_CLK_SRC] = &cam_cc_ife_lite_1_clk_src.clkr, |
| [CAM_CC_IFE_LITE_1_CPHY_RX_CLK] = &cam_cc_ife_lite_1_cphy_rx_clk.clkr, |
| [CAM_CC_IFE_LITE_1_CSID_CLK] = &cam_cc_ife_lite_1_csid_clk.clkr, |
| [CAM_CC_IFE_LITE_1_CSID_CLK_SRC] = &cam_cc_ife_lite_1_csid_clk_src.clkr, |
| [CAM_CC_IPE_0_AHB_CLK] = &cam_cc_ipe_0_ahb_clk.clkr, |
| [CAM_CC_IPE_0_AREG_CLK] = &cam_cc_ipe_0_areg_clk.clkr, |
| [CAM_CC_IPE_0_AXI_CLK] = &cam_cc_ipe_0_axi_clk.clkr, |
| [CAM_CC_IPE_0_CLK] = &cam_cc_ipe_0_clk.clkr, |
| [CAM_CC_IPE_0_CLK_SRC] = &cam_cc_ipe_0_clk_src.clkr, |
| [CAM_CC_JPEG_CLK] = &cam_cc_jpeg_clk.clkr, |
| [CAM_CC_JPEG_CLK_SRC] = &cam_cc_jpeg_clk_src.clkr, |
| [CAM_CC_LRME_CLK] = &cam_cc_lrme_clk.clkr, |
| [CAM_CC_LRME_CLK_SRC] = &cam_cc_lrme_clk_src.clkr, |
| [CAM_CC_MCLK0_CLK] = &cam_cc_mclk0_clk.clkr, |
| [CAM_CC_MCLK0_CLK_SRC] = &cam_cc_mclk0_clk_src.clkr, |
| [CAM_CC_MCLK1_CLK] = &cam_cc_mclk1_clk.clkr, |
| [CAM_CC_MCLK1_CLK_SRC] = &cam_cc_mclk1_clk_src.clkr, |
| [CAM_CC_MCLK2_CLK] = &cam_cc_mclk2_clk.clkr, |
| [CAM_CC_MCLK2_CLK_SRC] = &cam_cc_mclk2_clk_src.clkr, |
| [CAM_CC_MCLK3_CLK] = &cam_cc_mclk3_clk.clkr, |
| [CAM_CC_MCLK3_CLK_SRC] = &cam_cc_mclk3_clk_src.clkr, |
| [CAM_CC_MCLK4_CLK] = &cam_cc_mclk4_clk.clkr, |
| [CAM_CC_MCLK4_CLK_SRC] = &cam_cc_mclk4_clk_src.clkr, |
| [CAM_CC_MCLK5_CLK] = &cam_cc_mclk5_clk.clkr, |
| [CAM_CC_MCLK5_CLK_SRC] = &cam_cc_mclk5_clk_src.clkr, |
| [CAM_CC_PLL0] = &cam_cc_pll0.clkr, |
| [CAM_CC_PLL0_OUT_EVEN] = &cam_cc_pll0_out_even.clkr, |
| [CAM_CC_PLL0_OUT_ODD] = &cam_cc_pll0_out_odd.clkr, |
| [CAM_CC_PLL1] = &cam_cc_pll1.clkr, |
| [CAM_CC_PLL1_OUT_EVEN] = &cam_cc_pll1_out_even.clkr, |
| [CAM_CC_PLL2] = &cam_cc_pll2.clkr, |
| [CAM_CC_PLL2_OUT_AUX] = &cam_cc_pll2_out_aux.clkr, |
| [CAM_CC_PLL2_OUT_AUX2] = &cam_cc_pll2_out_aux2.clkr, |
| [CAM_CC_PLL3] = &cam_cc_pll3.clkr, |
| [CAM_CC_PLL3_OUT_EVEN] = &cam_cc_pll3_out_even.clkr, |
| [CAM_CC_PLL4] = &cam_cc_pll4.clkr, |
| [CAM_CC_PLL4_OUT_EVEN] = &cam_cc_pll4_out_even.clkr, |
| [CAM_CC_PLL5] = &cam_cc_pll5.clkr, |
| [CAM_CC_PLL5_OUT_EVEN] = &cam_cc_pll5_out_even.clkr, |
| [CAM_CC_PLL6] = &cam_cc_pll6.clkr, |
| [CAM_CC_PLL6_OUT_EVEN] = &cam_cc_pll6_out_even.clkr, |
| [CAM_CC_PLL6_OUT_ODD] = &cam_cc_pll6_out_odd.clkr, |
| [CAM_CC_SLEEP_CLK] = &cam_cc_sleep_clk.clkr, |
| [CAM_CC_SLEEP_CLK_SRC] = &cam_cc_sleep_clk_src.clkr, |
| [CAM_CC_SLOW_AHB_CLK_SRC] = &cam_cc_slow_ahb_clk_src.clkr, |
| [CAM_CC_XO_CLK_SRC] = &cam_cc_xo_clk_src.clkr, |
| }; |
| |
| static struct gdsc *cam_cc_sc7280_gdscs[] = { |
| [CAM_CC_TITAN_TOP_GDSC] = &cam_cc_titan_top_gdsc, |
| [CAM_CC_BPS_GDSC] = &cam_cc_bps_gdsc, |
| [CAM_CC_IFE_0_GDSC] = &cam_cc_ife_0_gdsc, |
| [CAM_CC_IFE_1_GDSC] = &cam_cc_ife_1_gdsc, |
| [CAM_CC_IFE_2_GDSC] = &cam_cc_ife_2_gdsc, |
| [CAM_CC_IPE_0_GDSC] = &cam_cc_ipe_0_gdsc, |
| }; |
| |
| static const struct regmap_config cam_cc_sc7280_regmap_config = { |
| .reg_bits = 32, |
| .reg_stride = 4, |
| .val_bits = 32, |
| .max_register = 0xf00c, |
| .fast_io = true, |
| }; |
| |
| static const struct qcom_cc_desc cam_cc_sc7280_desc = { |
| .config = &cam_cc_sc7280_regmap_config, |
| .clks = cam_cc_sc7280_clocks, |
| .num_clks = ARRAY_SIZE(cam_cc_sc7280_clocks), |
| .gdscs = cam_cc_sc7280_gdscs, |
| .num_gdscs = ARRAY_SIZE(cam_cc_sc7280_gdscs), |
| }; |
| |
| static const struct of_device_id cam_cc_sc7280_match_table[] = { |
| { .compatible = "qcom,sc7280-camcc" }, |
| { } |
| }; |
| MODULE_DEVICE_TABLE(of, cam_cc_sc7280_match_table); |
| |
| static int cam_cc_sc7280_probe(struct platform_device *pdev) |
| { |
| struct regmap *regmap; |
| |
| regmap = qcom_cc_map(pdev, &cam_cc_sc7280_desc); |
| if (IS_ERR(regmap)) |
| return PTR_ERR(regmap); |
| |
| clk_lucid_pll_configure(&cam_cc_pll0, regmap, &cam_cc_pll0_config); |
| clk_lucid_pll_configure(&cam_cc_pll1, regmap, &cam_cc_pll1_config); |
| clk_zonda_pll_configure(&cam_cc_pll2, regmap, &cam_cc_pll2_config); |
| clk_lucid_pll_configure(&cam_cc_pll3, regmap, &cam_cc_pll3_config); |
| clk_lucid_pll_configure(&cam_cc_pll4, regmap, &cam_cc_pll4_config); |
| clk_lucid_pll_configure(&cam_cc_pll5, regmap, &cam_cc_pll5_config); |
| clk_lucid_pll_configure(&cam_cc_pll6, regmap, &cam_cc_pll6_config); |
| |
| return qcom_cc_really_probe(pdev, &cam_cc_sc7280_desc, regmap); |
| } |
| |
| static struct platform_driver cam_cc_sc7280_driver = { |
| .probe = cam_cc_sc7280_probe, |
| .driver = { |
| .name = "cam_cc-sc7280", |
| .of_match_table = cam_cc_sc7280_match_table, |
| }, |
| }; |
| |
| static int __init cam_cc_sc7280_init(void) |
| { |
| return platform_driver_register(&cam_cc_sc7280_driver); |
| } |
| subsys_initcall(cam_cc_sc7280_init); |
| |
| static void __exit cam_cc_sc7280_exit(void) |
| { |
| platform_driver_unregister(&cam_cc_sc7280_driver); |
| } |
| module_exit(cam_cc_sc7280_exit); |
| |
| MODULE_DESCRIPTION("QTI CAM_CC SC7280 Driver"); |
| MODULE_LICENSE("GPL v2"); |
