Documentation/devicetree/bindings/pci/fsl,layerscape-pcie-ep.yaml

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/fsl,layerscape-pcie-ep.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Freescale Layerscape PCIe Endpoint(EP) controller

maintainers:
  - Frank Li <Frank.Li@nxp.com>

description:
  This PCIe EP controller is based on the Synopsys DesignWare PCIe IP.

  This controller derives its clocks from the Reset Configuration Word (RCW)
  which is used to describe the PLL settings at the time of chip-reset.

  Also as per the available Reference Manuals, there is no specific 'version'
  register available in the Freescale PCIe controller register set,
  which can allow determining the underlying DesignWare PCIe controller version
  information.

properties:
  compatible:
    enum:
      - fsl,ls2088a-pcie-ep
      - fsl,ls1088a-pcie-ep
      - fsl,ls1046a-pcie-ep
      - fsl,ls1028a-pcie-ep
      - fsl,lx2160ar2-pcie-ep

  reg:
    maxItems: 2

  reg-names:
    items:
      - const: regs
      - const: addr_space

  fsl,pcie-scfg:
    $ref: /schemas/types.yaml#/definitions/phandle
    description: A phandle to the SCFG device node. The second entry is the
      physical PCIe controller index starting from '0'. This is used to get
      SCFG PEXN registers.

  big-endian:
    $ref: /schemas/types.yaml#/definitions/flag
    description: If the PEX_LUT and PF register block is in big-endian, specify
      this property.

  dma-coherent: true

  interrupts:
    minItems: 1
    maxItems: 2

  interrupt-names:
    minItems: 1
    maxItems: 2

required:
  - compatible
  - reg
  - reg-names

allOf:
  - if:
      properties:
        compatible:
          enum:
            - fsl,ls1028a-pcie-ep
            - fsl,ls1046a-pcie-ep
            - fsl,ls1088a-pcie-ep
    then:
      properties:
        interrupt-names:
          items:
            - const: pme

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    soc {
      #address-cells = <2>;
      #size-cells = <2>;

      pcie_ep1: pcie-ep@3400000 {
        compatible = "fsl,ls1028a-pcie-ep";
        reg = <0x00 0x03400000 0x0 0x00100000
              0x80 0x00000000 0x8 0x00000000>;
        reg-names = "regs", "addr_space";
        interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */
        interrupt-names = "pme";
        num-ib-windows = <6>;
        num-ob-windows = <8>;
        status = "disabled";
      };
    };
...