| // SPDX-License-Identifier: GPL-2.0 |
| /* |
| * Copyright © 2017-2020 MediaTek Inc. |
| * Author: Sean Wang <sean.wang@mediatek.com> |
| * Ryder Lee <ryder.lee@mediatek.com> |
| * |
| */ |
| |
| #include "mt7623.dtsi" |
| #include <dt-bindings/memory/mt2701-larb-port.h> |
| |
| / { |
| aliases { |
| rdma0 = &rdma0; |
| rdma1 = &rdma1; |
| }; |
| |
| g3dsys: syscon@13000000 { |
| compatible = "mediatek,mt7623-g3dsys", |
| "mediatek,mt2701-g3dsys", |
| "syscon"; |
| reg = <0 0x13000000 0 0x200>; |
| #clock-cells = <1>; |
| #reset-cells = <1>; |
| }; |
| |
| mali: gpu@13040000 { |
| compatible = "mediatek,mt7623-mali", "arm,mali-450"; |
| reg = <0 0x13040000 0 0x30000>; |
| interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_LOW>, |
| <GIC_SPI 171 IRQ_TYPE_LEVEL_LOW>, |
| <GIC_SPI 172 IRQ_TYPE_LEVEL_LOW>, |
| <GIC_SPI 173 IRQ_TYPE_LEVEL_LOW>, |
| <GIC_SPI 174 IRQ_TYPE_LEVEL_LOW>, |
| <GIC_SPI 175 IRQ_TYPE_LEVEL_LOW>, |
| <GIC_SPI 176 IRQ_TYPE_LEVEL_LOW>, |
| <GIC_SPI 177 IRQ_TYPE_LEVEL_LOW>, |
| <GIC_SPI 178 IRQ_TYPE_LEVEL_LOW>, |
| <GIC_SPI 179 IRQ_TYPE_LEVEL_LOW>, |
| <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>; |
| interrupt-names = "gp", "gpmmu", "pp0", "ppmmu0", "pp1", |
| "ppmmu1", "pp2", "ppmmu2", "pp3", "ppmmu3", |
| "pp"; |
| clocks = <&topckgen CLK_TOP_MMPLL>, |
| <&g3dsys CLK_G3DSYS_CORE>; |
| clock-names = "bus", "core"; |
| power-domains = <&scpsys MT2701_POWER_DOMAIN_MFG>; |
| resets = <&g3dsys MT2701_G3DSYS_CORE_RST>; |
| }; |
| |
| mmsys: syscon@14000000 { |
| compatible = "mediatek,mt7623-mmsys", |
| "mediatek,mt2701-mmsys", |
| "syscon"; |
| reg = <0 0x14000000 0 0x1000>; |
| #clock-cells = <1>; |
| }; |
| |
| larb0: larb@14010000 { |
| compatible = "mediatek,mt7623-smi-larb", |
| "mediatek,mt2701-smi-larb"; |
| reg = <0 0x14010000 0 0x1000>; |
| mediatek,smi = <&smi_common>; |
| mediatek,larb-id = <0>; |
| clocks = <&mmsys CLK_MM_SMI_LARB0>, |
| <&mmsys CLK_MM_SMI_LARB0>; |
| clock-names = "apb", "smi"; |
| power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>; |
| }; |
| |
| larb1: larb@16010000 { |
| compatible = "mediatek,mt7623-smi-larb", |
| "mediatek,mt2701-smi-larb"; |
| reg = <0 0x16010000 0 0x1000>; |
| mediatek,smi = <&smi_common>; |
| mediatek,larb-id = <1>; |
| clocks = <&vdecsys CLK_VDEC_CKGEN>, |
| <&vdecsys CLK_VDEC_LARB>; |
| clock-names = "apb", "smi"; |
| power-domains = <&scpsys MT2701_POWER_DOMAIN_VDEC>; |
| }; |
| |
| larb2: larb@15001000 { |
| compatible = "mediatek,mt7623-smi-larb", |
| "mediatek,mt2701-smi-larb"; |
| reg = <0 0x15001000 0 0x1000>; |
| mediatek,smi = <&smi_common>; |
| mediatek,larb-id = <2>; |
| clocks = <&imgsys CLK_IMG_SMI_COMM>, |
| <&imgsys CLK_IMG_SMI_COMM>; |
| clock-names = "apb", "smi"; |
| power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>; |
| }; |
| |
| imgsys: syscon@15000000 { |
| compatible = "mediatek,mt7623-imgsys", |
| "mediatek,mt2701-imgsys", |
| "syscon"; |
| reg = <0 0x15000000 0 0x1000>; |
| #clock-cells = <1>; |
| }; |
| |
| iommu: mmsys_iommu@10205000 { |
| compatible = "mediatek,mt7623-m4u", |
| "mediatek,mt2701-m4u"; |
| reg = <0 0x10205000 0 0x1000>; |
| interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>; |
| clocks = <&infracfg CLK_INFRA_M4U>; |
| clock-names = "bclk"; |
| mediatek,larbs = <&larb0 &larb1 &larb2>; |
| #iommu-cells = <1>; |
| }; |
| |
| jpegdec: jpegdec@15004000 { |
| compatible = "mediatek,mt7623-jpgdec", |
| "mediatek,mt2701-jpgdec"; |
| reg = <0 0x15004000 0 0x1000>; |
| interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_LOW>; |
| clocks = <&imgsys CLK_IMG_JPGDEC_SMI>, |
| <&imgsys CLK_IMG_JPGDEC>; |
| clock-names = "jpgdec-smi", |
| "jpgdec"; |
| power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>; |
| iommus = <&iommu MT2701_M4U_PORT_JPGDEC_WDMA>, |
| <&iommu MT2701_M4U_PORT_JPGDEC_BSDMA>; |
| }; |
| |
| smi_common: smi@1000c000 { |
| compatible = "mediatek,mt7623-smi-common", |
| "mediatek,mt2701-smi-common"; |
| reg = <0 0x1000c000 0 0x1000>; |
| clocks = <&infracfg CLK_INFRA_SMI>, |
| <&mmsys CLK_MM_SMI_COMMON>, |
| <&infracfg CLK_INFRA_SMI>; |
| clock-names = "apb", "smi", "async"; |
| power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>; |
| }; |
| |
| ovl: ovl@14007000 { |
| compatible = "mediatek,mt7623-disp-ovl", |
| "mediatek,mt2701-disp-ovl"; |
| reg = <0 0x14007000 0 0x1000>; |
| interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_LOW>; |
| clocks = <&mmsys CLK_MM_DISP_OVL>; |
| iommus = <&iommu MT2701_M4U_PORT_DISP_OVL_0>; |
| }; |
| |
| rdma0: rdma@14008000 { |
| compatible = "mediatek,mt7623-disp-rdma", |
| "mediatek,mt2701-disp-rdma"; |
| reg = <0 0x14008000 0 0x1000>; |
| interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW>; |
| clocks = <&mmsys CLK_MM_DISP_RDMA>; |
| iommus = <&iommu MT2701_M4U_PORT_DISP_RDMA>; |
| }; |
| |
| wdma@14009000 { |
| compatible = "mediatek,mt7623-disp-wdma", |
| "mediatek,mt2701-disp-wdma"; |
| reg = <0 0x14009000 0 0x1000>; |
| interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_LOW>; |
| clocks = <&mmsys CLK_MM_DISP_WDMA>; |
| iommus = <&iommu MT2701_M4U_PORT_DISP_WDMA>; |
| }; |
| |
| bls: pwm@1400a000 { |
| compatible = "mediatek,mt7623-disp-pwm", |
| "mediatek,mt2701-disp-pwm"; |
| reg = <0 0x1400a000 0 0x1000>; |
| #pwm-cells = <2>; |
| clocks = <&mmsys CLK_MM_MDP_BLS_26M>, |
| <&mmsys CLK_MM_DISP_BLS>; |
| clock-names = "main", "mm"; |
| status = "disabled"; |
| }; |
| |
| color: color@1400b000 { |
| compatible = "mediatek,mt7623-disp-color", |
| "mediatek,mt2701-disp-color"; |
| reg = <0 0x1400b000 0 0x1000>; |
| interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_LOW>; |
| clocks = <&mmsys CLK_MM_DISP_COLOR>; |
| }; |
| |
| dsi: dsi@1400c000 { |
| compatible = "mediatek,mt7623-dsi", |
| "mediatek,mt2701-dsi"; |
| reg = <0 0x1400c000 0 0x1000>; |
| interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_LOW>; |
| clocks = <&mmsys CLK_MM_DSI_ENGINE>, |
| <&mmsys CLK_MM_DSI_DIG>, |
| <&mipi_tx0>; |
| clock-names = "engine", "digital", "hs"; |
| phys = <&mipi_tx0>; |
| phy-names = "dphy"; |
| status = "disabled"; |
| }; |
| |
| mutex: mutex@1400e000 { |
| compatible = "mediatek,mt7623-disp-mutex", |
| "mediatek,mt2701-disp-mutex"; |
| reg = <0 0x1400e000 0 0x1000>; |
| interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_LOW>; |
| clocks = <&mmsys CLK_MM_MUTEX_32K>; |
| }; |
| |
| rdma1: rdma@14012000 { |
| compatible = "mediatek,mt7623-disp-rdma", |
| "mediatek,mt2701-disp-rdma"; |
| reg = <0 0x14012000 0 0x1000>; |
| interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_LOW>; |
| clocks = <&mmsys CLK_MM_DISP_RDMA1>; |
| iommus = <&iommu MT2701_M4U_PORT_DISP_RDMA1>; |
| }; |
| |
| dpi0: dpi@14014000 { |
| compatible = "mediatek,mt7623-dpi", |
| "mediatek,mt2701-dpi"; |
| reg = <0 0x14014000 0 0x1000>; |
| interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>; |
| clocks = <&mmsys CLK_MM_DPI1_DIGL>, |
| <&mmsys CLK_MM_DPI1_ENGINE>, |
| <&apmixedsys CLK_APMIXED_TVDPLL>; |
| clock-names = "pixel", "engine", "pll"; |
| status = "disabled"; |
| }; |
| |
| hdmi0: hdmi@14015000 { |
| compatible = "mediatek,mt7623-hdmi", |
| "mediatek,mt2701-hdmi"; |
| reg = <0 0x14015000 0 0x400>; |
| clocks = <&mmsys CLK_MM_HDMI_PIXEL>, |
| <&mmsys CLK_MM_HDMI_PLL>, |
| <&mmsys CLK_MM_HDMI_AUDIO>, |
| <&mmsys CLK_MM_HDMI_SPDIF>; |
| clock-names = "pixel", "pll", "bclk", "spdif"; |
| phys = <&hdmi_phy>; |
| phy-names = "hdmi"; |
| mediatek,syscon-hdmi = <&mmsys 0x900>; |
| cec = <&cec>; |
| status = "disabled"; |
| }; |
| |
| mipi_tx0: dsi-phy@10010000 { |
| compatible = "mediatek,mt7623-mipi-tx", |
| "mediatek,mt2701-mipi-tx"; |
| reg = <0 0x10010000 0 0x90>; |
| clocks = <&clk26m>; |
| clock-output-names = "mipi_tx0_pll"; |
| #clock-cells = <0>; |
| #phy-cells = <0>; |
| }; |
| |
| cec: cec@10012000 { |
| compatible = "mediatek,mt7623-cec", |
| "mediatek,mt8173-cec"; |
| reg = <0 0x10012000 0 0xbc>; |
| interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>; |
| clocks = <&infracfg CLK_INFRA_CEC>; |
| status = "disabled"; |
| }; |
| |
| hdmi_phy: hdmi-phy@10209100 { |
| compatible = "mediatek,mt7623-hdmi-phy", |
| "mediatek,mt2701-hdmi-phy"; |
| reg = <0 0x10209100 0 0x24>; |
| clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>; |
| clock-names = "pll_ref"; |
| clock-output-names = "hdmitx_dig_cts"; |
| #clock-cells = <0>; |
| #phy-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| hdmiddc0: i2c@11013000 { |
| compatible = "mediatek,mt7623-hdmi-ddc", |
| "mediatek,mt8173-hdmi-ddc"; |
| interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>; |
| reg = <0 0x11013000 0 0x1C>; |
| clocks = <&pericfg CLK_PERI_I2C3>; |
| clock-names = "ddc-i2c"; |
| status = "disabled"; |
| }; |
| }; |
| |
| &pio { |
| hdmi_pins_a: hdmi-default { |
| pins-hdmi { |
| pinmux = <MT7623_PIN_123_HTPLG_FUNC_HTPLG>; |
| input-enable; |
| bias-pull-down; |
| }; |
| }; |
| |
| hdmi_ddc_pins_a: hdmi_ddc-default { |
| pins-hdmi-ddc { |
| pinmux = <MT7623_PIN_124_GPIO124_FUNC_HDMISCK>, |
| <MT7623_PIN_125_GPIO125_FUNC_HDMISD>; |
| }; |
| }; |
| }; |
