| // SPDX-License-Identifier: (GPL-2.0 OR MIT) |
| /* |
| * Copyright (C) 2022 Sophgo Technology Inc. All rights reserved. |
| */ |
| |
| / { |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| timebase-frequency = <50000000>; |
| |
| cpu-map { |
| socket0 { |
| cluster0 { |
| core0 { |
| cpu = <&cpu0>; |
| }; |
| core1 { |
| cpu = <&cpu1>; |
| }; |
| core2 { |
| cpu = <&cpu2>; |
| }; |
| core3 { |
| cpu = <&cpu3>; |
| }; |
| }; |
| |
| cluster1 { |
| core0 { |
| cpu = <&cpu4>; |
| }; |
| core1 { |
| cpu = <&cpu5>; |
| }; |
| core2 { |
| cpu = <&cpu6>; |
| }; |
| core3 { |
| cpu = <&cpu7>; |
| }; |
| }; |
| |
| cluster2 { |
| core0 { |
| cpu = <&cpu16>; |
| }; |
| core1 { |
| cpu = <&cpu17>; |
| }; |
| core2 { |
| cpu = <&cpu18>; |
| }; |
| core3 { |
| cpu = <&cpu19>; |
| }; |
| }; |
| |
| cluster3 { |
| core0 { |
| cpu = <&cpu20>; |
| }; |
| core1 { |
| cpu = <&cpu21>; |
| }; |
| core2 { |
| cpu = <&cpu22>; |
| }; |
| core3 { |
| cpu = <&cpu23>; |
| }; |
| }; |
| |
| cluster4 { |
| core0 { |
| cpu = <&cpu8>; |
| }; |
| core1 { |
| cpu = <&cpu9>; |
| }; |
| core2 { |
| cpu = <&cpu10>; |
| }; |
| core3 { |
| cpu = <&cpu11>; |
| }; |
| }; |
| |
| cluster5 { |
| core0 { |
| cpu = <&cpu12>; |
| }; |
| core1 { |
| cpu = <&cpu13>; |
| }; |
| core2 { |
| cpu = <&cpu14>; |
| }; |
| core3 { |
| cpu = <&cpu15>; |
| }; |
| }; |
| |
| cluster6 { |
| core0 { |
| cpu = <&cpu24>; |
| }; |
| core1 { |
| cpu = <&cpu25>; |
| }; |
| core2 { |
| cpu = <&cpu26>; |
| }; |
| core3 { |
| cpu = <&cpu27>; |
| }; |
| }; |
| |
| cluster7 { |
| core0 { |
| cpu = <&cpu28>; |
| }; |
| core1 { |
| cpu = <&cpu29>; |
| }; |
| core2 { |
| cpu = <&cpu30>; |
| }; |
| core3 { |
| cpu = <&cpu31>; |
| }; |
| }; |
| |
| cluster8 { |
| core0 { |
| cpu = <&cpu32>; |
| }; |
| core1 { |
| cpu = <&cpu33>; |
| }; |
| core2 { |
| cpu = <&cpu34>; |
| }; |
| core3 { |
| cpu = <&cpu35>; |
| }; |
| }; |
| |
| cluster9 { |
| core0 { |
| cpu = <&cpu36>; |
| }; |
| core1 { |
| cpu = <&cpu37>; |
| }; |
| core2 { |
| cpu = <&cpu38>; |
| }; |
| core3 { |
| cpu = <&cpu39>; |
| }; |
| }; |
| |
| cluster10 { |
| core0 { |
| cpu = <&cpu48>; |
| }; |
| core1 { |
| cpu = <&cpu49>; |
| }; |
| core2 { |
| cpu = <&cpu50>; |
| }; |
| core3 { |
| cpu = <&cpu51>; |
| }; |
| }; |
| |
| cluster11 { |
| core0 { |
| cpu = <&cpu52>; |
| }; |
| core1 { |
| cpu = <&cpu53>; |
| }; |
| core2 { |
| cpu = <&cpu54>; |
| }; |
| core3 { |
| cpu = <&cpu55>; |
| }; |
| }; |
| |
| cluster12 { |
| core0 { |
| cpu = <&cpu40>; |
| }; |
| core1 { |
| cpu = <&cpu41>; |
| }; |
| core2 { |
| cpu = <&cpu42>; |
| }; |
| core3 { |
| cpu = <&cpu43>; |
| }; |
| }; |
| |
| cluster13 { |
| core0 { |
| cpu = <&cpu44>; |
| }; |
| core1 { |
| cpu = <&cpu45>; |
| }; |
| core2 { |
| cpu = <&cpu46>; |
| }; |
| core3 { |
| cpu = <&cpu47>; |
| }; |
| }; |
| |
| cluster14 { |
| core0 { |
| cpu = <&cpu56>; |
| }; |
| core1 { |
| cpu = <&cpu57>; |
| }; |
| core2 { |
| cpu = <&cpu58>; |
| }; |
| core3 { |
| cpu = <&cpu59>; |
| }; |
| }; |
| |
| cluster15 { |
| core0 { |
| cpu = <&cpu60>; |
| }; |
| core1 { |
| cpu = <&cpu61>; |
| }; |
| core2 { |
| cpu = <&cpu62>; |
| }; |
| core3 { |
| cpu = <&cpu63>; |
| }; |
| }; |
| }; |
| }; |
| |
| cpu0: cpu@0 { |
| compatible = "thead,c920", "riscv"; |
| device_type = "cpu"; |
| riscv,isa = "rv64imafdc"; |
| riscv,isa-base = "rv64i"; |
| riscv,isa-extensions = "i", "m", "a", "f", "d", "c", |
| "zicntr", "zicsr", "zifencei", |
| "zihpm"; |
| reg = <0>; |
| i-cache-block-size = <64>; |
| i-cache-size = <65536>; |
| i-cache-sets = <512>; |
| d-cache-block-size = <64>; |
| d-cache-size = <65536>; |
| d-cache-sets = <512>; |
| next-level-cache = <&l2_cache0>; |
| mmu-type = "riscv,sv39"; |
| |
| cpu0_intc: interrupt-controller { |
| compatible = "riscv,cpu-intc"; |
| interrupt-controller; |
| #interrupt-cells = <1>; |
| }; |
| }; |
| |
| cpu1: cpu@1 { |
| compatible = "thead,c920", "riscv"; |
| device_type = "cpu"; |
| riscv,isa = "rv64imafdc"; |
| riscv,isa-base = "rv64i"; |
| riscv,isa-extensions = "i", "m", "a", "f", "d", "c", |
| "zicntr", "zicsr", "zifencei", |
| "zihpm"; |
| reg = <1>; |
| i-cache-block-size = <64>; |
| i-cache-size = <65536>; |
| i-cache-sets = <512>; |
| d-cache-block-size = <64>; |
| d-cache-size = <65536>; |
| d-cache-sets = <512>; |
| next-level-cache = <&l2_cache0>; |
| mmu-type = "riscv,sv39"; |
| |
| cpu1_intc: interrupt-controller { |
| compatible = "riscv,cpu-intc"; |
| interrupt-controller; |
| #interrupt-cells = <1>; |
| }; |
| }; |
| |
| cpu2: cpu@2 { |
| compatible = "thead,c920", "riscv"; |
| device_type = "cpu"; |
| riscv,isa = "rv64imafdc"; |
| riscv,isa-base = "rv64i"; |
| riscv,isa-extensions = "i", "m", "a", "f", "d", "c", |
| "zicntr", "zicsr", "zifencei", |
| "zihpm"; |
| reg = <2>; |
| i-cache-block-size = <64>; |
| i-cache-size = <65536>; |
| i-cache-sets = <512>; |
| d-cache-block-size = <64>; |
| d-cache-size = <65536>; |
| d-cache-sets = <512>; |
| next-level-cache = <&l2_cache0>; |
| mmu-type = "riscv,sv39"; |
| |
| cpu2_intc: interrupt-controller { |
| compatible = "riscv,cpu-intc"; |
| interrupt-controller; |
| #interrupt-cells = <1>; |
| }; |
| }; |
| |
| cpu3: cpu@3 { |
| compatible = "thead,c920", "riscv"; |
| device_type = "cpu"; |
| riscv,isa = "rv64imafdc"; |
| riscv,isa-base = "rv64i"; |
| riscv,isa-extensions = "i", "m", "a", "f", "d", "c", |
| "zicntr", "zicsr", "zifencei", |
| "zihpm"; |
| reg = <3>; |
| i-cache-block-size = <64>; |
| i-cache-size = <65536>; |
| i-cache-sets = <512>; |
| d-cache-block-size = <64>; |
| d-cache-size = <65536>; |
| d-cache-sets = <512>; |
| next-level-cache = <&l2_cache0>; |
| mmu-type = "riscv,sv39"; |
| |
| cpu3_intc: interrupt-controller { |
| compatible = "riscv,cpu-intc"; |
| interrupt-controller; |
| #interrupt-cells = <1>; |
| }; |
| }; |
| |
| cpu4: cpu@4 { |
| compatible = "thead,c920", "riscv"; |
| device_type = "cpu"; |
| riscv,isa = "rv64imafdc"; |
| riscv,isa-base = "rv64i"; |
| riscv,isa-extensions = "i", "m", "a", "f", "d", "c", |
| "zicntr", "zicsr", "zifencei", |
| "zihpm"; |
| reg = <4>; |
| i-cache-block-size = <64>; |
| i-cache-size = <65536>; |
| i-cache-sets = <512>; |
| d-cache-block-size = <64>; |
| d-cache-size = <65536>; |
| d-cache-sets = <512>; |
| next-level-cache = <&l2_cache1>; |
| mmu-type = "riscv,sv39"; |
| |
| cpu4_intc: interrupt-controller { |
| compatible = "riscv,cpu-intc"; |
| interrupt-controller; |
| #interrupt-cells = <1>; |
| }; |
| }; |
| |
| cpu5: cpu@5 { |
| compatible = "thead,c920", "riscv"; |
| device_type = "cpu"; |
| riscv,isa = "rv64imafdc"; |
| riscv,isa-base = "rv64i"; |
| riscv,isa-extensions = "i", "m", "a", "f", "d", "c", |
| "zicntr", "zicsr", "zifencei", |
| "zihpm"; |
| reg = <5>; |
| i-cache-block-size = <64>; |
| i-cache-size = <65536>; |
| i-cache-sets = <512>; |
| d-cache-block-size = <64>; |
| d-cache-size = <65536>; |
| d-cache-sets = <512>; |
| next-level-cache = <&l2_cache1>; |
| mmu-type = "riscv,sv39"; |
| |
| cpu5_intc: interrupt-controller { |
| compatible = "riscv,cpu-intc"; |
| interrupt-controller; |
| #interrupt-cells = <1>; |
| }; |
| }; |
| |
| cpu6: cpu@6 { |
| compatible = "thead,c920", "riscv"; |
| device_type = "cpu"; |
| riscv,isa = "rv64imafdc"; |
| riscv,isa-base = "rv64i"; |
| riscv,isa-extensions = "i", "m", "a", "f", "d", "c", |
| "zicntr", "zicsr", "zifencei", |
| "zihpm"; |
| reg = <6>; |
| i-cache-block-size = <64>; |
| i-cache-size = <65536>; |
| i-cache-sets = <512>; |
| d-cache-block-size = <64>; |
| d-cache-size = <65536>; |
| d-cache-sets = <512>; |
| next-level-cache = <&l2_cache1>; |
| mmu-type = "riscv,sv39"; |
| |
| cpu6_intc: interrupt-controller { |
| compatible = "riscv,cpu-intc"; |
| interrupt-controller; |
| #interrupt-cells = <1>; |
| }; |
| }; |
| |
| cpu7: cpu@7 { |
| compatible = "thead,c920", "riscv"; |
| device_type = "cpu"; |
| riscv,isa = "rv64imafdc"; |
| riscv,isa-base = "rv64i"; |
| riscv,isa-extensions = "i", "m", "a", "f", "d", "c", |
| "zicntr", "zicsr", "zifencei", |
| "zihpm"; |
| reg = <7>; |
| i-cache-block-size = <64>; |
| i-cache-size = <65536>; |
| i-cache-sets = <512>; |
| d-cache-block-size = <64>; |
| d-cache-size = <65536>; |
| d-cache-sets = <512>; |
| next-level-cache = <&l2_cache1>; |
| mmu-type = "riscv,sv39"; |
| |
| cpu7_intc: interrupt-controller { |
| compatible = "riscv,cpu-intc"; |
| interrupt-controller; |
| #interrupt-cells = <1>; |
| }; |
| }; |
| |
| cpu8: cpu@8 { |
| compatible = "thead,c920", "riscv"; |
| device_type = "cpu"; |
| riscv,isa = "rv64imafdc"; |
| riscv,isa-base = "rv64i"; |
| riscv,isa-extensions = "i", "m", "a", "f", "d", "c", |
| "zicntr", "zicsr", "zifencei", |
| "zihpm"; |
| reg = <8>; |
| i-cache-block-size = <64>; |
| i-cache-size = <65536>; |
| i-cache-sets = <512>; |
| d-cache-block-size = <64>; |
| d-cache-size = <65536>; |
| d-cache-sets = <512>; |
| next-level-cache = <&l2_cache4>; |
| mmu-type = "riscv,sv39"; |
| |
| cpu8_intc: interrupt-controller { |
| compatible = "riscv,cpu-intc"; |
| interrupt-controller; |
| #interrupt-cells = <1>; |
| }; |
| }; |
| |
| cpu9: cpu@9 { |
| compatible = "thead,c920", "riscv"; |
| device_type = "cpu"; |
| riscv,isa = "rv64imafdc"; |
| riscv,isa-base = "rv64i"; |
| riscv,isa-extensions = "i", "m", "a", "f", "d", "c", |
| "zicntr", "zicsr", "zifencei", |
| "zihpm"; |
| reg = <9>; |
| i-cache-block-size = <64>; |
| i-cache-size = <65536>; |
| i-cache-sets = <512>; |
| d-cache-block-size = <64>; |
| d-cache-size = <65536>; |
| d-cache-sets = <512>; |
| next-level-cache = <&l2_cache4>; |
| mmu-type = "riscv,sv39"; |
| |
| cpu9_intc: interrupt-controller { |
| compatible = "riscv,cpu-intc"; |
| interrupt-controller; |
| #interrupt-cells = <1>; |
| }; |
| }; |
| |
| cpu10: cpu@10 { |
| compatible = "thead,c920", "riscv"; |
| device_type = "cpu"; |
| riscv,isa = "rv64imafdc"; |
| riscv,isa-base = "rv64i"; |
| riscv,isa-extensions = "i", "m", "a", "f", "d", "c", |
| "zicntr", "zicsr", "zifencei", |
| "zihpm"; |
| reg = <10>; |
| i-cache-block-size = <64>; |
| i-cache-size = <65536>; |
| i-cache-sets = <512>; |
| d-cache-block-size = <64>; |
| d-cache-size = <65536>; |
| d-cache-sets = <512>; |
| next-level-cache = <&l2_cache4>; |
| mmu-type = "riscv,sv39"; |
| |
| cpu10_intc: interrupt-controller { |
| compatible = "riscv,cpu-intc"; |
| interrupt-controller; |
| #interrupt-cells = <1>; |
| }; |
| }; |
| |
| cpu11: cpu@11 { |
| compatible = "thead,c920", "riscv"; |
| device_type = "cpu"; |
| riscv,isa = "rv64imafdc"; |
| riscv,isa-base = "rv64i"; |
| riscv,isa-extensions = "i", "m", "a", "f", "d", "c", |
| "zicntr", "zicsr", "zifencei", |
| "zihpm"; |
| reg = <11>; |
| i-cache-block-size = <64>; |
| i-cache-size = <65536>; |
| i-cache-sets = <512>; |
| d-cache-block-size = <64>; |
| d-cache-size = <65536>; |
| d-cache-sets = <512>; |
| next-level-cache = <&l2_cache4>; |
| mmu-type = "riscv,sv39"; |
| |
| cpu11_intc: interrupt-controller { |
| compatible = "riscv,cpu-intc"; |
| interrupt-controller; |
| #interrupt-cells = <1>; |
| }; |
| }; |
| |
| cpu12: cpu@12 { |
| compatible = "thead,c920", "riscv"; |
| device_type = "cpu"; |
| riscv,isa = "rv64imafdc"; |
| riscv,isa-base = "rv64i"; |
| riscv,isa-extensions = "i", "m", "a", "f", "d", "c", |
| "zicntr", "zicsr", "zifencei", |
| "zihpm"; |
| reg = <12>; |
| i-cache-block-size = <64>; |
| i-cache-size = <65536>; |
| i-cache-sets = <512>; |
| d-cache-block-size = <64>; |
| d-cache-size = <65536>; |
| d-cache-sets = <512>; |
| next-level-cache = <&l2_cache5>; |
| mmu-type = "riscv,sv39"; |
| |
| cpu12_intc: interrupt-controller { |
| compatible = "riscv,cpu-intc"; |
| interrupt-controller; |
| #interrupt-cells = <1>; |
| }; |
| }; |
| |
| cpu13: cpu@13 { |
| compatible = "thead,c920", "riscv"; |
| device_type = "cpu"; |
| riscv,isa = "rv64imafdc"; |
| riscv,isa-base = "rv64i"; |
| riscv,isa-extensions = "i", "m", "a", "f", "d", "c", |
| "zicntr", "zicsr", "zifencei", |
| "zihpm"; |
| reg = <13>; |
| i-cache-block-size = <64>; |
| i-cache-size = <65536>; |
| i-cache-sets = <512>; |
| d-cache-block-size = <64>; |
| d-cache-size = <65536>; |
| d-cache-sets = <512>; |
| next-level-cache = <&l2_cache5>; |
| mmu-type = "riscv,sv39"; |
| |
| cpu13_intc: interrupt-controller { |
| compatible = "riscv,cpu-intc"; |
| interrupt-controller; |
| #interrupt-cells = <1>; |
| }; |
| }; |
| |
| cpu14: cpu@14 { |
| compatible = "thead,c920", "riscv"; |
| device_type = "cpu"; |
| riscv,isa = "rv64imafdc"; |
| riscv,isa-base = "rv64i"; |
| riscv,isa-extensions = "i", "m", "a", "f", "d", "c", |
| "zicntr", "zicsr", "zifencei", |
| "zihpm"; |
| reg = <14>; |
| i-cache-block-size = <64>; |
| i-cache-size = <65536>; |
| i-cache-sets = <512>; |
| d-cache-block-size = <64>; |
| d-cache-size = <65536>; |
| d-cache-sets = <512>; |
| next-level-cache = <&l2_cache5>; |
| mmu-type = "riscv,sv39"; |
| |
| cpu14_intc: interrupt-controller { |
| compatible = "riscv,cpu-intc"; |
| interrupt-controller; |
| #interrupt-cells = <1>; |
| }; |
| }; |
| |
| cpu15: cpu@15 { |
| compatible = "thead,c920", "riscv"; |
| device_type = "cpu"; |
| riscv,isa = "rv64imafdc"; |
| riscv,isa-base = "rv64i"; |
| riscv,isa-extensions = "i", "m", "a", "f", "d", "c", |
| "zicntr", "zicsr", "zifencei", |
| "zihpm"; |
| reg = <15>; |
| i-cache-block-size = <64>; |
| i-cache-size = <65536>; |
| i-cache-sets = <512>; |
| d-cache-block-size = <64>; |
| d-cache-size = <65536>; |
| d-cache-sets = <512>; |
| next-level-cache = <&l2_cache5>; |
| mmu-type = "riscv,sv39"; |
| |
| cpu15_intc: interrupt-controller { |
| compatible = "riscv,cpu-intc"; |
| interrupt-controller; |
| #interrupt-cells = <1>; |
| }; |
| }; |
| |
| cpu16: cpu@16 { |
| compatible = "thead,c920", "riscv"; |
| device_type = "cpu"; |
| riscv,isa = "rv64imafdc"; |
| riscv,isa-base = "rv64i"; |
| riscv,isa-extensions = "i", "m", "a", "f", "d", "c", |
| "zicntr", "zicsr", "zifencei", |
| "zihpm"; |
| reg = <16>; |
| i-cache-block-size = <64>; |
| i-cache-size = <65536>; |
| i-cache-sets = <512>; |
| d-cache-block-size = <64>; |
| d-cache-size = <65536>; |
| d-cache-sets = <512>; |
| next-level-cache = <&l2_cache2>; |
| mmu-type = "riscv,sv39"; |
| |
| cpu16_intc: interrupt-controller { |
| compatible = "riscv,cpu-intc"; |
| interrupt-controller; |
| #interrupt-cells = <1>; |
| }; |
| }; |
| |
| cpu17: cpu@17 { |
| compatible = "thead,c920", "riscv"; |
| device_type = "cpu"; |
| riscv,isa = "rv64imafdc"; |
| riscv,isa-base = "rv64i"; |
| riscv,isa-extensions = "i", "m", "a", "f", "d", "c", |
| "zicntr", "zicsr", "zifencei", |
| "zihpm"; |
| reg = <17>; |
| i-cache-block-size = <64>; |
| i-cache-size = <65536>; |
| i-cache-sets = <512>; |
| d-cache-block-size = <64>; |
| d-cache-size = <65536>; |
| d-cache-sets = <512>; |
| next-level-cache = <&l2_cache2>; |
| mmu-type = "riscv,sv39"; |
| |
| cpu17_intc: interrupt-controller { |
| compatible = "riscv,cpu-intc"; |
| interrupt-controller; |
| #interrupt-cells = <1>; |
| }; |
| }; |
| |
| cpu18: cpu@18 { |
| compatible = "thead,c920", "riscv"; |
| device_type = "cpu"; |
| riscv,isa = "rv64imafdc"; |
| riscv,isa-base = "rv64i"; |
| riscv,isa-extensions = "i", "m", "a", "f", "d", "c", |
| "zicntr", "zicsr", "zifencei", |
| "zihpm"; |
| reg = <18>; |
| i-cache-block-size = <64>; |
| i-cache-size = <65536>; |
| i-cache-sets = <512>; |
| d-cache-block-size = <64>; |
| d-cache-size = <65536>; |
| d-cache-sets = <512>; |
| next-level-cache = <&l2_cache2>; |
| mmu-type = "riscv,sv39"; |
| |
| cpu18_intc: interrupt-controller { |
| compatible = "riscv,cpu-intc"; |
| interrupt-controller; |
| #interrupt-cells = <1>; |
| }; |
| }; |
| |
| cpu19: cpu@19 { |
| compatible = "thead,c920", "riscv"; |
| device_type = "cpu"; |
| riscv,isa = "rv64imafdc"; |
| riscv,isa-base = "rv64i"; |
| riscv,isa-extensions = "i", "m", "a", "f", "d", "c", |
| "zicntr", "zicsr", "zifencei", |
| "zihpm"; |
| reg = <19>; |
| i-cache-block-size = <64>; |
| i-cache-size = <65536>; |
| i-cache-sets = <512>; |
| d-cache-block-size = <64>; |
| d-cache-size = <65536>; |
| d-cache-sets = <512>; |
| next-level-cache = <&l2_cache2>; |
| mmu-type = "riscv,sv39"; |
| |
| cpu19_intc: interrupt-controller { |
| compatible = "riscv,cpu-intc"; |
| interrupt-controller; |
| #interrupt-cells = <1>; |
| }; |
| }; |
| |
| cpu20: cpu@20 { |
| compatible = "thead,c920", "riscv"; |
| device_type = "cpu"; |
| riscv,isa = "rv64imafdc"; |
| riscv,isa-base = "rv64i"; |
| riscv,isa-extensions = "i", "m", "a", "f", "d", "c", |
| "zicntr", "zicsr", "zifencei", |
| "zihpm"; |
| reg = <20>; |
| i-cache-block-size = <64>; |
| i-cache-size = <65536>; |
| i-cache-sets = <512>; |
| d-cache-block-size = <64>; |
| d-cache-size = <65536>; |
| d-cache-sets = <512>; |
| next-level-cache = <&l2_cache3>; |
| mmu-type = "riscv,sv39"; |
| |
| cpu20_intc: interrupt-controller { |
| compatible = "riscv,cpu-intc"; |
| interrupt-controller; |
| #interrupt-cells = <1>; |
| }; |
| }; |
| |
| cpu21: cpu@21 { |
| compatible = "thead,c920", "riscv"; |
| device_type = "cpu"; |
| riscv,isa = "rv64imafdc"; |
| riscv,isa-base = "rv64i"; |
| riscv,isa-extensions = "i", "m", "a", "f", "d", "c", |
| "zicntr", "zicsr", "zifencei", |
| "zihpm"; |
| reg = <21>; |
| i-cache-block-size = <64>; |
| i-cache-size = <65536>; |
| i-cache-sets = <512>; |
| d-cache-block-size = <64>; |
| d-cache-size = <65536>; |
| d-cache-sets = <512>; |
| next-level-cache = <&l2_cache3>; |
| mmu-type = "riscv,sv39"; |
| |
| cpu21_intc: interrupt-controller { |
| compatible = "riscv,cpu-intc"; |
| interrupt-controller; |
| #interrupt-cells = <1>; |
| }; |
| }; |
| |
| cpu22: cpu@22 { |
| compatible = "thead,c920", "riscv"; |
| device_type = "cpu"; |
| riscv,isa = "rv64imafdc"; |
| riscv,isa-base = "rv64i"; |
| riscv,isa-extensions = "i", "m", "a", "f", "d", "c", |
| "zicntr", "zicsr", "zifencei", |
| "zihpm"; |
| reg = <22>; |
| i-cache-block-size = <64>; |
| i-cache-size = <65536>; |
| i-cache-sets = <512>; |
| d-cache-block-size = <64>; |
| d-cache-size = <65536>; |
| d-cache-sets = <512>; |
| next-level-cache = <&l2_cache3>; |
| mmu-type = "riscv,sv39"; |
| |
| cpu22_intc: interrupt-controller { |
| compatible = "riscv,cpu-intc"; |
| interrupt-controller; |
| #interrupt-cells = <1>; |
| }; |
| }; |
| |
| cpu23: cpu@23 { |
| compatible = "thead,c920", "riscv"; |
| device_type = "cpu"; |
| riscv,isa = "rv64imafdc"; |
| riscv,isa-base = "rv64i"; |
| riscv,isa-extensions = "i", "m", "a", "f", "d", "c", |
| "zicntr", "zicsr", "zifencei", |
| "zihpm"; |
| reg = <23>; |
| i-cache-block-size = <64>; |
| i-cache-size = <65536>; |
| i-cache-sets = <512>; |
| d-cache-block-size = <64>; |
| d-cache-size = <65536>; |
| d-cache-sets = <512>; |
| next-level-cache = <&l2_cache3>; |
| mmu-type = "riscv,sv39"; |
| |
| cpu23_intc: interrupt-controller { |
| compatible = "riscv,cpu-intc"; |
| interrupt-controller; |
| #interrupt-cells = <1>; |
| }; |
| }; |
| |
| cpu24: cpu@24 { |
| compatible = "thead,c920", "riscv"; |
| device_type = "cpu"; |
| riscv,isa = "rv64imafdc"; |
| riscv,isa-base = "rv64i"; |
| riscv,isa-extensions = "i", "m", "a", "f", "d", "c", |
| "zicntr", "zicsr", "zifencei", |
| "zihpm"; |
| reg = <24>; |
| i-cache-block-size = <64>; |
| i-cache-size = <65536>; |
| i-cache-sets = <512>; |
| d-cache-block-size = <64>; |
| d-cache-size = <65536>; |
| d-cache-sets = <512>; |
| next-level-cache = <&l2_cache6>; |
| mmu-type = "riscv,sv39"; |
| |
| cpu24_intc: interrupt-controller { |
| compatible = "riscv,cpu-intc"; |
| interrupt-controller; |
| #interrupt-cells = <1>; |
| }; |
| }; |
| |
| cpu25: cpu@25 { |
| compatible = "thead,c920", "riscv"; |
| device_type = "cpu"; |
| riscv,isa = "rv64imafdc"; |
| riscv,isa-base = "rv64i"; |
| riscv,isa-extensions = "i", "m", "a", "f", "d", "c", |
| "zicntr", "zicsr", "zifencei", |
| "zihpm"; |
| reg = <25>; |
| i-cache-block-size = <64>; |
| i-cache-size = <65536>; |
| i-cache-sets = <512>; |
| d-cache-block-size = <64>; |
| d-cache-size = <65536>; |
| d-cache-sets = <512>; |
| next-level-cache = <&l2_cache6>; |
| mmu-type = "riscv,sv39"; |
| |
| cpu25_intc: interrupt-controller { |
| compatible = "riscv,cpu-intc"; |
| interrupt-controller; |
| #interrupt-cells = <1>; |
| }; |
| }; |
| |
| cpu26: cpu@26 { |
| compatible = "thead,c920", "riscv"; |
| device_type = "cpu"; |
| riscv,isa = "rv64imafdc"; |
| riscv,isa-base = "rv64i"; |
| riscv,isa-extensions = "i", "m", "a", "f", "d", "c", |
| "zicntr", "zicsr", "zifencei", |
| "zihpm"; |
| reg = <26>; |
| i-cache-block-size = <64>; |
| i-cache-size = <65536>; |
| i-cache-sets = <512>; |
| d-cache-block-size = <64>; |
| d-cache-size = <65536>; |
| d-cache-sets = <512>; |
| next-level-cache = <&l2_cache6>; |
| mmu-type = "riscv,sv39"; |
| |
| cpu26_intc: interrupt-controller { |
| compatible = "riscv,cpu-intc"; |
| interrupt-controller; |
| #interrupt-cells = <1>; |
| }; |
| }; |
| |
| cpu27: cpu@27 { |
| compatible = "thead,c920", "riscv"; |
| device_type = "cpu"; |
| riscv,isa = "rv64imafdc"; |
| riscv,isa-base = "rv64i"; |
| riscv,isa-extensions = "i", "m", "a", "f", "d", "c", |
| "zicntr", "zicsr", "zifencei", |
| "zihpm"; |
| reg = <27>; |
| i-cache-block-size = <64>; |
| i-cache-size = <65536>; |
| i-cache-sets = <512>; |
| d-cache-block-size = <64>; |
| d-cache-size = <65536>; |
| d-cache-sets = <512>; |
| next-level-cache = <&l2_cache6>; |
| mmu-type = "riscv,sv39"; |
| |
| cpu27_intc: interrupt-controller { |
| compatible = "riscv,cpu-intc"; |
| interrupt-controller; |
| #interrupt-cells = <1>; |
| }; |
| }; |
| |
| cpu28: cpu@28 { |
| compatible = "thead,c920", "riscv"; |
| device_type = "cpu"; |
| riscv,isa = "rv64imafdc"; |
| riscv,isa-base = "rv64i"; |
| riscv,isa-extensions = "i", "m", "a", "f", "d", "c", |
| "zicntr", "zicsr", "zifencei", |
| "zihpm"; |
| reg = <28>; |
| i-cache-block-size = <64>; |
| i-cache-size = <65536>; |
| i-cache-sets = <512>; |
| d-cache-block-size = <64>; |
| d-cache-size = <65536>; |
| d-cache-sets = <512>; |
| next-level-cache = <&l2_cache7>; |
| mmu-type = "riscv,sv39"; |
| |
| cpu28_intc: interrupt-controller { |
| compatible = "riscv,cpu-intc"; |
| interrupt-controller; |
| #interrupt-cells = <1>; |
| }; |
| }; |
| |
| cpu29: cpu@29 { |
| compatible = "thead,c920", "riscv"; |
| device_type = "cpu"; |
| riscv,isa = "rv64imafdc"; |
| riscv,isa-base = "rv64i"; |
| riscv,isa-extensions = "i", "m", "a", "f", "d", "c", |
| "zicntr", "zicsr", "zifencei", |
| "zihpm"; |
| reg = <29>; |
| i-cache-block-size = <64>; |
| i-cache-size = <65536>; |
| i-cache-sets = <512>; |
| d-cache-block-size = <64>; |
| d-cache-size = <65536>; |
| d-cache-sets = <512>; |
| next-level-cache = <&l2_cache7>; |
| mmu-type = "riscv,sv39"; |
| |
| cpu29_intc: interrupt-controller { |
| compatible = "riscv,cpu-intc"; |
| interrupt-controller; |
| #interrupt-cells = <1>; |
| }; |
| }; |
| |
| cpu30: cpu@30 { |
| compatible = "thead,c920", "riscv"; |
| device_type = "cpu"; |
| riscv,isa = "rv64imafdc"; |
| riscv,isa-base = "rv64i"; |
| riscv,isa-extensions = "i", "m", "a", "f", "d", "c", |
| "zicntr", "zicsr", "zifencei", |
| "zihpm"; |
| reg = <30>; |
| i-cache-block-size = <64>; |
| i-cache-size = <65536>; |
| i-cache-sets = <512>; |
| d-cache-block-size = <64>; |
| d-cache-size = <65536>; |
| d-cache-sets = <512>; |
| next-level-cache = <&l2_cache7>; |
| mmu-type = "riscv,sv39"; |
| |
| cpu30_intc: interrupt-controller { |
| compatible = "riscv,cpu-intc"; |
| interrupt-controller; |
| #interrupt-cells = <1>; |
| }; |
| }; |
| |
| cpu31: cpu@31 { |
| compatible = "thead,c920", "riscv"; |
| device_type = "cpu"; |
| riscv,isa = "rv64imafdc"; |
| riscv,isa-base = "rv64i"; |
| riscv,isa-extensions = "i", "m", "a", "f", "d", "c", |
| "zicntr", "zicsr", "zifencei", |
| "zihpm"; |
| reg = <31>; |
| i-cache-block-size = <64>; |
| i-cache-size = <65536>; |
| i-cache-sets = <512>; |
| d-cache-block-size = <64>; |
| d-cache-size = <65536>; |
| d-cache-sets = <512>; |
| next-level-cache = <&l2_cache7>; |
| mmu-type = "riscv,sv39"; |
| |
| cpu31_intc: interrupt-controller { |
| compatible = "riscv,cpu-intc"; |
| interrupt-controller; |
| #interrupt-cells = <1>; |
| }; |
| }; |
| |
| cpu32: cpu@32 { |
| compatible = "thead,c920", "riscv"; |
| device_type = "cpu"; |
| riscv,isa = "rv64imafdc"; |
| riscv,isa-base = "rv64i"; |
| riscv,isa-extensions = "i", "m", "a", "f", "d", "c", |
| "zicntr", "zicsr", "zifencei", |
| "zihpm"; |
| reg = <32>; |
| i-cache-block-size = <64>; |
| i-cache-size = <65536>; |
| i-cache-sets = <512>; |
| d-cache-block-size = <64>; |
| d-cache-size = <65536>; |
| d-cache-sets = <512>; |
| next-level-cache = <&l2_cache8>; |
| mmu-type = "riscv,sv39"; |
| |
| cpu32_intc: interrupt-controller { |
| compatible = "riscv,cpu-intc"; |
| interrupt-controller; |
| #interrupt-cells = <1>; |
| }; |
| }; |
| |
| cpu33: cpu@33 { |
| compatible = "thead,c920", "riscv"; |
| device_type = "cpu"; |
| riscv,isa = "rv64imafdc"; |
| riscv,isa-base = "rv64i"; |
| riscv,isa-extensions = "i", "m", "a", "f", "d", "c", |
| "zicntr", "zicsr", "zifencei", |
| "zihpm"; |
| reg = <33>; |
| i-cache-block-size = <64>; |
| i-cache-size = <65536>; |
| i-cache-sets = <512>; |
| d-cache-block-size = <64>; |
| d-cache-size = <65536>; |
| d-cache-sets = <512>; |
| next-level-cache = <&l2_cache8>; |
| mmu-type = "riscv,sv39"; |
| |
| cpu33_intc: interrupt-controller { |
| compatible = "riscv,cpu-intc"; |
| interrupt-controller; |
| #interrupt-cells = <1>; |
| }; |
| }; |
| |
| cpu34: cpu@34 { |
| compatible = "thead,c920", "riscv"; |
| device_type = "cpu"; |
| riscv,isa = "rv64imafdc"; |
| riscv,isa-base = "rv64i"; |
| riscv,isa-extensions = "i", "m", "a", "f", "d", "c", |
| "zicntr", "zicsr", "zifencei", |
| "zihpm"; |
| reg = <34>; |
| i-cache-block-size = <64>; |
| i-cache-size = <65536>; |
| i-cache-sets = <512>; |
| d-cache-block-size = <64>; |
| d-cache-size = <65536>; |
| d-cache-sets = <512>; |
| next-level-cache = <&l2_cache8>; |
| mmu-type = "riscv,sv39"; |
| |
| cpu34_intc: interrupt-controller { |
| compatible = "riscv,cpu-intc"; |
| interrupt-controller; |
| #interrupt-cells = <1>; |
| }; |
| }; |
| |
| cpu35: cpu@35 { |
| compatible = "thead,c920", "riscv"; |
| device_type = "cpu"; |
| riscv,isa = "rv64imafdc"; |
| riscv,isa-base = "rv64i"; |
| riscv,isa-extensions = "i", "m", "a", "f", "d", "c", |
| "zicntr", "zicsr", "zifencei", |
| "zihpm"; |
| reg = <35>; |
| i-cache-block-size = <64>; |
| i-cache-size = <65536>; |
| i-cache-sets = <512>; |
| d-cache-block-size = <64>; |
| d-cache-size = <65536>; |
| d-cache-sets = <512>; |
| next-level-cache = <&l2_cache8>; |
| mmu-type = "riscv,sv39"; |
| |
| cpu35_intc: interrupt-controller { |
| compatible = "riscv,cpu-intc"; |
| interrupt-controller; |
| #interrupt-cells = <1>; |
| }; |
| }; |
| |
| cpu36: cpu@36 { |
| compatible = "thead,c920", "riscv"; |
| device_type = "cpu"; |
| riscv,isa = "rv64imafdc"; |
| riscv,isa-base = "rv64i"; |
| riscv,isa-extensions = "i", "m", "a", "f", "d", "c", |
| "zicntr", "zicsr", "zifencei", |
| "zihpm"; |
| reg = <36>; |
| i-cache-block-size = <64>; |
| i-cache-size = <65536>; |
| i-cache-sets = <512>; |
| d-cache-block-size = <64>; |
| d-cache-size = <65536>; |
| d-cache-sets = <512>; |
| next-level-cache = <&l2_cache9>; |
| mmu-type = "riscv,sv39"; |
| |
| cpu36_intc: interrupt-controller { |
| compatible = "riscv,cpu-intc"; |
| interrupt-controller; |
| #interrupt-cells = <1>; |
| }; |
| }; |
| |
| cpu37: cpu@37 { |
| compatible = "thead,c920", "riscv"; |
| device_type = "cpu"; |
| riscv,isa = "rv64imafdc"; |
| riscv,isa-base = "rv64i"; |
| riscv,isa-extensions = "i", "m", "a", "f", "d", "c", |
| "zicntr", "zicsr", "zifencei", |
| "zihpm"; |
| reg = <37>; |
| i-cache-block-size = <64>; |
| i-cache-size = <65536>; |
| i-cache-sets = <512>; |
| d-cache-block-size = <64>; |
| d-cache-size = <65536>; |
| d-cache-sets = <512>; |
| next-level-cache = <&l2_cache9>; |
| mmu-type = "riscv,sv39"; |
| |
| cpu37_intc: interrupt-controller { |
| compatible = "riscv,cpu-intc"; |
| interrupt-controller; |
| #interrupt-cells = <1>; |
| }; |
| }; |
| |
| cpu38: cpu@38 { |
| compatible = "thead,c920", "riscv"; |
| device_type = "cpu"; |
| riscv,isa = "rv64imafdc"; |
| riscv,isa-base = "rv64i"; |
| riscv,isa-extensions = "i", "m", "a", "f", "d", "c", |
| "zicntr", "zicsr", "zifencei", |
| "zihpm"; |
| reg = <38>; |
| i-cache-block-size = <64>; |
| i-cache-size = <65536>; |
| i-cache-sets = <512>; |
| d-cache-block-size = <64>; |
| d-cache-size = <65536>; |
| d-cache-sets = <512>; |
| next-level-cache = <&l2_cache9>; |
| mmu-type = "riscv,sv39"; |
| |
| cpu38_intc: interrupt-controller { |
| compatible = "riscv,cpu-intc"; |
| interrupt-controller; |
| #interrupt-cells = <1>; |
| }; |
| }; |
| |
| cpu39: cpu@39 { |
| compatible = "thead,c920", "riscv"; |
| device_type = "cpu"; |
| riscv,isa = "rv64imafdc"; |
| riscv,isa-base = "rv64i"; |
| riscv,isa-extensions = "i", "m", "a", "f", "d", "c", |
| "zicntr", "zicsr", "zifencei", |
| "zihpm"; |
| reg = <39>; |
| i-cache-block-size = <64>; |
| i-cache-size = <65536>; |
| i-cache-sets = <512>; |
| d-cache-block-size = <64>; |
| d-cache-size = <65536>; |
| d-cache-sets = <512>; |
| next-level-cache = <&l2_cache9>; |
| mmu-type = "riscv,sv39"; |
| |
| cpu39_intc: interrupt-controller { |
| compatible = "riscv,cpu-intc"; |
| interrupt-controller; |
| #interrupt-cells = <1>; |
| }; |
| }; |
| |
| cpu40: cpu@40 { |
| compatible = "thead,c920", "riscv"; |
| device_type = "cpu"; |
| riscv,isa = "rv64imafdc"; |
| riscv,isa-base = "rv64i"; |
| riscv,isa-extensions = "i", "m", "a", "f", "d", "c", |
| "zicntr", "zicsr", "zifencei", |
| "zihpm"; |
| reg = <40>; |
| i-cache-block-size = <64>; |
| i-cache-size = <65536>; |
| i-cache-sets = <512>; |
| d-cache-block-size = <64>; |
| d-cache-size = <65536>; |
| d-cache-sets = <512>; |
| next-level-cache = <&l2_cache12>; |
| mmu-type = "riscv,sv39"; |
| |
| cpu40_intc: interrupt-controller { |
| compatible = "riscv,cpu-intc"; |
| interrupt-controller; |
| #interrupt-cells = <1>; |
| }; |
| }; |
| |
| cpu41: cpu@41 { |
| compatible = "thead,c920", "riscv"; |
| device_type = "cpu"; |
| riscv,isa = "rv64imafdc"; |
| riscv,isa-base = "rv64i"; |
| riscv,isa-extensions = "i", "m", "a", "f", "d", "c", |
| "zicntr", "zicsr", "zifencei", |
| "zihpm"; |
| reg = <41>; |
| i-cache-block-size = <64>; |
| i-cache-size = <65536>; |
| i-cache-sets = <512>; |
| d-cache-block-size = <64>; |
| d-cache-size = <65536>; |
| d-cache-sets = <512>; |
| next-level-cache = <&l2_cache12>; |
| mmu-type = "riscv,sv39"; |
| |
| cpu41_intc: interrupt-controller { |
| compatible = "riscv,cpu-intc"; |
| interrupt-controller; |
| #interrupt-cells = <1>; |
| }; |
| }; |
| |
| cpu42: cpu@42 { |
| compatible = "thead,c920", "riscv"; |
| device_type = "cpu"; |
| riscv,isa = "rv64imafdc"; |
| riscv,isa-base = "rv64i"; |
| riscv,isa-extensions = "i", "m", "a", "f", "d", "c", |
| "zicntr", "zicsr", "zifencei", |
| "zihpm"; |
| reg = <42>; |
| i-cache-block-size = <64>; |
| i-cache-size = <65536>; |
| i-cache-sets = <512>; |
| d-cache-block-size = <64>; |
| d-cache-size = <65536>; |
| d-cache-sets = <512>; |
| next-level-cache = <&l2_cache12>; |
| mmu-type = "riscv,sv39"; |
| |
| cpu42_intc: interrupt-controller { |
| compatible = "riscv,cpu-intc"; |
| interrupt-controller; |
| #interrupt-cells = <1>; |
| }; |
| }; |
| |
| cpu43: cpu@43 { |
| compatible = "thead,c920", "riscv"; |
| device_type = "cpu"; |
| riscv,isa = "rv64imafdc"; |
| riscv,isa-base = "rv64i"; |
| riscv,isa-extensions = "i", "m", "a", "f", "d", "c", |
| "zicntr", "zicsr", "zifencei", |
| "zihpm"; |
| reg = <43>; |
| i-cache-block-size = <64>; |
| i-cache-size = <65536>; |
| i-cache-sets = <512>; |
| d-cache-block-size = <64>; |
| d-cache-size = <65536>; |
| d-cache-sets = <512>; |
| next-level-cache = <&l2_cache12>; |
| mmu-type = "riscv,sv39"; |
| |
| cpu43_intc: interrupt-controller { |
| compatible = "riscv,cpu-intc"; |
| interrupt-controller; |
| #interrupt-cells = <1>; |
| }; |
| }; |
| |
| cpu44: cpu@44 { |
| compatible = "thead,c920", "riscv"; |
| device_type = "cpu"; |
| riscv,isa = "rv64imafdc"; |
| riscv,isa-base = "rv64i"; |
| riscv,isa-extensions = "i", "m", "a", "f", "d", "c", |
| "zicntr", "zicsr", "zifencei", |
| "zihpm"; |
| reg = <44>; |
| i-cache-block-size = <64>; |
| i-cache-size = <65536>; |
| i-cache-sets = <512>; |
| d-cache-block-size = <64>; |
| d-cache-size = <65536>; |
| d-cache-sets = <512>; |
| next-level-cache = <&l2_cache13>; |
| mmu-type = "riscv,sv39"; |
| |
| cpu44_intc: interrupt-controller { |
| compatible = "riscv,cpu-intc"; |
| interrupt-controller; |
| #interrupt-cells = <1>; |
| }; |
| }; |
| |
| cpu45: cpu@45 { |
| compatible = "thead,c920", "riscv"; |
| device_type = "cpu"; |
| riscv,isa = "rv64imafdc"; |
| riscv,isa-base = "rv64i"; |
| riscv,isa-extensions = "i", "m", "a", "f", "d", "c", |
| "zicntr", "zicsr", "zifencei", |
| "zihpm"; |
| reg = <45>; |
| i-cache-block-size = <64>; |
| i-cache-size = <65536>; |
| i-cache-sets = <512>; |
| d-cache-block-size = <64>; |
| d-cache-size = <65536>; |
| d-cache-sets = <512>; |
| next-level-cache = <&l2_cache13>; |
| mmu-type = "riscv,sv39"; |
| |
| cpu45_intc: interrupt-controller { |
| compatible = "riscv,cpu-intc"; |
| interrupt-controller; |
| #interrupt-cells = <1>; |
| }; |
| }; |
| |
| cpu46: cpu@46 { |
| compatible = "thead,c920", "riscv"; |
| device_type = "cpu"; |
| riscv,isa = "rv64imafdc"; |
| riscv,isa-base = "rv64i"; |
| riscv,isa-extensions = "i", "m", "a", "f", "d", "c", |
| "zicntr", "zicsr", "zifencei", |
| "zihpm"; |
| reg = <46>; |
| i-cache-block-size = <64>; |
| i-cache-size = <65536>; |
| i-cache-sets = <512>; |
| d-cache-block-size = <64>; |
| d-cache-size = <65536>; |
| d-cache-sets = <512>; |
| next-level-cache = <&l2_cache13>; |
| mmu-type = "riscv,sv39"; |
| |
| cpu46_intc: interrupt-controller { |
| compatible = "riscv,cpu-intc"; |
| interrupt-controller; |
| #interrupt-cells = <1>; |
| }; |
| }; |
| |
| cpu47: cpu@47 { |
| compatible = "thead,c920", "riscv"; |
| device_type = "cpu"; |
| riscv,isa = "rv64imafdc"; |
| riscv,isa-base = "rv64i"; |
| riscv,isa-extensions = "i", "m", "a", "f", "d", "c", |
| "zicntr", "zicsr", "zifencei", |
| "zihpm"; |
| reg = <47>; |
| i-cache-block-size = <64>; |
| i-cache-size = <65536>; |
| i-cache-sets = <512>; |
| d-cache-block-size = <64>; |
| d-cache-size = <65536>; |
| d-cache-sets = <512>; |
| next-level-cache = <&l2_cache13>; |
| mmu-type = "riscv,sv39"; |
| |
| cpu47_intc: interrupt-controller { |
| compatible = "riscv,cpu-intc"; |
| interrupt-controller; |
| #interrupt-cells = <1>; |
| }; |
| }; |
| |
| cpu48: cpu@48 { |
| compatible = "thead,c920", "riscv"; |
| device_type = "cpu"; |
| riscv,isa = "rv64imafdc"; |
| riscv,isa-base = "rv64i"; |
| riscv,isa-extensions = "i", "m", "a", "f", "d", "c", |
| "zicntr", "zicsr", "zifencei", |
| "zihpm"; |
| reg = <48>; |
| i-cache-block-size = <64>; |
| i-cache-size = <65536>; |
| i-cache-sets = <512>; |
| d-cache-block-size = <64>; |
| d-cache-size = <65536>; |
| d-cache-sets = <512>; |
| next-level-cache = <&l2_cache10>; |
| mmu-type = "riscv,sv39"; |
| |
| cpu48_intc: interrupt-controller { |
| compatible = "riscv,cpu-intc"; |
| interrupt-controller; |
| #interrupt-cells = <1>; |
| }; |
| }; |
| |
| cpu49: cpu@49 { |
| compatible = "thead,c920", "riscv"; |
| device_type = "cpu"; |
| riscv,isa = "rv64imafdc"; |
| riscv,isa-base = "rv64i"; |
| riscv,isa-extensions = "i", "m", "a", "f", "d", "c", |
| "zicntr", "zicsr", "zifencei", |
| "zihpm"; |
| reg = <49>; |
| i-cache-block-size = <64>; |
| i-cache-size = <65536>; |
| i-cache-sets = <512>; |
| d-cache-block-size = <64>; |
| d-cache-size = <65536>; |
| d-cache-sets = <512>; |
| next-level-cache = <&l2_cache10>; |
| mmu-type = "riscv,sv39"; |
| |
| cpu49_intc: interrupt-controller { |
| compatible = "riscv,cpu-intc"; |
| interrupt-controller; |
| #interrupt-cells = <1>; |
| }; |
| }; |
| |
| cpu50: cpu@50 { |
| compatible = "thead,c920", "riscv"; |
| device_type = "cpu"; |
| riscv,isa = "rv64imafdc"; |
| riscv,isa-base = "rv64i"; |
| riscv,isa-extensions = "i", "m", "a", "f", "d", "c", |
| "zicntr", "zicsr", "zifencei", |
| "zihpm"; |
| reg = <50>; |
| i-cache-block-size = <64>; |
| i-cache-size = <65536>; |
| i-cache-sets = <512>; |
| d-cache-block-size = <64>; |
| d-cache-size = <65536>; |
| d-cache-sets = <512>; |
| next-level-cache = <&l2_cache10>; |
| mmu-type = "riscv,sv39"; |
| |
| cpu50_intc: interrupt-controller { |
| compatible = "riscv,cpu-intc"; |
| interrupt-controller; |
| #interrupt-cells = <1>; |
| }; |
| }; |
| |
| cpu51: cpu@51 { |
| compatible = "thead,c920", "riscv"; |
| device_type = "cpu"; |
| riscv,isa = "rv64imafdc"; |
| riscv,isa-base = "rv64i"; |
| riscv,isa-extensions = "i", "m", "a", "f", "d", "c", |
| "zicntr", "zicsr", "zifencei", |
| "zihpm"; |
| reg = <51>; |
| i-cache-block-size = <64>; |
| i-cache-size = <65536>; |
| i-cache-sets = <512>; |
| d-cache-block-size = <64>; |
| d-cache-size = <65536>; |
| d-cache-sets = <512>; |
| next-level-cache = <&l2_cache10>; |
| mmu-type = "riscv,sv39"; |
| |
| cpu51_intc: interrupt-controller { |
| compatible = "riscv,cpu-intc"; |
| interrupt-controller; |
| #interrupt-cells = <1>; |
| }; |
| }; |
| |
| cpu52: cpu@52 { |
| compatible = "thead,c920", "riscv"; |
| device_type = "cpu"; |
| riscv,isa = "rv64imafdc"; |
| riscv,isa-base = "rv64i"; |
| riscv,isa-extensions = "i", "m", "a", "f", "d", "c", |
| "zicntr", "zicsr", "zifencei", |
| "zihpm"; |
| reg = <52>; |
| i-cache-block-size = <64>; |
| i-cache-size = <65536>; |
| i-cache-sets = <512>; |
| d-cache-block-size = <64>; |
| d-cache-size = <65536>; |
| d-cache-sets = <512>; |
| next-level-cache = <&l2_cache11>; |
| mmu-type = "riscv,sv39"; |
| |
| cpu52_intc: interrupt-controller { |
| compatible = "riscv,cpu-intc"; |
| interrupt-controller; |
| #interrupt-cells = <1>; |
| }; |
| }; |
| |
| cpu53: cpu@53 { |
| compatible = "thead,c920", "riscv"; |
| device_type = "cpu"; |
| riscv,isa = "rv64imafdc"; |
| riscv,isa-base = "rv64i"; |
| riscv,isa-extensions = "i", "m", "a", "f", "d", "c", |
| "zicntr", "zicsr", "zifencei", |
| "zihpm"; |
| reg = <53>; |
| i-cache-block-size = <64>; |
| i-cache-size = <65536>; |
| i-cache-sets = <512>; |
| d-cache-block-size = <64>; |
| d-cache-size = <65536>; |
| d-cache-sets = <512>; |
| next-level-cache = <&l2_cache11>; |
| mmu-type = "riscv,sv39"; |
| |
| cpu53_intc: interrupt-controller { |
| compatible = "riscv,cpu-intc"; |
| interrupt-controller; |
| #interrupt-cells = <1>; |
| }; |
| }; |
| |
| cpu54: cpu@54 { |
| compatible = "thead,c920", "riscv"; |
| device_type = "cpu"; |
| riscv,isa = "rv64imafdc"; |
| riscv,isa-base = "rv64i"; |
| riscv,isa-extensions = "i", "m", "a", "f", "d", "c", |
| "zicntr", "zicsr", "zifencei", |
| "zihpm"; |
| reg = <54>; |
| i-cache-block-size = <64>; |
| i-cache-size = <65536>; |
| i-cache-sets = <512>; |
| d-cache-block-size = <64>; |
| d-cache-size = <65536>; |
| d-cache-sets = <512>; |
| next-level-cache = <&l2_cache11>; |
| mmu-type = "riscv,sv39"; |
| |
| cpu54_intc: interrupt-controller { |
| compatible = "riscv,cpu-intc"; |
| interrupt-controller; |
| #interrupt-cells = <1>; |
| }; |
| }; |
| |
| cpu55: cpu@55 { |
| compatible = "thead,c920", "riscv"; |
| device_type = "cpu"; |
| riscv,isa = "rv64imafdc"; |
| riscv,isa-base = "rv64i"; |
| riscv,isa-extensions = "i", "m", "a", "f", "d", "c", |
| "zicntr", "zicsr", "zifencei", |
| "zihpm"; |
| reg = <55>; |
| i-cache-block-size = <64>; |
| i-cache-size = <65536>; |
| i-cache-sets = <512>; |
| d-cache-block-size = <64>; |
| d-cache-size = <65536>; |
| d-cache-sets = <512>; |
| next-level-cache = <&l2_cache11>; |
| mmu-type = "riscv,sv39"; |
| |
| cpu55_intc: interrupt-controller { |
| compatible = "riscv,cpu-intc"; |
| interrupt-controller; |
| #interrupt-cells = <1>; |
| }; |
| }; |
| |
| cpu56: cpu@56 { |
| compatible = "thead,c920", "riscv"; |
| device_type = "cpu"; |
| riscv,isa = "rv64imafdc"; |
| riscv,isa-base = "rv64i"; |
| riscv,isa-extensions = "i", "m", "a", "f", "d", "c", |
| "zicntr", "zicsr", "zifencei", |
| "zihpm"; |
| reg = <56>; |
| i-cache-block-size = <64>; |
| i-cache-size = <65536>; |
| i-cache-sets = <512>; |
| d-cache-block-size = <64>; |
| d-cache-size = <65536>; |
| d-cache-sets = <512>; |
| next-level-cache = <&l2_cache14>; |
| mmu-type = "riscv,sv39"; |
| |
| cpu56_intc: interrupt-controller { |
| compatible = "riscv,cpu-intc"; |
| interrupt-controller; |
| #interrupt-cells = <1>; |
| }; |
| }; |
| |
| cpu57: cpu@57 { |
| compatible = "thead,c920", "riscv"; |
| device_type = "cpu"; |
| riscv,isa = "rv64imafdc"; |
| riscv,isa-base = "rv64i"; |
| riscv,isa-extensions = "i", "m", "a", "f", "d", "c", |
| "zicntr", "zicsr", "zifencei", |
| "zihpm"; |
| reg = <57>; |
| i-cache-block-size = <64>; |
| i-cache-size = <65536>; |
| i-cache-sets = <512>; |
| d-cache-block-size = <64>; |
| d-cache-size = <65536>; |
| d-cache-sets = <512>; |
| next-level-cache = <&l2_cache14>; |
| mmu-type = "riscv,sv39"; |
| |
| cpu57_intc: interrupt-controller { |
| compatible = "riscv,cpu-intc"; |
| interrupt-controller; |
| #interrupt-cells = <1>; |
| }; |
| }; |
| |
| cpu58: cpu@58 { |
| compatible = "thead,c920", "riscv"; |
| device_type = "cpu"; |
| riscv,isa = "rv64imafdc"; |
| riscv,isa-base = "rv64i"; |
| riscv,isa-extensions = "i", "m", "a", "f", "d", "c", |
| "zicntr", "zicsr", "zifencei", |
| "zihpm"; |
| reg = <58>; |
| i-cache-block-size = <64>; |
| i-cache-size = <65536>; |
| i-cache-sets = <512>; |
| d-cache-block-size = <64>; |
| d-cache-size = <65536>; |
| d-cache-sets = <512>; |
| next-level-cache = <&l2_cache14>; |
| mmu-type = "riscv,sv39"; |
| |
| cpu58_intc: interrupt-controller { |
| compatible = "riscv,cpu-intc"; |
| interrupt-controller; |
| #interrupt-cells = <1>; |
| }; |
| }; |
| |
| cpu59: cpu@59 { |
| compatible = "thead,c920", "riscv"; |
| device_type = "cpu"; |
| riscv,isa = "rv64imafdc"; |
| riscv,isa-base = "rv64i"; |
| riscv,isa-extensions = "i", "m", "a", "f", "d", "c", |
| "zicntr", "zicsr", "zifencei", |
| "zihpm"; |
| reg = <59>; |
| i-cache-block-size = <64>; |
| i-cache-size = <65536>; |
| i-cache-sets = <512>; |
| d-cache-block-size = <64>; |
| d-cache-size = <65536>; |
| d-cache-sets = <512>; |
| next-level-cache = <&l2_cache14>; |
| mmu-type = "riscv,sv39"; |
| |
| cpu59_intc: interrupt-controller { |
| compatible = "riscv,cpu-intc"; |
| interrupt-controller; |
| #interrupt-cells = <1>; |
| }; |
| }; |
| |
| cpu60: cpu@60 { |
| compatible = "thead,c920", "riscv"; |
| device_type = "cpu"; |
| riscv,isa = "rv64imafdc"; |
| riscv,isa-base = "rv64i"; |
| riscv,isa-extensions = "i", "m", "a", "f", "d", "c", |
| "zicntr", "zicsr", "zifencei", |
| "zihpm"; |
| reg = <60>; |
| i-cache-block-size = <64>; |
| i-cache-size = <65536>; |
| i-cache-sets = <512>; |
| d-cache-block-size = <64>; |
| d-cache-size = <65536>; |
| d-cache-sets = <512>; |
| next-level-cache = <&l2_cache15>; |
| mmu-type = "riscv,sv39"; |
| |
| cpu60_intc: interrupt-controller { |
| compatible = "riscv,cpu-intc"; |
| interrupt-controller; |
| #interrupt-cells = <1>; |
| }; |
| }; |
| |
| cpu61: cpu@61 { |
| compatible = "thead,c920", "riscv"; |
| device_type = "cpu"; |
| riscv,isa = "rv64imafdc"; |
| riscv,isa-base = "rv64i"; |
| riscv,isa-extensions = "i", "m", "a", "f", "d", "c", |
| "zicntr", "zicsr", "zifencei", |
| "zihpm"; |
| reg = <61>; |
| i-cache-block-size = <64>; |
| i-cache-size = <65536>; |
| i-cache-sets = <512>; |
| d-cache-block-size = <64>; |
| d-cache-size = <65536>; |
| d-cache-sets = <512>; |
| next-level-cache = <&l2_cache15>; |
| mmu-type = "riscv,sv39"; |
| |
| cpu61_intc: interrupt-controller { |
| compatible = "riscv,cpu-intc"; |
| interrupt-controller; |
| #interrupt-cells = <1>; |
| }; |
| }; |
| |
| cpu62: cpu@62 { |
| compatible = "thead,c920", "riscv"; |
| device_type = "cpu"; |
| riscv,isa = "rv64imafdc"; |
| riscv,isa-base = "rv64i"; |
| riscv,isa-extensions = "i", "m", "a", "f", "d", "c", |
| "zicntr", "zicsr", "zifencei", |
| "zihpm"; |
| reg = <62>; |
| i-cache-block-size = <64>; |
| i-cache-size = <65536>; |
| i-cache-sets = <512>; |
| d-cache-block-size = <64>; |
| d-cache-size = <65536>; |
| d-cache-sets = <512>; |
| next-level-cache = <&l2_cache15>; |
| mmu-type = "riscv,sv39"; |
| |
| cpu62_intc: interrupt-controller { |
| compatible = "riscv,cpu-intc"; |
| interrupt-controller; |
| #interrupt-cells = <1>; |
| }; |
| }; |
| |
| cpu63: cpu@63 { |
| compatible = "thead,c920", "riscv"; |
| device_type = "cpu"; |
| riscv,isa = "rv64imafdc"; |
| riscv,isa-base = "rv64i"; |
| riscv,isa-extensions = "i", "m", "a", "f", "d", "c", |
| "zicntr", "zicsr", "zifencei", |
| "zihpm"; |
| reg = <63>; |
| i-cache-block-size = <64>; |
| i-cache-size = <65536>; |
| i-cache-sets = <512>; |
| d-cache-block-size = <64>; |
| d-cache-size = <65536>; |
| d-cache-sets = <512>; |
| next-level-cache = <&l2_cache15>; |
| mmu-type = "riscv,sv39"; |
| |
| cpu63_intc: interrupt-controller { |
| compatible = "riscv,cpu-intc"; |
| interrupt-controller; |
| #interrupt-cells = <1>; |
| }; |
| }; |
| |
| l2_cache0: cache-controller-0 { |
| compatible = "cache"; |
| cache-block-size = <64>; |
| cache-level = <2>; |
| cache-size = <1048576>; |
| cache-sets = <1024>; |
| cache-unified; |
| }; |
| |
| l2_cache1: cache-controller-1 { |
| compatible = "cache"; |
| cache-block-size = <64>; |
| cache-level = <2>; |
| cache-size = <1048576>; |
| cache-sets = <1024>; |
| cache-unified; |
| }; |
| |
| l2_cache2: cache-controller-2 { |
| compatible = "cache"; |
| cache-block-size = <64>; |
| cache-level = <2>; |
| cache-size = <1048576>; |
| cache-sets = <1024>; |
| cache-unified; |
| }; |
| |
| l2_cache3: cache-controller-3 { |
| compatible = "cache"; |
| cache-block-size = <64>; |
| cache-level = <2>; |
| cache-size = <1048576>; |
| cache-sets = <1024>; |
| cache-unified; |
| }; |
| |
| l2_cache4: cache-controller-4 { |
| compatible = "cache"; |
| cache-block-size = <64>; |
| cache-level = <2>; |
| cache-size = <1048576>; |
| cache-sets = <1024>; |
| cache-unified; |
| }; |
| |
| l2_cache5: cache-controller-5 { |
| compatible = "cache"; |
| cache-block-size = <64>; |
| cache-level = <2>; |
| cache-size = <1048576>; |
| cache-sets = <1024>; |
| cache-unified; |
| }; |
| |
| l2_cache6: cache-controller-6 { |
| compatible = "cache"; |
| cache-block-size = <64>; |
| cache-level = <2>; |
| cache-size = <1048576>; |
| cache-sets = <1024>; |
| cache-unified; |
| }; |
| |
| l2_cache7: cache-controller-7 { |
| compatible = "cache"; |
| cache-block-size = <64>; |
| cache-level = <2>; |
| cache-size = <1048576>; |
| cache-sets = <1024>; |
| cache-unified; |
| }; |
| |
| l2_cache8: cache-controller-8 { |
| compatible = "cache"; |
| cache-block-size = <64>; |
| cache-level = <2>; |
| cache-size = <1048576>; |
| cache-sets = <1024>; |
| cache-unified; |
| }; |
| |
| l2_cache9: cache-controller-9 { |
| compatible = "cache"; |
| cache-block-size = <64>; |
| cache-level = <2>; |
| cache-size = <1048576>; |
| cache-sets = <1024>; |
| cache-unified; |
| }; |
| |
| l2_cache10: cache-controller-10 { |
| compatible = "cache"; |
| cache-block-size = <64>; |
| cache-level = <2>; |
| cache-size = <1048576>; |
| cache-sets = <1024>; |
| cache-unified; |
| }; |
| |
| l2_cache11: cache-controller-11 { |
| compatible = "cache"; |
| cache-block-size = <64>; |
| cache-level = <2>; |
| cache-size = <1048576>; |
| cache-sets = <1024>; |
| cache-unified; |
| }; |
| |
| l2_cache12: cache-controller-12 { |
| compatible = "cache"; |
| cache-block-size = <64>; |
| cache-level = <2>; |
| cache-size = <1048576>; |
| cache-sets = <1024>; |
| cache-unified; |
| }; |
| |
| l2_cache13: cache-controller-13 { |
| compatible = "cache"; |
| cache-block-size = <64>; |
| cache-level = <2>; |
| cache-size = <1048576>; |
| cache-sets = <1024>; |
| cache-unified; |
| }; |
| |
| l2_cache14: cache-controller-14 { |
| compatible = "cache"; |
| cache-block-size = <64>; |
| cache-level = <2>; |
| cache-size = <1048576>; |
| cache-sets = <1024>; |
| cache-unified; |
| }; |
| |
| l2_cache15: cache-controller-15 { |
| compatible = "cache"; |
| cache-block-size = <64>; |
| cache-level = <2>; |
| cache-size = <1048576>; |
| cache-sets = <1024>; |
| cache-unified; |
| }; |
| }; |
| }; |
