| /* SPDX-License-Identifier: GPL-2.0 */ |
| /* |
| * Copyright (c) 2017, The Linux Foundation. All rights reserved. |
| */ |
| |
| #ifndef QCOM_PHY_QMP_PCS_PCIE_V4_H_ |
| #define QCOM_PHY_QMP_PCS_PCIE_V4_H_ |
| |
| /* Only for QMP V4 PHY - PCS_PCIE registers (same as PCS_MISC?) */ |
| #define QPHY_V4_PCS_PCIE_INT_AUX_CLK_STATUS 0x00 |
| #define QPHY_V4_PCS_PCIE_OSC_DTCT_STATUS 0x04 |
| #define QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG1 0x08 |
| #define QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2 0x0c |
| #define QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG3 0x10 |
| #define QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4 0x14 |
| #define QPHY_V4_PCS_PCIE_PCS_TX_RX_CONFIG 0x18 |
| #define QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x1c |
| #define QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_CNTRL 0x20 |
| #define QPHY_V4_PCS_PCIE_EPCLK_PRE_PLL_LOCK_DLY_AUXCLK 0x24 |
| #define QPHY_V4_PCS_PCIE_EPCLK_DLY_COUNT_VAL_L 0x28 |
| #define QPHY_V4_PCS_PCIE_EPCLK_DLY_COUNT_VAL_H 0x2c |
| #define QPHY_V4_PCS_PCIE_RX_IDLE_DTCT_CNTRL1 0x30 |
| #define QPHY_V4_PCS_PCIE_RX_IDLE_DTCT_CNTRL2 0x34 |
| #define QPHY_V4_PCS_PCIE_SIGDET_CNTRL 0x38 |
| #define QPHY_V4_PCS_PCIE_SIGDET_LOW_2_IDLE_TIME 0x3c |
| #define QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L 0x40 |
| #define QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H 0x44 |
| #define QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L 0x48 |
| #define QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H 0x4c |
| #define QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1 0x50 |
| #define QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG2 0x54 |
| #define QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG1 0x58 |
| #define QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG2 0x5c |
| #define QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG3 0x60 |
| #define QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG4 0x64 |
| #define QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG5 0x68 |
| #define QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG6 0x6c |
| #define QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG7 0x70 |
| #define QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG1 0x74 |
| #define QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG2 0x78 |
| #define QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG3 0x7c |
| #define QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG4 0x80 |
| #define QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5 0x84 |
| #define QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG6 0x88 |
| #define QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG7 0x8c |
| #define QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS 0x90 |
| #define QPHY_V4_PCS_PCIE_LOCAL_FS 0x94 |
| #define QPHY_V4_PCS_PCIE_LOCAL_LF 0x98 |
| #define QPHY_V4_PCS_PCIE_LOCAL_FS_RS 0x9c |
| #define QPHY_V4_PCS_PCIE_EQ_CONFIG1 0xa0 |
| #define QPHY_V4_PCS_PCIE_EQ_CONFIG2 0xa4 |
| #define QPHY_V4_PCS_PCIE_PRESET_P0_P1_PRE 0xa8 |
| #define QPHY_V4_PCS_PCIE_PRESET_P2_P3_PRE 0xac |
| #define QPHY_V4_PCS_PCIE_PRESET_P4_P5_PRE 0xb0 |
| #define QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE 0xb4 |
| #define QPHY_V4_PCS_PCIE_PRESET_P8_P9_PRE 0xb8 |
| #define QPHY_V4_PCS_PCIE_PRESET_P10_PRE 0xbc |
| #define QPHY_V4_PCS_PCIE_PRESET_P1_P3_PRE_RS 0xc0 |
| #define QPHY_V4_PCS_PCIE_PRESET_P4_P5_PRE_RS 0xc4 |
| #define QPHY_V4_PCS_PCIE_PRESET_P6_P9_PRE_RS 0xc8 |
| #define QPHY_V4_PCS_PCIE_PRESET_P0_P1_POST 0xcc |
| #define QPHY_V4_PCS_PCIE_PRESET_P2_P3_POST 0xd0 |
| #define QPHY_V4_PCS_PCIE_PRESET_P4_P5_POST 0xd4 |
| #define QPHY_V4_PCS_PCIE_PRESET_P6_P7_POST 0xd8 |
| #define QPHY_V4_PCS_PCIE_PRESET_P8_P9_POST 0xdc |
| #define QPHY_V4_PCS_PCIE_PRESET_P10_POST 0xe0 |
| #define QPHY_V4_PCS_PCIE_PRESET_P1_P3_POST_RS 0xe4 |
| #define QPHY_V4_PCS_PCIE_PRESET_P4_P5_POST_RS 0xe8 |
| #define QPHY_V4_PCS_PCIE_PRESET_P6_P9_POST_RS 0xec |
| #define QPHY_V4_PCS_PCIE_RXEQEVAL_TIME 0xf0 |
| |
| #endif |
